Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Please do not download this program if you are expecting a full featured replacement for NC-Verilog, VCS or another commercial Verilog simulator or Verilog compiler for a little project! (Try Icarus instead.) However, if you are looking for a path to migrate synthesizable Verilog to C++ or SystemC, and writing just a touch of C code and Makefiles doesn't scare you off, this is the free Verilog compiler for you. Verilator supports the synthesis subset of Verilog, plus initial statements, proper blocking/non-blocking assignments, functions, tasks, multi-dimensional arrays, and signed numbers. It also supports very simple forms of SystemVerilog assertions and coverage analysis. Verilator supports the more important Verilog 2001 constructs, with additional constructs and SystemVerilog support added as users request them. Verilator has been used to simulate many very large multi-million gate designs with thousands of modules. HOMEPAGE: http://www.veripool.org/wiki/verilator Reproducible: Always
Created attachment 262561 [details] verilator-9999.ebuild I quickly write this ebuild, however I don't know what package I need to add in DEPEND
Please stop CC'ing random arches.
Created attachment 304601 [details] EAPI=4 version verilator-9999.ebuild FYI, i made EAPI=4 version and it just works on ~ppc too.
The bug has been closed via the following commit(s): https://gitweb.gentoo.org/repo/proj/guru.git/commit/?id=03fda63eacc4df3eb7217a3e8d68dbb2c6754af7 commit 03fda63eacc4df3eb7217a3e8d68dbb2c6754af7 Author: Huang Rui <vowstar@gmail.com> AuthorDate: 2020-02-23 06:51:23 +0000 Commit: Huang Rui <vowstar@gmail.com> CommitDate: 2020-02-23 06:51:53 +0000 sci-electronics/verilator: new package 4.026 The fast free Verilog/SystemVerilog simulator Closes: https://bugs.gentoo.org/354957 Package-Manager: Portage-2.3.89, Repoman-2.3.20 Signed-off-by: Huang Rui <vowstar@gmail.com> sci-electronics/verilator/Manifest | 1 + sci-electronics/verilator/metadata.xml | 19 ++++++++++++ sci-electronics/verilator/verilator-4.026.ebuild | 39 ++++++++++++++++++++++++ 3 files changed, 59 insertions(+)
