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(-)verilog-0.8.6/elab_net.cc (+1 lines)
Lines 28-33 Link Here
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# include  "compiler.h"
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# include  "compiler.h"
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# include  <iostream>
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# include  <iostream>
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# include  <cstring>
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/*
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/*
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 * This is a state flag that determines whether an elaborate_net must
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 * This is a state flag that determines whether an elaborate_net must
(-)verilog-0.8.6/elab_scope.cc (+1 lines)
Lines 24-29 Link Here
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# include  "compiler.h"
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# include  "compiler.h"
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# include  <iostream>
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# include  <iostream>
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# include  <stdio.h>
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# include  <stdio.h>
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# include  <cstring>
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/*
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/*
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 * Elaboration happens in two passes, generally. The first scans the
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 * Elaboration happens in two passes, generally. The first scans the
(-)verilog-0.8.6/elab_sig.cc (+1 lines)
Lines 23-28 Link Here
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# include "config.h"
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# include "config.h"
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# include  <iostream>
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# include  <iostream>
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# include  <cstdlib>
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# include  "Module.h"
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# include  "Module.h"
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# include  "PExpr.h"
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# include  "PExpr.h"
(-)verilog-0.8.6/emit.cc (+1 lines)
Lines 32-37 Link Here
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# include  "netlist.h"
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# include  "netlist.h"
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# include  <typeinfo>
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# include  <typeinfo>
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# include  <cassert>
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# include  <cassert>
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# include  <cstring>
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bool NetNode::emit_node(struct target_t*tgt) const
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bool NetNode::emit_node(struct target_t*tgt) const
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{
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{
(-)verilog-0.8.6/load_module.cc (+2 lines)
Lines 31-36 Link Here
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# include  <dirent.h>
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# include  <dirent.h>
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# include  <ctype.h>
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# include  <ctype.h>
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# include  <assert.h>
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# include  <assert.h>
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# include  <cstdlib>
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# include  <cstring>
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/*
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/*
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 * The module library items are maps of key names to file name within
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 * The module library items are maps of key names to file name within
(-)verilog-0.8.6/net_design.cc (+1 lines)
Lines 33-38 Link Here
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# include  "util.h"
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# include  "util.h"
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# include  "compiler.h"
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# include  "compiler.h"
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# include  <sstream>
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# include  <sstream>
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# include  <cstring>
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Design:: Design()
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Design:: Design()
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: errors(0), nodes_(0), procs_(0), lcounter_(0)
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: errors(0), nodes_(0), procs_(0), lcounter_(0)
(-)verilog-0.8.6/net_link.cc (+1 lines)
Lines 27-32 Link Here
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# include  "netlist.h"
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# include  "netlist.h"
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# include  <sstream>
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# include  <sstream>
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# include  <string>
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# include  <string>
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# include  <cstring>
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# include  <typeinfo>
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# include  <typeinfo>
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#ifdef HAVE_MALLOC_H
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#ifdef HAVE_MALLOC_H
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# include  <malloc.h>
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# include  <malloc.h>
(-)verilog-0.8.6/net_scope.cc (+1 lines)
Lines 25-30 Link Here
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# include  "netlist.h"
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# include  "netlist.h"
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# include  <sstream>
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# include  <sstream>
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# include  <cstring>
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/*
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/*
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 * The NetScope class keeps a scope tree organized. Each node of the
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 * The NetScope class keeps a scope tree organized. Each node of the
(-)verilog-0.8.6/pform.h (+2 lines)
Lines 37-42 Link Here
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# include  <string>
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# include  <string>
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# include  <list>
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# include  <list>
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# include  <stdio.h>
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# include  <stdio.h>
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# include  <cstring>
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# include  <cstdlib>
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/*
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/*
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 * These classes implement the parsed form (P-form for short) of the
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 * These classes implement the parsed form (P-form for short) of the
(-)verilog-0.8.6/synth2.cc (+1 lines)
Lines 28-33 Link Here
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#include <cassert>
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#include <cassert>
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#include "NetLatch.h"
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#include "NetLatch.h"
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#include <climits>
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#include <climits>
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#include <cstdlib>
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#include <new> // standard operator new
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#include <new> // standard operator new
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using std::bad_alloc;
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using std::bad_alloc;
(-)verilog-0.8.6/sys_funcs.cc (+2 lines)
Lines 23-28 Link Here
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# include  "config.h"
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# include  "config.h"
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# include  "compiler.h"
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# include  "compiler.h"
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# include  <stdio.h>
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# include  <stdio.h>
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# include  <cstdlib>
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# include  <cstring>
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/*
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/*
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 * Manage the information about system functions. This information is
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 * Manage the information about system functions. This information is
(-)verilog-0.8.6/t-dll.cc (-1 / +2 lines)
Lines 31-37 Link Here
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#ifdef HAVE_MALLOC_H
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#ifdef HAVE_MALLOC_H
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# include  <malloc.h>
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# include  <malloc.h>
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#endif
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#endif
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# include  <stdlib.h>
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# include  <cstdlib>
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# include  <cstring>
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#include <new> // standard operator new
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#include <new> // standard operator new
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using std::bad_alloc;
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using std::bad_alloc;
(-)verilog-0.8.6/t-dll-expr.cc (-1 / +2 lines)
Lines 30-36 Link Here
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#ifdef HAVE_MALLOC_H
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#ifdef HAVE_MALLOC_H
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# include  <malloc.h>
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# include  <malloc.h>
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#endif
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#endif
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# include  <stdlib.h>
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# include  <cstdlib>
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# include  <cstring>
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/*
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/*
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 * This is a little convenience function for converting a NetExpr
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 * This is a little convenience function for converting a NetExpr
(-)verilog-0.8.6/t-dll-proc.cc (-1 / +2 lines)
Lines 32-38 Link Here
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#ifdef HAVE_MALLOC_H
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#ifdef HAVE_MALLOC_H
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# include  <malloc.h>
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# include  <malloc.h>
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#endif
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#endif
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# include  <stdlib.h>
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# include  <cstdlib>
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# include  <cstring>
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bool dll_target::process(const NetProcTop*net)
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bool dll_target::process(const NetProcTop*net)
(-)verilog-0.8.6/verireal.cc (-1 / +2 lines)
Lines 24-30 Link Here
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# include  "verireal.h"
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# include  "verireal.h"
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# include  "verinum.h"
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# include  "verinum.h"
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# include  <stdlib.h>
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# include  <cstdlib>
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# include  <cstring>
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# include  <ctype.h>
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# include  <ctype.h>
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# include  <iostream>
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# include  <iostream>
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# include  <math.h>
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# include  <math.h>

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