Lines 100-105
Link Here
|
100 |
{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } |
100 |
{ PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) } |
101 |
|
101 |
|
102 |
static struct pci_device_id radeonfb_pci_table[] = { |
102 |
static struct pci_device_id radeonfb_pci_table[] = { |
|
|
103 |
/* Radeon Xpress 200m */ |
104 |
CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY), |
103 |
/* Mobility M6 */ |
105 |
/* Mobility M6 */ |
104 |
CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), |
106 |
CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), |
105 |
CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), |
107 |
CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY), |
Lines 268-273
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|
268 |
#endif |
270 |
#endif |
269 |
static int force_sleep; |
271 |
static int force_sleep; |
270 |
static int ignore_devlist; |
272 |
static int ignore_devlist; |
|
|
273 |
#ifdef CONFIG_PMAC_BACKLIGHT |
274 |
static int backlight = 1; |
275 |
#else |
276 |
static int backlight = 0; |
277 |
#endif |
271 |
|
278 |
|
272 |
/* |
279 |
/* |
273 |
* prototypes |
280 |
* prototypes |
Lines 575-580
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|
575 |
return 0; |
582 |
return 0; |
576 |
} |
583 |
} |
577 |
|
584 |
|
|
|
585 |
static void radeon_detect_bios_type(struct radeonfb_info *rinfo) |
586 |
{ |
587 |
#ifndef CONFIG_PPC_OF |
588 |
int offset = rinfo->fp_bios_start + 4; |
589 |
unsigned char sign[4]; |
590 |
|
591 |
sign[0] = BIOS_IN8(offset); |
592 |
sign[1] = BIOS_IN8(offset + 1); |
593 |
sign[2] = BIOS_IN8(offset + 2); |
594 |
sign[3] = BIOS_IN8(offset + 3); |
595 |
|
596 |
if (!memcmp(sign, "ATOM", 4) || !memcmp(sign, "MOTA", 4)) { |
597 |
rinfo->is_atom_bios = 1; |
598 |
rinfo->atom_data_start = BIOS_IN16(rinfo->fp_bios_start + 32); |
599 |
|
600 |
printk(KERN_INFO "radeonfb: ATOM BIOS signature found\n"); |
601 |
|
602 |
return; |
603 |
} |
604 |
#endif /* NOT CONFIG_PPC_OF */ |
605 |
|
606 |
rinfo->is_atom_bios = 0; |
607 |
|
608 |
return; |
609 |
} |
610 |
|
578 |
/* |
611 |
/* |
579 |
* Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) |
612 |
* Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...) |
580 |
*/ |
613 |
*/ |
Lines 651-670
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|
651 |
#endif /* CONFIG_PPC_OF */ |
684 |
#endif /* CONFIG_PPC_OF */ |
652 |
|
685 |
|
653 |
/* |
686 |
/* |
654 |
* Check out if we have an X86 which gave us some PLL informations |
687 |
* Check out if we have an ATOM BIOS which gave us some PLL informations |
655 |
* and if yes, retrieve them |
688 |
* and if yes, retrieve them |
656 |
*/ |
689 |
*/ |
|
|
690 |
|
657 |
if (!force_measure_pll && rinfo->bios_seg) { |
691 |
if (!force_measure_pll && rinfo->bios_seg) { |
658 |
u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); |
692 |
u16 pll_info_block; |
659 |
|
693 |
|
660 |
rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); |
694 |
if(rinfo->is_atom_bios) { |
661 |
rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); |
695 |
pll_info_block = BIOS_IN16(rinfo->atom_data_start + 12); |
662 |
rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); |
|
|
663 |
rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); |
664 |
rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); |
665 |
rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); |
666 |
|
696 |
|
|
|
697 |
rinfo->pll.sclk = BIOS_IN32(pll_info_block + 8); |
698 |
rinfo->pll.mclk = BIOS_IN32(pll_info_block + 12); |
699 |
rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 82); |
700 |
rinfo->pll.ref_div = 0; /* Have to get it elsewhere */ |
701 |
rinfo->pll.ppll_min = BIOS_IN16(pll_info_block + 78); |
702 |
rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 32); |
703 |
} else { |
704 |
/* |
705 |
* Check out if we have an X86 which gave us some PLL informations |
706 |
* and if yes, retrieve them |
707 |
*/ |
708 |
pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30); |
709 |
|
710 |
rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08); |
711 |
rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a); |
712 |
rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e); |
713 |
rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); |
714 |
rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12); |
715 |
rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16); |
716 |
} |
667 |
printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); |
717 |
printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n"); |
|
|
718 |
|
668 |
goto found; |
719 |
goto found; |
669 |
} |
720 |
} |
670 |
|
721 |
|
Lines 680-697
Link Here
|
680 |
/* |
731 |
/* |
681 |
* Fall back to already-set defaults... |
732 |
* Fall back to already-set defaults... |
682 |
*/ |
733 |
*/ |
683 |
printk(KERN_INFO "radeonfb: Used default PLL infos\n"); |
734 |
printk(KERN_INFO "radeonfb: Fall back to default PLL infos\n"); |
684 |
|
735 |
|
685 |
found: |
736 |
found: |
|
|
737 |
/* Check and fix-up the PLL divisor if necessary */ |
738 |
if (rinfo->pll.ref_div < 2) { |
739 |
int tmp = INPLL(PPLL_REF_DIV); |
740 |
if (rinfo->family == CHIP_FAMILY_RS300) { |
741 |
rinfo->pll.ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT; |
742 |
} else { |
743 |
rinfo->pll.ref_div = tmp & PPLL_REF_DIV_MASK; |
744 |
} |
745 |
|
746 |
/* Sane default */ |
747 |
if (rinfo->pll.ref_div < 2) { |
748 |
printk(KERN_INFO "radeonfb: Set a sane default PLL divisor\n"); |
749 |
rinfo->pll.ref_div = 12; |
750 |
} |
751 |
} |
752 |
|
686 |
/* |
753 |
/* |
687 |
* Some methods fail to retrieve SCLK and MCLK values, we apply default |
754 |
* Some methods fail to retrieve SCLK and MCLK values, we apply default |
688 |
* settings in this case (200Mhz). If that really happne often, we could |
755 |
* settings in this case (200Mhz). If that really happen often, we could |
689 |
* fetch from registers instead... |
756 |
* fetch from registers instead... |
690 |
*/ |
757 |
*/ |
691 |
if (rinfo->pll.mclk == 0) |
758 |
if (rinfo->pll.mclk == 0) { |
|
|
759 |
printk(KERN_INFO "radeonfb: Set a sane default MCLK value\n"); |
692 |
rinfo->pll.mclk = 20000; |
760 |
rinfo->pll.mclk = 20000; |
693 |
if (rinfo->pll.sclk == 0) |
761 |
} |
|
|
762 |
if (rinfo->pll.mclk == 0) { |
763 |
printk(KERN_INFO "radeonfb: Set a sane default SCLK value\n"); |
694 |
rinfo->pll.sclk = 20000; |
764 |
rinfo->pll.sclk = 20000; |
|
|
765 |
} |
695 |
|
766 |
|
696 |
printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", |
767 |
printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n", |
697 |
rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, |
768 |
rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100, |
Lines 1026-1033
Link Here
|
1026 |
break; |
1097 |
break; |
1027 |
} |
1098 |
} |
1028 |
|
1099 |
|
1029 |
/* let fbcon do a soft blank for us */ |
1100 |
return 0; |
1030 |
return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0; |
|
|
1031 |
} |
1101 |
} |
1032 |
|
1102 |
|
1033 |
static int radeonfb_blank (int blank, struct fb_info *info) |
1103 |
static int radeonfb_blank (int blank, struct fb_info *info) |
Lines 1990-1996
Link Here
|
1990 |
/* framebuffer size */ |
2060 |
/* framebuffer size */ |
1991 |
if ((rinfo->family == CHIP_FAMILY_RS100) || |
2061 |
if ((rinfo->family == CHIP_FAMILY_RS100) || |
1992 |
(rinfo->family == CHIP_FAMILY_RS200) || |
2062 |
(rinfo->family == CHIP_FAMILY_RS200) || |
1993 |
(rinfo->family == CHIP_FAMILY_RS300)) { |
2063 |
(rinfo->family == CHIP_FAMILY_RS300) || |
|
|
2064 |
(rinfo->family == CHIP_FAMILY_RS480) ) { |
1994 |
u32 tom = INREG(NB_TOM); |
2065 |
u32 tom = INREG(NB_TOM); |
1995 |
tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); |
2066 |
tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); |
1996 |
|
2067 |
|
Lines 2295-2300
Link Here
|
2295 |
if (rinfo->bios_seg == NULL && rinfo->is_mobility) |
2366 |
if (rinfo->bios_seg == NULL && rinfo->is_mobility) |
2296 |
radeon_map_ROM(rinfo, pdev); |
2367 |
radeon_map_ROM(rinfo, pdev); |
2297 |
|
2368 |
|
|
|
2369 |
/* Check BIOS Type */ |
2370 |
radeon_detect_bios_type(rinfo); |
2371 |
|
2298 |
/* Get informations about the board's PLL */ |
2372 |
/* Get informations about the board's PLL */ |
2299 |
radeon_get_pllinfo(rinfo); |
2373 |
radeon_get_pllinfo(rinfo); |
2300 |
|
2374 |
|
Lines 2349-2355
Link Here
|
2349 |
MTRR_TYPE_WRCOMB, 1); |
2423 |
MTRR_TYPE_WRCOMB, 1); |
2350 |
#endif |
2424 |
#endif |
2351 |
|
2425 |
|
2352 |
radeonfb_bl_init(rinfo); |
2426 |
if (backlight) |
|
|
2427 |
radeonfb_bl_init(rinfo); |
2353 |
|
2428 |
|
2354 |
printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); |
2429 |
printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name); |
2355 |
|
2430 |
|
Lines 2393-2399
Link Here
|
2393 |
if (!rinfo) |
2468 |
if (!rinfo) |
2394 |
return; |
2469 |
return; |
2395 |
|
2470 |
|
2396 |
radeonfb_bl_exit(rinfo); |
|
|
2397 |
radeonfb_pm_exit(rinfo); |
2471 |
radeonfb_pm_exit(rinfo); |
2398 |
|
2472 |
|
2399 |
if (rinfo->mon1_EDID) |
2473 |
if (rinfo->mon1_EDID) |
Lines 2420-2425
Link Here
|
2420 |
|
2494 |
|
2421 |
unregister_framebuffer(info); |
2495 |
unregister_framebuffer(info); |
2422 |
|
2496 |
|
|
|
2497 |
radeonfb_bl_exit(rinfo); |
2498 |
|
2423 |
iounmap(rinfo->mmio_base); |
2499 |
iounmap(rinfo->mmio_base); |
2424 |
iounmap(rinfo->fb_base); |
2500 |
iounmap(rinfo->fb_base); |
2425 |
|
2501 |
|
Lines 2469-2474
Link Here
|
2469 |
force_dfp = 1; |
2545 |
force_dfp = 1; |
2470 |
} else if (!strncmp(this_opt, "panel_yres:", 11)) { |
2546 |
} else if (!strncmp(this_opt, "panel_yres:", 11)) { |
2471 |
panel_yres = simple_strtoul((this_opt+11), NULL, 0); |
2547 |
panel_yres = simple_strtoul((this_opt+11), NULL, 0); |
|
|
2548 |
} else if (!strncmp(this_opt, "backlight:", 10)) { |
2549 |
backlight = simple_strtoul(this_opt+10, NULL, 0); |
2472 |
#ifdef CONFIG_MTRR |
2550 |
#ifdef CONFIG_MTRR |
2473 |
} else if (!strncmp(this_opt, "nomtrr", 6)) { |
2551 |
} else if (!strncmp(this_opt, "nomtrr", 6)) { |
2474 |
nomtrr = 1; |
2552 |
nomtrr = 1; |