|
Lines 1342-1347
static void genesis_stop(struct skge_por
Link Here
|
| 1342 |
int port = skge->port; |
1342 |
int port = skge->port; |
| 1343 |
u32 reg; |
1343 |
u32 reg; |
| 1344 |
|
1344 |
|
|
|
1345 |
genesis_reset(hw, port); |
| 1346 |
|
| 1345 |
/* Clear Tx packet arbiter timeout IRQ */ |
1347 |
/* Clear Tx packet arbiter timeout IRQ */ |
| 1346 |
skge_write16(hw, B3_PA_CTRL, |
1348 |
skge_write16(hw, B3_PA_CTRL, |
| 1347 |
port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); |
1349 |
port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); |
|
Lines 1679-1687
static void yukon_mac_init(struct skge_h
Link Here
|
| 1679 |
|
1681 |
|
| 1680 |
/* WA code for COMA mode -- set PHY reset */ |
1682 |
/* WA code for COMA mode -- set PHY reset */ |
| 1681 |
if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1683 |
if (hw->chip_id == CHIP_ID_YUKON_LITE && |
| 1682 |
hw->chip_rev >= CHIP_REV_YU_LITE_A3) |
1684 |
hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
| 1683 |
skge_write32(hw, B2_GP_IO, |
1685 |
reg = skge_read32(hw, B2_GP_IO); |
| 1684 |
(skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9)); |
1686 |
reg |= GP_DIR_9 | GP_IO_9; |
|
|
1687 |
skge_write32(hw, B2_GP_IO, reg); |
| 1688 |
} |
| 1685 |
|
1689 |
|
| 1686 |
/* hard reset */ |
1690 |
/* hard reset */ |
| 1687 |
skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1691 |
skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
|
Lines 1689-1698
static void yukon_mac_init(struct skge_h
Link Here
|
| 1689 |
|
1693 |
|
| 1690 |
/* WA code for COMA mode -- clear PHY reset */ |
1694 |
/* WA code for COMA mode -- clear PHY reset */ |
| 1691 |
if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1695 |
if (hw->chip_id == CHIP_ID_YUKON_LITE && |
| 1692 |
hw->chip_rev >= CHIP_REV_YU_LITE_A3) |
1696 |
hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
| 1693 |
skge_write32(hw, B2_GP_IO, |
1697 |
reg = skge_read32(hw, B2_GP_IO); |
| 1694 |
(skge_read32(hw, B2_GP_IO) | GP_DIR_9) |
1698 |
reg |= GP_DIR_9; |
| 1695 |
& ~GP_IO_9); |
1699 |
reg &= ~GP_IO_9; |
|
|
1700 |
skge_write32(hw, B2_GP_IO, reg); |
| 1701 |
} |
| 1696 |
|
1702 |
|
| 1697 |
/* Set hardware config mode */ |
1703 |
/* Set hardware config mode */ |
| 1698 |
reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | |
1704 |
reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | |
|
Lines 1803-1822
static void yukon_stop(struct skge_port
Link Here
|
| 1803 |
struct skge_hw *hw = skge->hw; |
1809 |
struct skge_hw *hw = skge->hw; |
| 1804 |
int port = skge->port; |
1810 |
int port = skge->port; |
| 1805 |
|
1811 |
|
| 1806 |
if (hw->chip_id == CHIP_ID_YUKON_LITE && |
1812 |
skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
| 1807 |
hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1813 |
yukon_reset(hw, port); |
| 1808 |
skge_write32(hw, B2_GP_IO, |
|
|
| 1809 |
skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9); |
| 1810 |
} |
| 1811 |
|
1814 |
|
| 1812 |
gma_write16(hw, port, GM_GP_CTRL, |
1815 |
gma_write16(hw, port, GM_GP_CTRL, |
| 1813 |
gma_read16(hw, port, GM_GP_CTRL) |
1816 |
gma_read16(hw, port, GM_GP_CTRL) |
| 1814 |
& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
1817 |
& ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
| 1815 |
gma_read16(hw, port, GM_GP_CTRL); |
1818 |
gma_read16(hw, port, GM_GP_CTRL); |
| 1816 |
|
1819 |
|
|
|
1820 |
if (hw->chip_id == CHIP_ID_YUKON_LITE && |
| 1821 |
hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
| 1822 |
u32 io = skge_read32(hw, B2_GP_IO); |
| 1823 |
|
| 1824 |
io |= GP_DIR_9 | GP_IO_9; |
| 1825 |
skge_write32(hw, B2_GP_IO, io); |
| 1826 |
skge_read32(hw, B2_GP_IO); |
| 1827 |
} |
| 1828 |
|
| 1817 |
/* set GPHY Control reset */ |
1829 |
/* set GPHY Control reset */ |
| 1818 |
skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1830 |
skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
| 1819 |
skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1831 |
skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
| 1820 |
} |
1832 |
} |
| 1821 |
|
1833 |
|
| 1822 |
static void yukon_get_stats(struct skge_port *skge, u64 *data) |
1834 |
static void yukon_get_stats(struct skge_port *skge, u64 *data) |
|
Lines 2137-2151
static int skge_down(struct net_device *
Link Here
|
| 2137 |
|
2149 |
|
| 2138 |
netif_stop_queue(dev); |
2150 |
netif_stop_queue(dev); |
| 2139 |
|
2151 |
|
|
|
2152 |
skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
| 2153 |
if (hw->chip_id == CHIP_ID_GENESIS) |
| 2154 |
genesis_stop(skge); |
| 2155 |
else |
| 2156 |
yukon_stop(skge); |
| 2157 |
|
| 2158 |
hw->intr_mask &= ~portirqmask[skge->port]; |
| 2159 |
skge_write32(hw, B0_IMSK, hw->intr_mask); |
| 2160 |
|
| 2140 |
/* Stop transmitter */ |
2161 |
/* Stop transmitter */ |
| 2141 |
skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); |
2162 |
skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); |
| 2142 |
skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), |
2163 |
skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), |
| 2143 |
RB_RST_SET|RB_DIS_OP_MD); |
2164 |
RB_RST_SET|RB_DIS_OP_MD); |
| 2144 |
|
2165 |
|
| 2145 |
if (hw->chip_id == CHIP_ID_GENESIS) |
|
|
| 2146 |
genesis_stop(skge); |
| 2147 |
else |
| 2148 |
yukon_stop(skge); |
| 2149 |
|
2166 |
|
| 2150 |
/* Disable Force Sync bit and Enable Alloc bit */ |
2167 |
/* Disable Force Sync bit and Enable Alloc bit */ |
| 2151 |
skge_write8(hw, SK_REG(port, TXA_CTRL), |
2168 |
skge_write8(hw, SK_REG(port, TXA_CTRL), |
|
Lines 3229-3234
static void __devexit skge_remove(struct
Link Here
|
| 3229 |
dev0 = hw->dev[0]; |
3246 |
dev0 = hw->dev[0]; |
| 3230 |
unregister_netdev(dev0); |
3247 |
unregister_netdev(dev0); |
| 3231 |
|
3248 |
|
|
|
3249 |
skge_write32(hw, B0_IMSK, 0); |
| 3250 |
skge_write16(hw, B0_LED, LED_STAT_OFF); |
| 3251 |
skge_pci_clear(hw); |
| 3252 |
skge_write8(hw, B0_CTST, CS_RST_SET); |
| 3253 |
|
| 3232 |
tasklet_kill(&hw->ext_tasklet); |
3254 |
tasklet_kill(&hw->ext_tasklet); |
| 3233 |
|
3255 |
|
| 3234 |
free_irq(pdev->irq, hw); |
3256 |
free_irq(pdev->irq, hw); |
|
Lines 3237-3243
static void __devexit skge_remove(struct
Link Here
|
| 3237 |
if (dev1) |
3259 |
if (dev1) |
| 3238 |
free_netdev(dev1); |
3260 |
free_netdev(dev1); |
| 3239 |
free_netdev(dev0); |
3261 |
free_netdev(dev0); |
| 3240 |
skge_write16(hw, B0_LED, LED_STAT_OFF); |
3262 |
|
| 3241 |
iounmap(hw->regs); |
3263 |
iounmap(hw->regs); |
| 3242 |
kfree(hw); |
3264 |
kfree(hw); |
| 3243 |
pci_set_drvdata(pdev, NULL); |
3265 |
pci_set_drvdata(pdev, NULL); |
|
Lines 3256-3262
static int skge_suspend(struct pci_dev *
Link Here
|
| 3256 |
struct skge_port *skge = netdev_priv(dev); |
3278 |
struct skge_port *skge = netdev_priv(dev); |
| 3257 |
if (netif_running(dev)) { |
3279 |
if (netif_running(dev)) { |
| 3258 |
netif_carrier_off(dev); |
3280 |
netif_carrier_off(dev); |
| 3259 |
skge_down(dev); |
3281 |
if (skge->wol) |
|
|
3282 |
netif_stop_queue(dev); |
| 3283 |
else |
| 3284 |
skge_down(dev); |
| 3260 |
} |
3285 |
} |
| 3261 |
netif_device_detach(dev); |
3286 |
netif_device_detach(dev); |
| 3262 |
wol |= skge->wol; |
3287 |
wol |= skge->wol; |
