Attachment #224831 for bug #310079

View | Details | Raw Unified | Return to bug 310079
Collapse All | Expand All




   struct intel_context *intel = intel_context(ctx);
   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
   int cpp;
   GLuint pitch;

   ASSERT(rb->Name != 0);



   /* allocate new memory region/renderbuffer */

   /* Choose a pitch to match hardware requirements:
    */
   pitch = ((cpp * width + 63) & ~63) / cpp;

   /* alloc hardware renderbuffer */
   DBG("Allocating %d x %d Intel RBO\n", width, height);

   irb->region = intel_region_alloc(intel, I915_TILING_NONE, cpp,
				    width, height, GL_TRUE);
   if (!irb->region)
      return GL_FALSE;       /* out of memory? */





				   mt->cpp,
				   mt->pitch,
				   mt->total_height,
				   mt->pitch,
				   expect_accelerated_upload);
   mt->pitch = mt->region->pitch;

   if (!mt->region) {
       free(mt);

				      I915_TILING_NONE);
   if (!mt)
      return mt;

   if (mt->pitch != region->pitch) {
      fprintf(stderr,
	      "region pitch (%d) doesn't match mipmap tree pitch (%d)\n",
	      region->pitch, mt->pitch);
      free(mt);
      return NULL;
   }
#else
   /* The mipmap tree pitch is aligned to 64 bytes to make sure render
    * to texture works, but we don't need that for texturing from a
    * pixmap.  Just override it here. */
   mt->pitch = region->pitch;
#endif

   intel_region_reference(&mt->region, region);





struct intel_region *
intel_region_alloc(struct intel_context *intel,
		   uint32_t tiling,
                   GLuint cpp, GLuint width, GLuint height,
		   GLboolean expect_accelerated_upload)
{
   dri_bo *buffer;

   buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "region",
				     width, height, cpp,
				     &tiling, &aligned_pitch, flags);
   /* We've already chosen a pitch as part of miptree layout.  It had
    * better be the same.
    */
   assert(aligned_pitch == pitch * cpp);

   region = intel_region_alloc_internal(intel, cpp, width, height,
					aligned_pitch / cpp, buffer);

   if (tiling != I915_TILING_NONE) {
      assert((aligned_pitch & 127) == 0);
      drm_intel_bo_set_tiling(buffer, &tiling, aligned_pitch);
      drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
   }

Lines 79-85 struct intel_region Link Here

(-)a/src/mesa/drivers/dri/intel/intel_regions.h (-1 / +1 lines)
79	struct intel_region intel_region_alloc(struct intel_context intel,	79	struct intel_region intel_region_alloc(struct intel_context intel,
80	uint32_t tiling,	80	uint32_t tiling,
81	GLuint cpp, GLuint width,	81	GLuint cpp, GLuint width,
82	GLuint height, GLuint pitch,	82	GLuint height,
83	GLboolean expect_accelerated_upload);	83	GLboolean expect_accelerated_upload);
84		84
85	struct intel_region *	85	struct intel_region *

Return to bug 310079

Lines 104-110 intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, Link Here

(-)a/src/mesa/drivers/dri/intel/intel_fbo.c (-7 / +2 lines)
104	struct intel_context *intel = intel_context(ctx);	104	struct intel_context *intel = intel_context(ctx);
105	struct intel_renderbuffer *irb = intel_renderbuffer(rb);	105	struct intel_renderbuffer *irb = intel_renderbuffer(rb);
106	int cpp;	106	int cpp;
107	GLuint pitch;
108		107
109	ASSERT(rb->Name != 0);	108	ASSERT(rb->Name != 0);
110		109
Lines 176-190 intel_alloc_renderbuffer_storage(GLcontext * ctx, struct gl_renderbuffer *rb, Link Here
176		175
177	/* allocate new memory region/renderbuffer */	176	/* allocate new memory region/renderbuffer */
178		177
179	/* Choose a pitch to match hardware requirements:
180	*/
181	pitch = ((cpp * width + 63) & ~63) / cpp;
182
183	/* alloc hardware renderbuffer */	178	/* alloc hardware renderbuffer */
184	DBG("Allocating %d x %d Intel RBO (pitch %d)\n", width, height, pitch);	179	DBG("Allocating %d x %d Intel RBO\n", width, height);
185		180
186	irb->region = intel_region_alloc(intel, I915_TILING_NONE, cpp,	181	irb->region = intel_region_alloc(intel, I915_TILING_NONE, cpp,
187	width, height, pitch, GL_TRUE);	182	width, height, GL_TRUE);
188	if (!irb->region)	183	if (!irb->region)
189	return GL_FALSE; /* out of memory? */	184	return GL_FALSE; /* out of memory? */
190		185

Lines 146-153 intel_miptree_create(struct intel_context *intel, Link Here

(-)a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c (-11 / +2 lines)
146	mt->cpp,	146	mt->cpp,
147	mt->pitch,	147	mt->pitch,
148	mt->total_height,	148	mt->total_height,
149	mt->pitch,
150	expect_accelerated_upload);	149	expect_accelerated_upload);
		150	mt->pitch = mt->region->pitch;
151		151
152	if (!mt->region) {	152	if (!mt->region) {
153	free(mt);	153	free(mt);
Lines 177-196 intel_miptree_create_for_region(struct intel_context *intel, Link Here
177	I915_TILING_NONE);	177	I915_TILING_NONE);
178	if (!mt)	178	if (!mt)
179	return mt;	179	return mt;
180	#if 0	180
181	if (mt->pitch != region->pitch) {
182	fprintf(stderr,
183	"region pitch (%d) doesn't match mipmap tree pitch (%d)\n",
184	region->pitch, mt->pitch);
185	free(mt);
186	return NULL;
187	}
188	#else
189	/* The mipmap tree pitch is aligned to 64 bytes to make sure render	181	/* The mipmap tree pitch is aligned to 64 bytes to make sure render
190	* to texture works, but we don't need that for texturing from a	182	* to texture works, but we don't need that for texturing from a
191	* pixmap. Just override it here. */	183	* pixmap. Just override it here. */
192	mt->pitch = region->pitch;	184	mt->pitch = region->pitch;
193	#endif
194		185
195	intel_region_reference(&mt->region, region);	186	intel_region_reference(&mt->region, region);
196		187

Lines 173-179 Link Here

(-)a/src/mesa/drivers/dri/intel/intel_regions.c (-8 / +4 lines)
173	struct intel_region *	173	struct intel_region *
174	intel_region_alloc(struct intel_context *intel,	174	intel_region_alloc(struct intel_context *intel,
175	uint32_t tiling,	175	uint32_t tiling,
176	GLuint cpp, GLuint width, GLuint height, GLuint pitch,	176	GLuint cpp, GLuint width, GLuint height,
177	GLboolean expect_accelerated_upload)	177	GLboolean expect_accelerated_upload)
178	{	178	{
179	dri_bo *buffer;	179	dri_bo *buffer;
Lines 187-203 Link Here
187	buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "region",	187	buffer = drm_intel_bo_alloc_tiled(intel->bufmgr, "region",
188	width, height, cpp,	188	width, height, cpp,
189	&tiling, &aligned_pitch, flags);	189	&tiling, &aligned_pitch, flags);
190	/* We've already chosen a pitch as part of miptree layout. It had
191	* better be the same.
192	*/
193	assert(aligned_pitch == pitch * cpp);
194		190
195	region = intel_region_alloc_internal(intel, cpp, width, height,	191	region = intel_region_alloc_internal(intel, cpp, width, height,
196	pitch, buffer);	192	aligned_pitch / cpp, buffer);
197		193
198	if (tiling != I915_TILING_NONE) {	194	if (tiling != I915_TILING_NONE) {
199	assert(((pitch * cpp) & 127) == 0);	195	assert((aligned_pitch & 127) == 0);
200	drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);	196	drm_intel_bo_set_tiling(buffer, &tiling, aligned_pitch);
201	drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);	197	drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
202	}	198	}