stijn@marvin ~ ➜ resolve-march-native ERROR: No entry -m(arch|cpu)=.. found in: -mabi=lp64 -march= -mbranch-protection= -mcmodel=small -mcpu= -mfix-cortex-a53-835769 -mfix-cortex-a53-843419 -mglibc -mharden-sls= -mlittle-endian -mno-big-endian -mno-bionic -mno-general-regs-only -mno-low-precision-div -mno-low-precision-recip-sqrt -mno-low-precision-sqrt -mno-musl -mno-strict-align -mno-track-speculation -mno-uclibc -mno-verbose-cost-dump -momit-leaf-frame-pointer -moutline-atomics -moverride= -mpc-relative-literal-loads -msign-return-address=none -mstack-protector-guard-offset= -mstack-protector-guard-reg= -mstack-protector-guard=global -msve-vector-bits=scalable -mtls-dialect=desc -mtls-size=24 -mtune= stijn@marvin ~ ❯ gcc -fverbose-asm -march=native -mcpu=native -Q --help=target The following options are target specific: -mabi= lp64 -march= armv8-a+crc+lse+rcpc+rdma+dotprod+aes+sha3+fp16fml+sb+ssbs+i8mm+bf16+flagm+pauth -mbig-endian [disabled] -mbionic [disabled] -mbranch-protection= -mcmodel= small -mcpu= -mfix-cortex-a53-835769 [enabled] -mfix-cortex-a53-843419 [enabled] -mgeneral-regs-only [disabled] -mglibc [enabled] -mharden-sls= -mlittle-endian [enabled] -mlow-precision-div [disabled] -mlow-precision-recip-sqrt [disabled] -mlow-precision-sqrt [disabled] -mmusl [disabled] -momit-leaf-frame-pointer [enabled] -moutline-atomics [enabled] -moverride=<string> -mpc-relative-literal-loads [enabled] -msign-return-address= none -mstack-protector-guard-offset= -mstack-protector-guard-reg= -mstack-protector-guard= global -mstrict-align [disabled] -msve-vector-bits=<number> scalable -mtls-dialect= desc -mtls-size= 24 -mtrack-speculation [disabled] -mtune= -muclibc [disabled] -mverbose-cost-dump [disabled] Known AArch64 ABIs (for use with the -mabi= option): ilp32 lp64 Supported AArch64 return address signing scope (for use with -msign-return-address= option): all non-leaf none The code model option names for -mcmodel: large small tiny Valid arguments to -mstack-protector-guard=: global sysreg The possible SVE vector lengths: 1024 128 2048 256 512 scalable The possible TLS dialects: desc trad stijn@marvin ~ ❯ lscpu Architecture: aarch64 CPU op-mode(s): 64-bit Byte Order: Little Endian CPU(s): 8 On-line CPU(s) list: 0-7 Vendor ID: Apple Model name: Blizzard-M2 Model: 0 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 Stepping: 0x1 Frequency boost: enabled CPU(s) scaling MHz: 100% CPU max MHz: 2424.0000 CPU min MHz: 600.0000 BogoMIPS: 48.00 Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 bti ecv Model name: Avalanche-M2 Model: 0 Thread(s) per core: 1 Core(s) per socket: 4 Socket(s): 1 Stepping: 0x1 CPU(s) scaling MHz: 100% CPU max MHz: 3504.0000 CPU min MHz: 660.0000 BogoMIPS: 48.00 Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 asimddp sha512 asimdfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint i8mm bf16 bti ecv Caches (sum of all): L1d: 768 KiB (8 instances) L1i: 1.3 MiB (8 instances) L2: 20 MiB (2 instances) Vulnerabilities: Gather data sampling: Not affected Itlb multihit: Not affected L1tf: Not affected Mds: Not affected Meltdown: Not affected Mmio stale data: Not affected Retbleed: Not affected Spec rstack overflow: Not affected Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl Spectre v1: Mitigation; __user pointer sanitization Spectre v2: Not affected Srbds: Not affected Tsx async abort: Not affected
Hello! It does say "-march=" in the first output so this _may_ be something not possible to fix, but I can try. Please create an issue at https://github.com/hartwork/resolve-march-native/issues providing the _four text files_ easily created via the commands listed at https://github.com/hartwork/resolve-march-native/issues/127#issuecomment-1871609163 . These four files will be the best chance at fixing this if possible. Thanks! Best, Sebastian
