I suppose this is somehow related to gcc but I don't really know where it's coming from... with just -march=native or -march=athlon64-sse3 the following happens with a multitude of packages my current temporary solution was to add -mno-ssse3 -mno-sse4.1 -mno-sse4.2 -mno-sse4 -mno-avx to CFLAGS and CXXFLAGS but adding -mno-newinstructionset each time one pops up is not a real solution detected by qt build system... but glibc, mplayer and other stuff do the same MMX/3DNOW/SSE/SSE2/SSE3. yes/yes/yes/yes/yes SSSE3/SSE4.1/SSE4.2..... yes/yes/yes AVX..................... yes my /proc/cpuinfo processor : 0 vendor_id : AuthenticAMD cpu family : 15 model : 107 model name : AMD Athlon(tm) X2 Dual Core Processor BE-2300 stepping : 2 cpu MHz : 1900.000 cache size : 512 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 2 apicid : 0 initial apicid : 0 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm 3dnowext 3dnow rep_good nopl extd_apicid pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch lbrv bogomips : 3817.49 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp tm stc 100mhzsteps processor : 1 vendor_id : AuthenticAMD cpu family : 15 model : 107 model name : AMD Athlon(tm) X2 Dual Core Processor BE-2300 stepping : 2 cpu MHz : 1900.000 cache size : 512 KB physical id : 0 siblings : 2 core id : 1 cpu cores : 2 apicid : 1 initial apicid : 1 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm 3dnowext 3dnow rep_good nopl extd_apicid pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy 3dnowprefetch lbrv bogomips : 3817.49 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp tm stc 100mhzsteps
This is not really a bug. What this tell the software is that they _can_ compile those instructions. Whether they can use it or not it's a different point altogether. In general, software is designed to check at runtime which instruction sets are available — so for instance your glibc has an AVX version of strcasecmp, but will use it only if your CPU is capable of that.
