The following package fails to compile when used with SSE2 or SSE3 flag & when processor doesn't support above instructions set. As is visible in compile output the crypto++ uses palignr instruction defined in SSE3. From other hand crypto++ supports only sse2 use flag witch applied to this package causes compilation failure. In other words sse2 flag turn on sse3 instruction in crypto++. === The compilation output with error === x86_64-pc-linux-gnu-g++ -O1 -pipe -ftree-vectorize -c pkcspad.cpp {standard input}: Assembler messages: {standard input}:231: Error: no such instruction: `palignr xmm5,xmm2,4' {standard input}:231: Error: no such instruction: `palignr xmm6,xmm3,4' {standard input}:237: Error: no such instruction: `palignr xmm7,xmm3,4' {standard input}:237: Error: no such instruction: `palignr xmm6,xmm2,4' {standard input}:237: Error: no such instruction: `palignr xmm5,xmm1,4' {standard input}:237: Error: no such instruction: `palignr xmm4,xmm0,4' === The /proc/cpuinfo === processor : 0 vendor_id : AuthenticAMD cpu family : 15 model : 72 model name : AMD Turion(tm) 64 X2 Mobile Technology TL-50 stepping : 2 cpu MHz : 1600.000 cache size : 256 KB physical id : 0 siblings : 2 core id : 0 cpu cores : 2 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy bogomips : 3194.25 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp tm stc processor : 1 vendor_id : AuthenticAMD cpu family : 15 model : 72 model name : AMD Turion(tm) 64 X2 Mobile Technology TL-50 stepping : 2 cpu MHz : 1600.000 cache size : 256 KB physical id : 0 siblings : 2 core id : 1 cpu cores : 2 fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt rdtscp lm 3dnowext 3dnow rep_good pni cx16 lahf_lm cmp_legacy svm extapic cr8_legacy bogomips : 3191.89 TLB size : 1024 4K pages clflush size : 64 cache_alignment : 64 address sizes : 40 bits physical, 48 bits virtual power management: ts fid vid ttp tm stc
change sse2 use flag to sse3. Hopeing all sse3 chips have sse2 instructions sets. Thanks for the bug report.
