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Bug 187067 - sci-electronics/gplcver-2.12a version bump
Summary: sci-electronics/gplcver-2.12a version bump
Status: RESOLVED FIXED
Alias: None
Product: Gentoo Linux
Classification: Unclassified
Component: New packages (show other bugs)
Hardware: All Linux
: High enhancement (vote)
Assignee: The Soldering-Iron Brotherhood
URL: http://www.pragmatic-c.com/gpl-cver/
Whiteboard:
Keywords: EBUILD
Depends on:
Blocks:
 
Reported: 2007-07-29 22:15 UTC by Luis Vitorio Cargnini
Modified: 2007-09-16 15:40 UTC (History)
0 users

See Also:
Package list:
Runtime testing required: ---


Attachments
GPL-Cver 2.12a ebuild (gplcver-2.12a.ebuild,1.47 KB, text/plain)
2007-07-29 22:16 UTC, Luis Vitorio Cargnini
Details

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Description Luis Vitorio Cargnini 2007-07-29 22:15:45 UTC
GPL Cver is a Verilog HDL simulator that is released under the GNU General Public License. GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Cver is a full featured IEEE P1364 Verilog simulator. Features are:

    * Full 1995 IEEE P1364 implementation with some Verilog 2001 features.

    * Cver Interpreter loads the largest designs in only a few seconds
      During design develop and initial debugging; the edit, load and debug cycle is most important. The Cver interpreter eliminates the long wait for compiled simulators to compile every library module and then to load and link each module into the final design model. Cver reduces the waiting time to effectively zero.

    * Verilog XL (tm) style Verilog statement debugger with Enhancements.
      In addition to a Verilog statement debugger, Cver has added gdb style programming language debugger. Convenience features such as :info, :set: and :help comamnds. Also more convenient statement break point setting commands. Statement break points can be set by line number or function/task and filtered by instance (or all instances), skipped until a given ignore count is reached, or skipped until conditional expression becomes true.

    * Full Strength Model and Accurate Delay Modeling Support.
      Supports all P1364 delay modes with both SDF and PLI annotation: distributed, path, MIPD, and +show_canceled.

    * Implements Fast Relaxation Algorithm for Switch Level Simulation.

    * Non flattening Algorithm that Uses at Least 2/3 Less Memory.

    * Supports +loadvpi and +loadpli1 Dynamic Libary User PLI Program Loading. 

GPL Cver is the last Cver release made to our former licensee Antrim Design Systems before Antrim Design assets were purchased by Cadence Design systems. Cver has been used in commercial design flows and therefore mimics Cadence Verilog-XLā„¢. 

Reproducible: Always
Comment 1 Luis Vitorio Cargnini 2007-07-29 22:16:53 UTC
Created attachment 126394 [details]
GPL-Cver 2.12a ebuild

Ebuild file for upgrade
Comment 2 Denis Dupeyron (RETIRED) gentoo-dev 2007-09-16 15:40:59 UTC
Done. Thanks for reporting this.

Denis.