Gentoo Websites Logo
Go to: Gentoo Home Documentation Forums Lists Bugs Planet Store Wiki Get Gentoo!

Bug 51204

Summary: RadeonFB kernel modules "flik" on new iBook G4 1Ghz
Product: Gentoo Linux Reporter: Detro <demarino>
Component: [OLD] Core systemAssignee: PPC Porters <ppc>
Status: VERIFIED FIXED    
Severity: major CC: jcarlos
Priority: High    
Version: unspecified   
Hardware: PPC   
OS: Linux   
Whiteboard:
Package list:
Runtime testing required: ---

Description Detro 2004-05-16 06:51:54 UTC
As in the Summary, the "radeonfb" kernel module "flik" on the new iBook G4 1Ghz.
Other users (but with previous iBook version) don't releave this problem.

After Xfree shutdown, strange, the flik disappear.
Comment 1 Detro 2004-05-27 11:31:08 UTC
The problem is caused by a "mismatch" in the sync of kernel on radeonfb.
Problem is solved by a patch by Benh. Search on Google debian newsgroups
Comment 2 Detro 2004-05-27 11:34:37 UTC
This is the patch!!!

<code>
diff -uprN -X dontdiff linux-2.6.4-clean/drivers/video/aty/radeon_base.c linux-2.6.4/drivers/video/aty/radeon_base.c
--- linux-2.6.4-clean/drivers/video/aty/radeon_base.c	2004-03-10 18:55:25.000000000 -0800
+++ linux-2.6.4/drivers/video/aty/radeon_base.c	2004-04-01 16:10:32.050172056 -0800
@@ -1144,6 +1144,7 @@ static void radeon_write_pll_regs(struct
 
 	/* Set PPLL ref. div */
 	if (rinfo->family == CHIP_FAMILY_R300 ||
+	    rinfo->family == CHIP_FAMILY_RS300 ||
 	    rinfo->family == CHIP_FAMILY_R350 ||
 	    rinfo->family == CHIP_FAMILY_RV350) {
 		if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
@@ -2129,7 +2130,31 @@ static int radeonfb_pci_register (struct
 #endif /* CONFIG_PPC_OF */
 
 	/* framebuffer size */
-	tmp = INREG(CONFIG_MEMSIZE);
+	if ((rinfo->family == CHIP_FAMILY_RS100) ||
+	    (rinfo->family == CHIP_FAMILY_RS200) ||
+	    (rinfo->family == CHIP_FAMILY_RS300)) {
+	  u32 tom = INREG(NB_TOM);
+	  tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
+
+	  OUTREG(MC_FB_LOCATION, tom);
+	  OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
+	  OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
+	  OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
+
+	  /* This is supposed to fix the crtc2 noise problem. */
+	  OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
+ 
+	  if ((rinfo->family == CHIP_FAMILY_RS100) ||
+	      (rinfo->family == CHIP_FAMILY_RS200)) {
+            /* This is to workaround the asic bug for RMX, some versions
+               of BIOS dosen't have this register initialized correctly.
+            */
+            OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
+                    ~CRTC_H_CUTOFF_ACTIVE_EN);
+	  }
+	} else {
+	  tmp = INREG(CONFIG_MEMSIZE);
+	}
 
 	/* mem size is bits [28:0], mask off the rest */
 	rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
diff -uprN -X dontdiff linux-2.6.4-clean/include/video/radeon.h linux-2.6.4/include/video/radeon.h
--- linux-2.6.4-clean/include/video/radeon.h	2004-03-10 18:55:54.000000000 -0800
+++ linux-2.6.4/include/video/radeon.h	2004-03-29 18:34:57.000000000 -0800
@@ -73,6 +73,7 @@
 #define MEM_IO_CNTL_A0                         0x0178  
 #define MEM_INIT_LATENCY_TIMER                 0x0154  
 #define MEM_SDRAM_MODE_REG                     0x0158  
+#define NB_TOM                                 0x015C  
 #define AGP_BASE                               0x0170  
 #define MEM_IO_CNTL_A1                         0x017C  
 #define MEM_IO_CNTL_B0                         0x0180
@@ -173,6 +174,8 @@
 #define CUR_CLR1                               0x0270  
 #define FP_HORZ_VERT_ACTIVE                    0x0278  
 #define CRTC_MORE_CNTL                         0x027C  
+#       define CRTC_H_CUTOFF_ACTIVE_EN         (1<<4)
+#       define CRTC_V_CUTOFF_ACTIVE_EN         (1<<5)
 #define DAC_EXT_CNTL                           0x0280  
 #define FP_GEN_CNTL                            0x0284  
 #define FP_HORZ_STRETCH                        0x028C  
@@ -185,6 +188,7 @@
 //#define DDA_ON_OFF			       0x02e4
 #define DVI_I2C_CNTL_1			       0x02e4
 #define GRPH_BUFFER_CNTL                       0x02F0
+#define GRPH2_BUFFER_CNTL                      0x03F0
 #define VGA_BUFFER_CNTL                        0x02F4
 #define OV0_Y_X_START                          0x0400
 #define OV0_Y_X_END                            0x0404  
</code>