|
Lines 150-160
static const int multicast_filter_limit
Link Here
|
| 150 |
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
150 |
#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) |
| 151 |
|
151 |
|
| 152 |
enum mac_version { |
152 |
enum mac_version { |
| 153 |
RTL_GIGA_MAC_VER_B = 0x00, |
153 |
RTL_GIGA_MAC_VER_01 = 0x00, |
| 154 |
/* RTL_GIGA_MAC_VER_C = 0x03, */ |
154 |
RTL_GIGA_MAC_VER_02 = 0x01, |
| 155 |
RTL_GIGA_MAC_VER_D = 0x01, |
155 |
RTL_GIGA_MAC_VER_03 = 0x02, |
| 156 |
RTL_GIGA_MAC_VER_E = 0x02, |
156 |
RTL_GIGA_MAC_VER_04 = 0x03, |
| 157 |
RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */ |
157 |
RTL_GIGA_MAC_VER_05 = 0x04, |
|
|
158 |
RTL_GIGA_MAC_VER_11 = 0x0b, |
| 159 |
RTL_GIGA_MAC_VER_12 = 0x0c, |
| 160 |
RTL_GIGA_MAC_VER_13 = 0x0d, |
| 161 |
RTL_GIGA_MAC_VER_14 = 0x0e, |
| 162 |
RTL_GIGA_MAC_VER_15 = 0x0f |
| 158 |
}; |
163 |
}; |
| 159 |
|
164 |
|
| 160 |
enum phy_version { |
165 |
enum phy_version { |
|
Lines 166-172
enum phy_version {
Link Here
|
| 166 |
RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ |
171 |
RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */ |
| 167 |
}; |
172 |
}; |
| 168 |
|
173 |
|
| 169 |
|
|
|
| 170 |
#define _R(NAME,MAC,MASK) \ |
174 |
#define _R(NAME,MAC,MASK) \ |
| 171 |
{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
175 |
{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } |
| 172 |
|
176 |
|
|
Lines 175-193
static const struct {
Link Here
|
| 175 |
u8 mac_version; |
179 |
u8 mac_version; |
| 176 |
u32 RxConfigMask; /* Clears the bits supported by this chip */ |
180 |
u32 RxConfigMask; /* Clears the bits supported by this chip */ |
| 177 |
} rtl_chip_info[] = { |
181 |
} rtl_chip_info[] = { |
| 178 |
_R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880), |
182 |
_R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), |
| 179 |
_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880), |
183 |
_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_02, 0xff7e1880), |
| 180 |
_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880), |
184 |
_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), |
| 181 |
_R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880), |
185 |
_R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), |
|
|
186 |
_R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), |
| 187 |
_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
| 188 |
_R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E |
| 189 |
_R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 |
| 190 |
_R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 |
| 191 |
_R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139 |
| 182 |
}; |
192 |
}; |
| 183 |
#undef _R |
193 |
#undef _R |
| 184 |
|
194 |
|
|
|
195 |
enum cfg_version { |
| 196 |
RTL_CFG_0 = 0x00, |
| 197 |
RTL_CFG_1, |
| 198 |
RTL_CFG_2 |
| 199 |
}; |
| 200 |
|
| 201 |
static const struct { |
| 202 |
unsigned int region; |
| 203 |
unsigned int align; |
| 204 |
} rtl_cfg_info[] = { |
| 205 |
[RTL_CFG_0] = { 1, NET_IP_ALIGN }, |
| 206 |
[RTL_CFG_1] = { 2, NET_IP_ALIGN }, |
| 207 |
[RTL_CFG_2] = { 2, 8 } |
| 208 |
}; |
| 209 |
|
| 185 |
static struct pci_device_id rtl8169_pci_tbl[] = { |
210 |
static struct pci_device_id rtl8169_pci_tbl[] = { |
| 186 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), }, |
211 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
| 187 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), }, |
212 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_1 }, |
| 188 |
{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), }, |
213 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_1 }, |
| 189 |
{ PCI_DEVICE(0x16ec, 0x0116), }, |
214 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_2 }, |
| 190 |
{ PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, }, |
215 |
{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
|
|
216 |
{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, |
| 217 |
{ PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
| 218 |
{ PCI_VENDOR_ID_LINKSYS, 0x1032, |
| 219 |
PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, |
| 191 |
{0,}, |
220 |
{0,}, |
| 192 |
}; |
221 |
}; |
| 193 |
|
222 |
|
|
Lines 346-351
enum RTL8169_register_content {
Link Here
|
| 346 |
PHY_Cap_100_Full = 0x0100, |
375 |
PHY_Cap_100_Full = 0x0100, |
| 347 |
|
376 |
|
| 348 |
/* PHY_1000_CTRL_REG = 9 */ |
377 |
/* PHY_1000_CTRL_REG = 9 */ |
|
|
378 |
PHY_Cap_1000_Half = 0x0100, |
| 349 |
PHY_Cap_1000_Full = 0x0200, |
379 |
PHY_Cap_1000_Full = 0x0200, |
| 350 |
|
380 |
|
| 351 |
PHY_Cap_Null = 0x0, |
381 |
PHY_Cap_Null = 0x0, |
|
Lines 433-438
struct rtl8169_private {
Link Here
|
| 433 |
dma_addr_t RxPhyAddr; |
463 |
dma_addr_t RxPhyAddr; |
| 434 |
struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
464 |
struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ |
| 435 |
struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
465 |
struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
|
|
466 |
unsigned align; |
| 436 |
unsigned rx_buf_sz; |
467 |
unsigned rx_buf_sz; |
| 437 |
struct timer_list timer; |
468 |
struct timer_list timer; |
| 438 |
u16 cp_cmd; |
469 |
u16 cp_cmd; |
|
Lines 749-773
static int rtl8169_set_speed_xmii(struct
Link Here
|
| 749 |
auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full | |
780 |
auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full | |
| 750 |
PHY_Cap_100_Half | PHY_Cap_100_Full); |
781 |
PHY_Cap_100_Half | PHY_Cap_100_Full); |
| 751 |
giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG); |
782 |
giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG); |
| 752 |
giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null); |
783 |
giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half | PHY_Cap_Null); |
| 753 |
|
784 |
|
| 754 |
if (autoneg == AUTONEG_ENABLE) { |
785 |
if (autoneg == AUTONEG_ENABLE) { |
| 755 |
auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full | |
786 |
auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full | |
| 756 |
PHY_Cap_100_Half | PHY_Cap_100_Full); |
787 |
PHY_Cap_100_Half | PHY_Cap_100_Full); |
| 757 |
giga_ctrl |= PHY_Cap_1000_Full; |
788 |
giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half; |
| 758 |
} else { |
789 |
} else { |
| 759 |
if (speed == SPEED_10) |
790 |
if (speed == SPEED_10) |
| 760 |
auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full; |
791 |
auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full; |
| 761 |
else if (speed == SPEED_100) |
792 |
else if (speed == SPEED_100) |
| 762 |
auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full; |
793 |
auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full; |
| 763 |
else if (speed == SPEED_1000) |
794 |
else if (speed == SPEED_1000) |
| 764 |
giga_ctrl |= PHY_Cap_1000_Full; |
795 |
giga_ctrl |= PHY_Cap_1000_Full | PHY_Cap_1000_Half; |
| 765 |
|
796 |
|
| 766 |
if (duplex == DUPLEX_HALF) |
797 |
if (duplex == DUPLEX_HALF) |
| 767 |
auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full); |
798 |
auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full); |
| 768 |
|
799 |
|
| 769 |
if (duplex == DUPLEX_FULL) |
800 |
if (duplex == DUPLEX_FULL) |
| 770 |
auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half); |
801 |
auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half); |
|
|
802 |
|
| 803 |
/* This tweak comes straight from Realtek's driver. */ |
| 804 |
if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && |
| 805 |
(tp->mac_version == RTL_GIGA_MAC_VER_13)) { |
| 806 |
auto_nego = PHY_Cap_100_Half | 0x01; |
| 807 |
} |
| 808 |
} |
| 809 |
|
| 810 |
/* The 8100e/8101e do Fast Ethernet only. */ |
| 811 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
| 812 |
(tp->mac_version == RTL_GIGA_MAC_VER_14) || |
| 813 |
(tp->mac_version == RTL_GIGA_MAC_VER_15)) { |
| 814 |
if ((giga_ctrl & (PHY_Cap_1000_Full | PHY_Cap_1000_Half)) && |
| 815 |
netif_msg_link(tp)) { |
| 816 |
printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", |
| 817 |
dev->name); |
| 818 |
} |
| 819 |
giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_1000_Half); |
| 771 |
} |
820 |
} |
| 772 |
|
821 |
|
| 773 |
tp->phy_auto_nego_reg = auto_nego; |
822 |
tp->phy_auto_nego_reg = auto_nego; |
|
Lines 1140-1149
static void rtl8169_get_mac_version(stru
Link Here
|
| 1140 |
u32 mask; |
1189 |
u32 mask; |
| 1141 |
int mac_version; |
1190 |
int mac_version; |
| 1142 |
} mac_info[] = { |
1191 |
} mac_info[] = { |
| 1143 |
{ 0x1 << 28, RTL_GIGA_MAC_VER_X }, |
1192 |
{ 0x38800000, RTL_GIGA_MAC_VER_15 }, |
| 1144 |
{ 0x1 << 26, RTL_GIGA_MAC_VER_E }, |
1193 |
{ 0x38000000, RTL_GIGA_MAC_VER_12 }, |
| 1145 |
{ 0x1 << 23, RTL_GIGA_MAC_VER_D }, |
1194 |
{ 0x34000000, RTL_GIGA_MAC_VER_13 }, |
| 1146 |
{ 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */ |
1195 |
{ 0x30800000, RTL_GIGA_MAC_VER_14 }, |
|
|
1196 |
{ 0x30000000, RTL_GIGA_MAC_VER_11 }, |
| 1197 |
{ 0x18000000, RTL_GIGA_MAC_VER_05 }, |
| 1198 |
{ 0x10000000, RTL_GIGA_MAC_VER_04 }, |
| 1199 |
{ 0x04000000, RTL_GIGA_MAC_VER_03 }, |
| 1200 |
{ 0x00800000, RTL_GIGA_MAC_VER_02 }, |
| 1201 |
{ 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ |
| 1147 |
}, *p = mac_info; |
1202 |
}, *p = mac_info; |
| 1148 |
u32 reg; |
1203 |
u32 reg; |
| 1149 |
|
1204 |
|
|
Lines 1155-1178
static void rtl8169_get_mac_version(stru
Link Here
|
| 1155 |
|
1210 |
|
| 1156 |
static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
1211 |
static void rtl8169_print_mac_version(struct rtl8169_private *tp) |
| 1157 |
{ |
1212 |
{ |
| 1158 |
struct { |
1213 |
dprintk("mac_version = 0x%02x\n", tp->mac_version); |
| 1159 |
int version; |
|
|
| 1160 |
char *msg; |
| 1161 |
} mac_print[] = { |
| 1162 |
{ RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" }, |
| 1163 |
{ RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" }, |
| 1164 |
{ RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" }, |
| 1165 |
{ 0, NULL } |
| 1166 |
}, *p; |
| 1167 |
|
| 1168 |
for (p = mac_print; p->msg; p++) { |
| 1169 |
if (tp->mac_version == p->version) { |
| 1170 |
dprintk("mac_version == %s (%04d)\n", p->msg, |
| 1171 |
p->version); |
| 1172 |
return; |
| 1173 |
} |
| 1174 |
} |
| 1175 |
dprintk("mac_version == Unknown\n"); |
| 1176 |
} |
1214 |
} |
| 1177 |
|
1215 |
|
| 1178 |
static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr) |
1216 |
static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr) |
|
Lines 1257-1263
static void rtl8169_hw_phy_config(struct
Link Here
|
| 1257 |
rtl8169_print_mac_version(tp); |
1295 |
rtl8169_print_mac_version(tp); |
| 1258 |
rtl8169_print_phy_version(tp); |
1296 |
rtl8169_print_phy_version(tp); |
| 1259 |
|
1297 |
|
| 1260 |
if (tp->mac_version <= RTL_GIGA_MAC_VER_B) |
1298 |
if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
| 1261 |
return; |
1299 |
return; |
| 1262 |
if (tp->phy_version >= RTL_GIGA_PHY_VER_H) |
1300 |
if (tp->phy_version >= RTL_GIGA_PHY_VER_H) |
| 1263 |
return; |
1301 |
return; |
|
Lines 1267-1273
static void rtl8169_hw_phy_config(struct
Link Here
|
| 1267 |
|
1305 |
|
| 1268 |
/* Shazam ! */ |
1306 |
/* Shazam ! */ |
| 1269 |
|
1307 |
|
| 1270 |
if (tp->mac_version == RTL_GIGA_MAC_VER_X) { |
1308 |
if (tp->mac_version == RTL_GIGA_MAC_VER_04) { |
| 1271 |
mdio_write(ioaddr, 31, 0x0001); |
1309 |
mdio_write(ioaddr, 31, 0x0001); |
| 1272 |
mdio_write(ioaddr, 9, 0x273a); |
1310 |
mdio_write(ioaddr, 9, 0x273a); |
| 1273 |
mdio_write(ioaddr, 14, 0x7bfb); |
1311 |
mdio_write(ioaddr, 14, 0x7bfb); |
|
Lines 1306-1312
static void rtl8169_phy_timer(unsigned l
Link Here
|
| 1306 |
void __iomem *ioaddr = tp->mmio_addr; |
1344 |
void __iomem *ioaddr = tp->mmio_addr; |
| 1307 |
unsigned long timeout = RTL8169_PHY_TIMEOUT; |
1345 |
unsigned long timeout = RTL8169_PHY_TIMEOUT; |
| 1308 |
|
1346 |
|
| 1309 |
assert(tp->mac_version > RTL_GIGA_MAC_VER_B); |
1347 |
assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
| 1310 |
assert(tp->phy_version < RTL_GIGA_PHY_VER_H); |
1348 |
assert(tp->phy_version < RTL_GIGA_PHY_VER_H); |
| 1311 |
|
1349 |
|
| 1312 |
if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)) |
1350 |
if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)) |
|
Lines 1342-1348
static inline void rtl8169_delete_timer(
Link Here
|
| 1342 |
struct rtl8169_private *tp = netdev_priv(dev); |
1380 |
struct rtl8169_private *tp = netdev_priv(dev); |
| 1343 |
struct timer_list *timer = &tp->timer; |
1381 |
struct timer_list *timer = &tp->timer; |
| 1344 |
|
1382 |
|
| 1345 |
if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) || |
1383 |
if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) || |
| 1346 |
(tp->phy_version >= RTL_GIGA_PHY_VER_H)) |
1384 |
(tp->phy_version >= RTL_GIGA_PHY_VER_H)) |
| 1347 |
return; |
1385 |
return; |
| 1348 |
|
1386 |
|
|
Lines 1354-1360
static inline void rtl8169_request_timer
Link Here
|
| 1354 |
struct rtl8169_private *tp = netdev_priv(dev); |
1392 |
struct rtl8169_private *tp = netdev_priv(dev); |
| 1355 |
struct timer_list *timer = &tp->timer; |
1393 |
struct timer_list *timer = &tp->timer; |
| 1356 |
|
1394 |
|
| 1357 |
if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) || |
1395 |
if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) || |
| 1358 |
(tp->phy_version >= RTL_GIGA_PHY_VER_H)) |
1396 |
(tp->phy_version >= RTL_GIGA_PHY_VER_H)) |
| 1359 |
return; |
1397 |
return; |
| 1360 |
|
1398 |
|
|
Lines 1393-1400
static void rtl8169_release_board(struct
Link Here
|
| 1393 |
|
1431 |
|
| 1394 |
static int __devinit |
1432 |
static int __devinit |
| 1395 |
rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out, |
1433 |
rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out, |
| 1396 |
void __iomem **ioaddr_out) |
1434 |
void __iomem **ioaddr_out, const struct pci_device_id *ent) |
| 1397 |
{ |
1435 |
{ |
|
|
1436 |
const unsigned int region = rtl_cfg_info[ent->driver_data].region; |
| 1398 |
void __iomem *ioaddr; |
1437 |
void __iomem *ioaddr; |
| 1399 |
struct net_device *dev; |
1438 |
struct net_device *dev; |
| 1400 |
struct rtl8169_private *tp; |
1439 |
struct rtl8169_private *tp; |
|
Lines 1441-1447
rtl8169_init_board(struct pci_dev *pdev,
Link Here
|
| 1441 |
} |
1480 |
} |
| 1442 |
|
1481 |
|
| 1443 |
/* make sure PCI base addr 1 is MMIO */ |
1482 |
/* make sure PCI base addr 1 is MMIO */ |
| 1444 |
if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) { |
1483 |
if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
| 1445 |
if (netif_msg_probe(tp)) |
1484 |
if (netif_msg_probe(tp)) |
| 1446 |
dev_err(&pdev->dev, |
1485 |
dev_err(&pdev->dev, |
| 1447 |
"region #1 not an MMIO resource, aborting\n"); |
1486 |
"region #1 not an MMIO resource, aborting\n"); |
|
Lines 1449-1455
rtl8169_init_board(struct pci_dev *pdev,
Link Here
|
| 1449 |
goto err_out_mwi; |
1488 |
goto err_out_mwi; |
| 1450 |
} |
1489 |
} |
| 1451 |
/* check for weird/broken PCI region reporting */ |
1490 |
/* check for weird/broken PCI region reporting */ |
| 1452 |
if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) { |
1491 |
if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
| 1453 |
if (netif_msg_probe(tp)) |
1492 |
if (netif_msg_probe(tp)) |
| 1454 |
dev_err(&pdev->dev, |
1493 |
dev_err(&pdev->dev, |
| 1455 |
"Invalid PCI region size(s), aborting\n"); |
1494 |
"Invalid PCI region size(s), aborting\n"); |
|
Lines 1483-1489
rtl8169_init_board(struct pci_dev *pdev,
Link Here
|
| 1483 |
pci_set_master(pdev); |
1522 |
pci_set_master(pdev); |
| 1484 |
|
1523 |
|
| 1485 |
/* ioremap MMIO region */ |
1524 |
/* ioremap MMIO region */ |
| 1486 |
ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE); |
1525 |
ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
| 1487 |
if (ioaddr == NULL) { |
1526 |
if (ioaddr == NULL) { |
| 1488 |
if (netif_msg_probe(tp)) |
1527 |
if (netif_msg_probe(tp)) |
| 1489 |
dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
1528 |
dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
|
Lines 1574-1580
rtl8169_init_one(struct pci_dev *pdev, c
Link Here
|
| 1574 |
MODULENAME, RTL8169_VERSION); |
1613 |
MODULENAME, RTL8169_VERSION); |
| 1575 |
} |
1614 |
} |
| 1576 |
|
1615 |
|
| 1577 |
rc = rtl8169_init_board(pdev, &dev, &ioaddr); |
1616 |
rc = rtl8169_init_board(pdev, &dev, &ioaddr, ent); |
| 1578 |
if (rc) |
1617 |
if (rc) |
| 1579 |
return rc; |
1618 |
return rc; |
| 1580 |
|
1619 |
|
|
Lines 1632-1637
rtl8169_init_one(struct pci_dev *pdev, c
Link Here
|
| 1632 |
tp->intr_mask = 0xffff; |
1671 |
tp->intr_mask = 0xffff; |
| 1633 |
tp->pci_dev = pdev; |
1672 |
tp->pci_dev = pdev; |
| 1634 |
tp->mmio_addr = ioaddr; |
1673 |
tp->mmio_addr = ioaddr; |
|
|
1674 |
tp->align = rtl_cfg_info[ent->driver_data].align; |
| 1635 |
|
1675 |
|
| 1636 |
spin_lock_init(&tp->lock); |
1676 |
spin_lock_init(&tp->lock); |
| 1637 |
|
1677 |
|
|
Lines 1641-1651
rtl8169_init_one(struct pci_dev *pdev, c
Link Here
|
| 1641 |
return rc; |
1681 |
return rc; |
| 1642 |
} |
1682 |
} |
| 1643 |
|
1683 |
|
| 1644 |
if (netif_msg_probe(tp)) { |
|
|
| 1645 |
printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", |
| 1646 |
dev->name, rtl_chip_info[tp->chipset].name); |
| 1647 |
} |
| 1648 |
|
| 1649 |
pci_set_drvdata(pdev, dev); |
1684 |
pci_set_drvdata(pdev, dev); |
| 1650 |
|
1685 |
|
| 1651 |
if (netif_msg_probe(tp)) { |
1686 |
if (netif_msg_probe(tp)) { |
|
Lines 1653-1659
rtl8169_init_one(struct pci_dev *pdev, c
Link Here
|
| 1653 |
"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
1688 |
"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " |
| 1654 |
"IRQ %d\n", |
1689 |
"IRQ %d\n", |
| 1655 |
dev->name, |
1690 |
dev->name, |
| 1656 |
rtl_chip_info[ent->driver_data].name, |
1691 |
rtl_chip_info[tp->chipset].name, |
| 1657 |
dev->base_addr, |
1692 |
dev->base_addr, |
| 1658 |
dev->dev_addr[0], dev->dev_addr[1], |
1693 |
dev->dev_addr[0], dev->dev_addr[1], |
| 1659 |
dev->dev_addr[2], dev->dev_addr[3], |
1694 |
dev->dev_addr[2], dev->dev_addr[3], |
|
Lines 1665-1676
rtl8169_init_one(struct pci_dev *pdev, c
Link Here
|
| 1665 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1700 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
| 1666 |
RTL_W8(0x82, 0x01); |
1701 |
RTL_W8(0x82, 0x01); |
| 1667 |
|
1702 |
|
| 1668 |
if (tp->mac_version < RTL_GIGA_MAC_VER_E) { |
1703 |
if (tp->mac_version < RTL_GIGA_MAC_VER_03) { |
| 1669 |
dprintk("Set PCI Latency=0x40\n"); |
1704 |
dprintk("Set PCI Latency=0x40\n"); |
| 1670 |
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); |
1705 |
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40); |
| 1671 |
} |
1706 |
} |
| 1672 |
|
1707 |
|
| 1673 |
if (tp->mac_version == RTL_GIGA_MAC_VER_D) { |
1708 |
if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
| 1674 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1709 |
dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
| 1675 |
RTL_W8(0x82, 0x01); |
1710 |
RTL_W8(0x82, 0x01); |
| 1676 |
dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
1711 |
dprintk("Set PHY Reg 0x0bh = 0x00h\n"); |
|
Lines 1780-1785
rtl8169_hw_start(struct net_device *dev)
Link Here
|
| 1780 |
{ |
1815 |
{ |
| 1781 |
struct rtl8169_private *tp = netdev_priv(dev); |
1816 |
struct rtl8169_private *tp = netdev_priv(dev); |
| 1782 |
void __iomem *ioaddr = tp->mmio_addr; |
1817 |
void __iomem *ioaddr = tp->mmio_addr; |
|
|
1818 |
struct pci_dev *pdev = tp->pci_dev; |
| 1783 |
u32 i; |
1819 |
u32 i; |
| 1784 |
|
1820 |
|
| 1785 |
/* Soft reset the chip. */ |
1821 |
/* Soft reset the chip. */ |
|
Lines 1792-1799
rtl8169_hw_start(struct net_device *dev)
Link Here
|
| 1792 |
udelay(10); |
1828 |
udelay(10); |
| 1793 |
} |
1829 |
} |
| 1794 |
|
1830 |
|
|
|
1831 |
if (tp->mac_version == RTL_GIGA_MAC_VER_13) { |
| 1832 |
pci_write_config_word(pdev, 0x68, 0x00); |
| 1833 |
pci_write_config_word(pdev, 0x69, 0x08); |
| 1834 |
} |
| 1835 |
|
| 1836 |
/* Undocumented stuff. */ |
| 1837 |
if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
| 1838 |
u16 cmd; |
| 1839 |
|
| 1840 |
/* Realtek's r1000_n.c driver uses '&& 0x01' here. Well... */ |
| 1841 |
if ((RTL_R8(Config2) & 0x07) & 0x01) |
| 1842 |
RTL_W32(0x7c, 0x0007ffff); |
| 1843 |
|
| 1844 |
RTL_W32(0x7c, 0x0007ff00); |
| 1845 |
|
| 1846 |
pci_read_config_word(pdev, PCI_COMMAND, &cmd); |
| 1847 |
cmd = cmd & 0xef; |
| 1848 |
pci_write_config_word(pdev, PCI_COMMAND, cmd); |
| 1849 |
} |
| 1850 |
|
| 1851 |
|
| 1795 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
1852 |
RTL_W8(Cfg9346, Cfg9346_Unlock); |
| 1796 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
|
|
| 1797 |
RTL_W8(EarlyTxThres, EarlyTxThld); |
1853 |
RTL_W8(EarlyTxThres, EarlyTxThld); |
| 1798 |
|
1854 |
|
| 1799 |
/* Low hurts. Let's disable the filtering. */ |
1855 |
/* Low hurts. Let's disable the filtering. */ |
|
Lines 1808-1824
rtl8169_hw_start(struct net_device *dev)
Link Here
|
| 1808 |
RTL_W32(TxConfig, |
1864 |
RTL_W32(TxConfig, |
| 1809 |
(TX_DMA_BURST << TxDMAShift) | (InterFrameGap << |
1865 |
(TX_DMA_BURST << TxDMAShift) | (InterFrameGap << |
| 1810 |
TxInterFrameGapShift)); |
1866 |
TxInterFrameGapShift)); |
| 1811 |
tp->cp_cmd |= RTL_R16(CPlusCmd); |
|
|
| 1812 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
| 1813 |
|
1867 |
|
| 1814 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_D) || |
1868 |
tp->cp_cmd |= RTL_R16(CPlusCmd) | PCIMulRW; |
| 1815 |
(tp->mac_version == RTL_GIGA_MAC_VER_E)) { |
1869 |
|
|
|
1870 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
| 1871 |
(tp->mac_version == RTL_GIGA_MAC_VER_03)) { |
| 1816 |
dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. " |
1872 |
dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. " |
| 1817 |
"Bit-3 and bit-14 MUST be 1\n"); |
1873 |
"Bit-3 and bit-14 MUST be 1\n"); |
| 1818 |
tp->cp_cmd |= (1 << 14) | PCIMulRW; |
1874 |
tp->cp_cmd |= (1 << 14); |
| 1819 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
|
|
| 1820 |
} |
1875 |
} |
| 1821 |
|
1876 |
|
|
|
1877 |
RTL_W16(CPlusCmd, tp->cp_cmd); |
| 1878 |
|
| 1822 |
/* |
1879 |
/* |
| 1823 |
* Undocumented corner. Supposedly: |
1880 |
* Undocumented corner. Supposedly: |
| 1824 |
* (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
1881 |
* (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets |
|
Lines 1829-1834
rtl8169_hw_start(struct net_device *dev)
Link Here
|
| 1829 |
RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); |
1886 |
RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32)); |
| 1830 |
RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); |
1887 |
RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK)); |
| 1831 |
RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); |
1888 |
RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32)); |
|
|
1889 |
RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
| 1832 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
1890 |
RTL_W8(Cfg9346, Cfg9346_Lock); |
| 1833 |
udelay(10); |
1891 |
udelay(10); |
| 1834 |
|
1892 |
|
|
Lines 1910-1926
static inline void rtl8169_map_to_asic(s
Link Here
|
| 1910 |
} |
1968 |
} |
| 1911 |
|
1969 |
|
| 1912 |
static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff, |
1970 |
static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff, |
| 1913 |
struct RxDesc *desc, int rx_buf_sz) |
1971 |
struct RxDesc *desc, int rx_buf_sz, |
|
|
1972 |
unsigned int align) |
| 1914 |
{ |
1973 |
{ |
| 1915 |
struct sk_buff *skb; |
1974 |
struct sk_buff *skb; |
| 1916 |
dma_addr_t mapping; |
1975 |
dma_addr_t mapping; |
| 1917 |
int ret = 0; |
1976 |
int ret = 0; |
| 1918 |
|
1977 |
|
| 1919 |
skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN); |
1978 |
skb = dev_alloc_skb(rx_buf_sz + align); |
| 1920 |
if (!skb) |
1979 |
if (!skb) |
| 1921 |
goto err_out; |
1980 |
goto err_out; |
| 1922 |
|
1981 |
|
| 1923 |
skb_reserve(skb, NET_IP_ALIGN); |
1982 |
skb_reserve(skb, align); |
| 1924 |
*sk_buff = skb; |
1983 |
*sk_buff = skb; |
| 1925 |
|
1984 |
|
| 1926 |
mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
1985 |
mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
|
Lines 1959-1967
static u32 rtl8169_rx_fill(struct rtl816
Link Here
|
| 1959 |
|
2018 |
|
| 1960 |
if (tp->Rx_skbuff[i]) |
2019 |
if (tp->Rx_skbuff[i]) |
| 1961 |
continue; |
2020 |
continue; |
| 1962 |
|
2021 |
|
| 1963 |
ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i, |
2022 |
ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i, |
| 1964 |
tp->RxDescArray + i, tp->rx_buf_sz); |
2023 |
tp->RxDescArray + i, tp->rx_buf_sz, tp->align); |
| 1965 |
if (ret < 0) |
2024 |
if (ret < 0) |
| 1966 |
break; |
2025 |
break; |
| 1967 |
} |
2026 |
} |
|
Lines 2372-2387
static inline void rtl8169_rx_csum(struc
Link Here
|
| 2372 |
} |
2431 |
} |
| 2373 |
|
2432 |
|
| 2374 |
static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size, |
2433 |
static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size, |
| 2375 |
struct RxDesc *desc, int rx_buf_sz) |
2434 |
struct RxDesc *desc, int rx_buf_sz, |
|
|
2435 |
unsigned int align) |
| 2376 |
{ |
2436 |
{ |
| 2377 |
int ret = -1; |
2437 |
int ret = -1; |
| 2378 |
|
2438 |
|
| 2379 |
if (pkt_size < rx_copybreak) { |
2439 |
if (pkt_size < rx_copybreak) { |
| 2380 |
struct sk_buff *skb; |
2440 |
struct sk_buff *skb; |
| 2381 |
|
2441 |
|
| 2382 |
skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN); |
2442 |
skb = dev_alloc_skb(pkt_size + align); |
| 2383 |
if (skb) { |
2443 |
if (skb) { |
| 2384 |
skb_reserve(skb, NET_IP_ALIGN); |
2444 |
skb_reserve(skb, align); |
| 2385 |
eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0); |
2445 |
eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0); |
| 2386 |
*sk_buff = skb; |
2446 |
*sk_buff = skb; |
| 2387 |
rtl8169_mark_to_asic(desc, rx_buf_sz); |
2447 |
rtl8169_mark_to_asic(desc, rx_buf_sz); |
|
Lines 2447-2459
rtl8169_rx_interrupt(struct net_device *
Link Here
|
| 2447 |
} |
2507 |
} |
| 2448 |
|
2508 |
|
| 2449 |
rtl8169_rx_csum(skb, desc); |
2509 |
rtl8169_rx_csum(skb, desc); |
| 2450 |
|
2510 |
|
| 2451 |
pci_dma_sync_single_for_cpu(tp->pci_dev, |
2511 |
pci_dma_sync_single_for_cpu(tp->pci_dev, |
| 2452 |
le64_to_cpu(desc->addr), tp->rx_buf_sz, |
2512 |
le64_to_cpu(desc->addr), tp->rx_buf_sz, |
| 2453 |
PCI_DMA_FROMDEVICE); |
2513 |
PCI_DMA_FROMDEVICE); |
| 2454 |
|
2514 |
|
| 2455 |
if (rtl8169_try_rx_copy(&skb, pkt_size, desc, |
2515 |
if (rtl8169_try_rx_copy(&skb, pkt_size, desc, |
| 2456 |
tp->rx_buf_sz)) { |
2516 |
tp->rx_buf_sz, tp->align)) { |
| 2457 |
pci_action = pci_unmap_single; |
2517 |
pci_action = pci_unmap_single; |
| 2458 |
tp->Rx_skbuff[entry] = NULL; |
2518 |
tp->Rx_skbuff[entry] = NULL; |
| 2459 |
} |
2519 |
} |
|
Lines 2716-2721
rtl8169_set_rx_mode(struct net_device *d
Link Here
|
| 2716 |
tmp = rtl8169_rx_config | rx_mode | |
2776 |
tmp = rtl8169_rx_config | rx_mode | |
| 2717 |
(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
2777 |
(RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); |
| 2718 |
|
2778 |
|
|
|
2779 |
if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
| 2780 |
(tp->mac_version == RTL_GIGA_MAC_VER_12) || |
| 2781 |
(tp->mac_version == RTL_GIGA_MAC_VER_13) || |
| 2782 |
(tp->mac_version == RTL_GIGA_MAC_VER_14) || |
| 2783 |
(tp->mac_version == RTL_GIGA_MAC_VER_15)) { |
| 2784 |
mc_filter[0] = 0xffffffff; |
| 2785 |
mc_filter[1] = 0xffffffff; |
| 2786 |
} |
| 2787 |
|
| 2719 |
RTL_W32(RxConfig, tmp); |
2788 |
RTL_W32(RxConfig, tmp); |
| 2720 |
RTL_W32(MAR0 + 0, mc_filter[0]); |
2789 |
RTL_W32(MAR0 + 0, mc_filter[0]); |
| 2721 |
RTL_W32(MAR0 + 4, mc_filter[1]); |
2790 |
RTL_W32(MAR0 + 4, mc_filter[1]); |
