[patch] workaround

workaround_uart2clock.patch (text/plain), 876 bytes, created by Étienne Buira on 2024-03-29 16:54:34 UTC

--- drivers/clk/rockchip/clk-rk3328.c.orig	2024-03-29 16:48:29.671985503 +0000
+++ drivers/clk/rockchip/clk-rk3328.c	2024-03-29 16:48:35.145390867 +0000
@@ -782,7 +782,7 @@
 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 10, GFLAGS),
 	GATE(PCLK_UART0, "pclk_uart0", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 11, GFLAGS),
 	GATE(PCLK_UART1, "pclk_uart1", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 12, GFLAGS),
-	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 13, GFLAGS),
+	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(16), 13, GFLAGS),
 	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 14, GFLAGS),
 	GATE(PCLK_DCF, "pclk_dcf", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 15, GFLAGS),
 	GATE(PCLK_GRF, "pclk_grf", "pclk_bus", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(17), 0, GFLAGS),