1-LastTest.log

1-LastTest.log (text/plain), 190.48 KB, created by Agostino Sarubbo on 2024-02-18 14:14:11 UTC

Start testing: Feb 18 14:55 CET
----------------------------------------------------------
1/24 Testing: capstone_test_basic
1/24 Test: capstone_test_basic
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_basic"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_basic" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: X86 16bit (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		cx, [si + 0x32]
0x1003:	or		byte ptr [bx + di], al
0x1005:	fadd		dword ptr [bx + di + 0x34c6]
0x1009:	adc		al, byte ptr [bx + si]
0x100b:

****************
Platform: X86 32bit (ATT syntax)
Code: 0xba 0xcd 0xab 0x00 0x00 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	movl		$0xabcd, %edx
0x1005:	leal		8(%edx, %esi), %ecx
0x1009:	addl		%ebx, %eax
0x100b:	addl		$0x1234, %esi
0x1011:

****************
Platform: X86 32 (Intel syntax)
Code: 0xba 0xcd 0xab 0x00 0x00 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	mov		edx, 0xabcd
0x1005:	lea		ecx, [edx + esi + 8]
0x1009:	add		eax, ebx
0x100b:	add		esi, 0x1234
0x1011:

****************
Platform: X86 32 (MASM syntax)
Code: 0xba 0xcd 0xab 0x00 0x00 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	mov		edx, 0abcdh
0x1005:	lea		ecx, [edx + esi + 8]
0x1009:	add		eax, ebx
0x100b:	add		esi, 1234h
0x1011:

****************
Platform: X86 64 (Intel syntax)
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push		rbp
0x1001:	mov		rax, qword ptr [rip + 0x13b8]
0x1008:

****************
Platform: ARM
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 
Disasm:
0x1000:	bl		#0xfbc
0x1004:	str		lr, [sp, #-4]!
0x1008:	andeq		r0, r0, r0
0x100c:	str		r8, [r2, #-0x3e0]!
0x1010:	mcreq		p2, #0, r0, c3, c1, #7
0x1014:	mov		r0, #0
0x1018:	strb		r3, [r1, r2]
0x101c:	cmp		r3, #0
0x1020:

****************
Platform: THUMB-2
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 
Disasm:
0x1000:	mov.w		r1, #0
0x1004:	pop.w		{fp, pc}
0x1008:	tbb		[r1, r0]
0x100c:

****************
Platform: ARM: Cortex-A15 + NEON
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 
Disasm:
0x1000:	sdiv		r0, r0, r1
0x1004:	udiv		r1, r1, r2
0x1008:	vbit		q5, q15, q6
0x100c:	vcgt.f32		q10, q9, q12
0x1010:

****************
Platform: THUMB
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 
Disasm:
0x1000:	bx		lr
0x1002:	mov		fp, sp
0x1004:	sub		sp, #0xc
0x1006:	ldr		r1, [r1, #0xc]
0x1008:

****************
Platform: Thumb-MClass
Code: 0xef 0xf3 0x02 0x80 
Disasm:
0x1000:	mrs		r0, eapsr
0x1004:

****************
Platform: Arm-V8
Code: 0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
Disasm:
0x1000:	vcvtt.f64.f16		d3, s1
0x1004:	crc32b		r0, r1, r2
0x1008:	dmb		oshld
0x100c:

****************
Platform: MIPS-32 (Big-endian)
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 
Disasm:
0x1000:	jal		0x40025c
0x1004:	nop		
0x1008:	addiu		$v0, $zero, 0xc
0x100c:	lw		$v0, ($sp)
0x1010:	ori		$at, $at, 0x3456
0x1014:

****************
Platform: MIPS-64-EL (Little-endian)
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori		$at, $at, 0x3456
0x1004:	srl		$v0, $at, 0x1f
0x1008:

****************
Platform: MIPS-32R6 | Micro (Big-endian)
Code: 0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 
Disasm:
0x1000:	break		7, 0
0x1004:	wait		0x11
0x1008:	syscall		0x18c
0x100c:	rotrv		$t1, $a2, $a3
0x1010:

****************
Platform: MIPS-32R6 (Big-endian)
Code: 0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 
Disasm:
0x1000:	addiupc		$a0, 0x64
0x1004:	align		$a0, $v0, $v1, 2
0x1008:

****************
Platform: ARM-64
Code: 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 
Disasm:
0x1000:	mul		x1, x1, x2
0x1004:	lsr		w1, w1, #0
0x1008:	sub		w0, w0, w1, uxtw
0x100c:	ldr		w1, [sp, #8]
0x1010:

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 
Disasm:
0x1000:	lwz		r1, 0(0)
0x1004:	lwz		r1, 0(r31)
0x1008:	vpkpx		v2, v3, v4
0x100c:	stfs		f2, 0x80(r4)
0x1010:	crand		cr0eq, cr0un, cr1lt
0x1014:	cmpwi		cr2, r3, 0x80
0x1018:	addc		r2, r3, r4
0x101c:	mulhd.		r2, r3, r4
0x1020:	bdnzlrl+		
0x1024:	bgelrl-		cr2
0x1028:

****************
Platform: PPC-64, print register with number only
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 
Disasm:
0x1000:	lwz		1, 0(0)
0x1004:	lwz		1, 0(31)
0x1008:	vpkpx		2, 3, 4
0x100c:	stfs		2, 0x80(4)
0x1010:	crand		0, 0, 1
0x1014:	cmpwi		2, 3, 0x80
0x1018:	addc		2, 3, 4
0x101c:	mulhd.		2, 3, 4
0x1020:	bdnzlrl+		
0x1024:	bgelrl-		cr2
0x1028:

****************
Platform: PPC-64 + QPX
Code: 0x10 0x60 0x2a 0x10 0x10 0x64 0x28 0x88 0x7c 0x4a 0x5d 0x0f 
Disasm:
0x1000:	qvfabs		q3, q5
0x1004:	qvfand		q3, q4, q5
0x1008:	qvstfsxa		q2, r10, r11
0x100c:

****************
Platform: Sparc
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp		%g1, %g2
0x1004:	jmpl		%o1+8, %g2
0x1008:	restore		%g0, 1, %g2
0x100c:	restore		
0x1010:	mov		1, %o0
0x1014:	casx		[%i0], %l6, %o2
0x1018:	sethi		0xa, %l0
0x101c:	add		%g1, %g2, %g3
0x1020:	nop		
0x1024:	bne		0x1020
0x1028:	ba		0x1024
0x102c:	add		%o0, %o1, %l0
0x1030:	fbg		0x102c
0x1034:	st		%o2, [%g1]
0x1038:	ldsb		[%i0+%l6], %o2
0x103c:	brnz,a,pn		%o2, 0x1048
0x1040:

****************
Platform: SparcV9
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps		%f0, %f4
0x1004:	fstox		%f0, %f4
0x1008:	fqtoi		%f0, %f4
0x100c:	fnegq		%f0, %f4
0x1010:

****************
Platform: SystemZ
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	adb		%f0, 0
0x1006:	a		%r0, 0xfff(%r15, %r1)
0x100a:	afi		%r0, -0x80000000
0x1010:	br		%r7
0x1012:	xiy		0x7ffff(%r15), 0x2a
0x1018:	xy		%r0, 0x7ffff(%r1, %r15)
0x101e:	stmg		%r0, %r0, 0(%r15)
0x1024:	ear		%r7, %a8
0x1028:

****************
Platform: XCore
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 
Disasm:
0x1000:	get		r11, ed
0x1002:	ldw		et, sp[4]
0x1004:	setd		res[r3], r4
0x1006:	init		t[r2]:lr, r1
0x100a:	divu		r9, r1, r3
0x100e:	lda16		r9, r3[-r11]
0x1012:	ldw		dp, dp[0x81c5]
0x1016:	lmul		r11, r0, r2, r5, r8, r10
0x101a:	add		r1, r2, r3
0x101c:

****************
Platform: M68K
Code: 0xd4 0x40 0x87 0x5a 0x4e 0x71 0x02 0xb4 0xc0 0xde 0xc0 0xde 0x5c 0x00 0x1d 0x80 0x71 0x12 0x01 0x23 0xf2 0x3c 0x44 0x22 0x40 0x49 0x0e 0x56 0x54 0xc5 0xf2 0x3c 0x44 0x00 0x44 0x7a 0x00 0x00 0xf2 0x00 0x0a 0x28 
Disasm:
0x1000:	add.w		d0, d2
0x1002:	or.w		d3, (a2)+
0x1004:	nop		
0x1006:	andi.l		#$c0dec0de, (a4, d5.l * 4)
0x100e:	move.b		d0, ([a6, d7.w], $123)
0x1014:	fadd.s		#3.141500, fp0
0x101c:	scc.b		d5
0x101e:	fmove.s		#1000.000000, fp0
0x1026:	fsub		fp2, fp4
0x102a:

****************
Platform: TMS320C64x
Code: 0x01 0xac 0x88 0x40 0x81 0xac 0x88 0x43 0x00 0x00 0x00 0x00 0x02 0x90 0x32 0x96 0x02 0x80 0x46 0x9e 0x05 0x3c 0x83 0xe6 0x0b 0x0c 0x8b 0x24 
Disasm:
0x1000:	add		a11, a4, a3
0x1004:	add		b11, b4, b3
0x1008:	NOP		
0x100c:	ldbu		*++a4[1], b5
0x1010:	ldbu		*+b15[0x46], b5
0x1014:	lddw		*+a15[4], b11:b10
0x1018:	ldndw		*+a3(a4), a23:a22
0x101c:

****************
Platform: M680X_M6809
Code: 0x06 0x10 0x19 0x1a 0x55 0x1e 0x01 0x23 0xe9 0x31 0x06 0x34 0x55 0xa6 0x81 0xa7 0x89 0x7f 0xff 0xa6 0x9d 0x10 0x00 0xa7 0x91 0xa6 0x9f 0x10 0x00 0x11 0xac 0x99 0x10 0x00 0x39 
Disasm:
0x1000:	ror		$10
0x1002:	daa		
0x1003:	orcc		#85
0x1005:	exg		d, x
0x1007:	bls		$0ff2
0x1009:	leay		6, x
0x100b:	pshs		cc, b, x, u
0x100d:	lda		, x++
0x100f:	sta		32767, x
0x1013:	lda		[$2017, pcr]
0x1017:	sta		[, x++]
0x1019:	lda		[$1000]
0x101d:	cmps		[4096, x]
0x1022:	rts		
0x1023:

****************
Platform: EVM
Code: 0x60 0x61 
Disasm:
0x1000:	push1		61
0x1002:

****************
Platform: WASM
Code: 0x20 0x00 0x20 0x01 0x41 0x20 0x10 0xc9 0x01 0x45 0x0b 
Disasm:
0x1000:	get_local		0x0
0x1002:	get_local		0x1
0x1004:	i32.const		0x20
0x1006:	call		0xc9
0x1009:	i32.eqz		
0x100a:	end		
0x100b:

****************
Platform: MOS65XX
Code: 0x0d 0x34 0x12 0x00 0x81 0x65 0x6c 0x01 0x00 0x85 0xff 0x10 0x00 0x19 0x42 0x42 0x00 0x49 0x42 
Disasm:
0x1000:	ora		0x1234
0x1003:	brk		0x81
0x1005:	adc		0x6c
0x1007:	ora		(0x00, x)
0x1009:	sta		0xff
0x100b:	bpl		0x100d
0x100d:	ora		0x4242, y
0x1010:	brk		0x49
0x1012:

****************
Platform: eBPF
Code: 0x97 0x09 0x00 0x00 0x37 0x13 0x03 0x00 0xdc 0x02 0x00 0x00 0x20 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xdb 0x3a 0x00 0x01 0x00 0x00 0x00 0x00 0x84 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x6d 0x33 0x17 0x02 0x00 0x00 0x00 0x00 
Disasm:
0x1000:	mod64		r9, 0x31337
0x1008:	be32		r2
0x1010:	ldb		[0x0]
0x1018:	xadddw		[r10+0x100], r3
0x1020:	neg		r2
0x1028:	jsgt		r3, r3, +0x217
0x1030:

****************
Platform: RISCV32
Code: 0x37 0x34 0x00 0x00 0x97 0x82 0x00 0x00 0xef 0x00 0x80 0x00 0xef 0xf0 0x1f 0xff 0xe7 0x00 0x45 0x00 0xe7 0x00 0xc0 0xff 0x63 0x05 0x41 0x00 0xe3 0x9d 0x61 0xfe 0x63 0xca 0x93 0x00 0x63 0x53 0xb5 0x00 0x63 0x65 0xd6 0x00 0x63 0x76 0xf7 0x00 0x03 0x88 0x18 0x00 0x03 0x99 0x49 0x00 0x03 0xaa 0x6a 0x00 0x03 0xcb 0x2b 0x01 0x03 0xdc 0x8c 0x01 0x23 0x86 0xad 0x03 0x23 0x9a 0xce 0x03 0x23 0x8f 0xef 0x01 0x93 0x00 0xe0 0x00 0x13 0xa1 0x01 0x01 0x13 0xb2 0x02 0x7d 0x13 0xc3 0x03 0xdd 0x13 0xe4 0xc4 0x12 0x13 0xf5 0x85 0x0c 0x13 0x96 0xe6 0x01 0x13 0xd7 0x97 0x01 0x13 0xd8 0xf8 0x40 0x33 0x89 0x49 0x01 0xb3 0x0a 0x7b 0x41 0x33 0xac 0xac 0x01 0xb3 0x3d 0xde 0x01 0x33 0xd2 0x62 0x40 0xb3 0x43 0x94 0x00 0x33 0xe5 0xc5 0x00 0xb3 0x76 0xf7 0x00 0xb3 0x54 0x39 0x01 0xb3 0x50 0x31 0x00 0x33 0x9f 0x0f 0x00 
Disasm:
0x1000:	lui		s0, 3
0x1004:	auipc		t0, 8
0x1008:	jal		8
0x100c:	jal		-0x10
0x1010:	jalr		ra, a0, 4
0x1014:	jalr		ra, zero, -4
0x1018:	beq		sp, tp, 0xa
0x101c:	bne		gp, t1, -6
0x1020:	blt		t2, s1, 0x14
0x1024:	bge		a0, a1, 6
0x1028:	bltu		a2, a3, 0xa
0x102c:	bgeu		a4, a5, 0xc
0x1030:	lb		a6, 1(a7)
0x1034:	lh		s2, 4(s3)
0x1038:	lw		s4, 6(s5)
0x103c:	lbu		s6, 0x12(s7)
0x1040:	lhu		s8, 0x18(s9)
0x1044:	sb		s10, 0x2c(s11)
0x1048:	sh		t3, 0x34(t4)
0x104c:	sb		t5, 0x1e(t6)
0x1050:	addi		ra, zero, 0xe
0x1054:	slti		sp, gp, 0x10
0x1058:	sltiu		tp, t0, 0x7d0
0x105c:	xori		t1, t2, -0x230
0x1060:	ori		s0, s1, 0x12c
0x1064:	andi		a0, a1, 0xc8
0x1068:	slli		a2, a3, 0x1e
0x106c:	srli		a4, a5, 0x19
0x1070:	srai		a6, a7, 0xf
0x1074:	add		s2, s3, s4
0x1078:	sub		s5, s6, s7
0x107c:	slt		s8, s9, s10
0x1080:	sltu		s11, t3, t4
0x1084:	sra		tp, t0, t1
0x1088:	xor		t2, s0, s1
0x108c:	or		a0, a1, a2
0x1090:	and		a3, a4, a5
0x1094:	srl		s1, s2, s3
0x1098:	srl		ra, sp, gp
0x109c:	sll		t5, t6, zero
0x10a0:

****************
Platform: RISCV64
Code: 0x13 0x04 0xa8 0x7a 
Disasm:
0x1000:	addi		s0, a6, 0x7aa
0x1004:

<end of output>
Test time =   0.04 sec
----------------------------------------------------------
Test Passed.
"capstone_test_basic" end time: Feb 18 14:55 CET
"capstone_test_basic" time elapsed: 00:00:00
----------------------------------------------------------

2/24 Testing: capstone_test_detail
2/24 Test: capstone_test_detail
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_detail"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_detail" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: X86 16bit (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		cx, [si + 0x32] // insn-ID: 332, insn-mnem: lea
0x1003:	or		byte ptr [bx + di], al // insn-ID: 512, insn-mnem: or
	Implicit registers modified: flags 
0x1005:	fadd		dword ptr [bx + di + 0x34c6] // insn-ID: 15, insn-mnem: fadd
	Implicit registers modified: fpsw 
	This instruction belongs to groups: fpu 
0x1009:	adc		al, byte ptr [bx + si] // insn-ID: 6, insn-mnem: adc
	Implicit registers read: flags 
	Implicit registers modified: flags 
0x100b:

****************
Platform: X86 32bit (ATT syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	leal		8(%edx, %esi), %ecx // insn-ID: 332, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	addl		%ebx, %eax // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	addl		$0x1234, %esi // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x100c:

****************
Platform: X86 32 (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		ecx, [edx + esi + 8] // insn-ID: 332, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	add		eax, ebx // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	add		esi, 0x1234 // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x100c:

****************
Platform: X86 64 (Intel syntax)
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push		rbp // insn-ID: 609, insn-mnem: push
	Implicit registers read: rsp 
	Implicit registers modified: rsp 
	This instruction belongs to groups: mode64 
0x1001:	mov		rax, qword ptr [rip + 0x13b8] // insn-ID: 460, insn-mnem: mov
0x1008:

****************
Platform: ARM
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 
Disasm:
0x1000:	bl		#0xfbc // insn-ID: 16, insn-mnem: bl
	Implicit registers read: pc 
	Implicit registers modified: lr pc 
	This instruction belongs to groups: call branch_relative arm jump 
0x1004:	str		lr, [sp, #-4]! // insn-ID: 240, insn-mnem: str
	This instruction belongs to groups: arm 
0x1008:	andeq		r0, r0, r0 // insn-ID: 9, insn-mnem: and
	This instruction belongs to groups: arm 
0x100c:	str		r8, [r2, #-0x3e0]! // insn-ID: 240, insn-mnem: str
	This instruction belongs to groups: arm 
0x1010:	mcreq		p2, #0, r0, c3, c1, #7 // insn-ID: 100, insn-mnem: mcr
	This instruction belongs to groups: privilege arm 
0x1014:	mov		r0, #0 // insn-ID: 106, insn-mnem: mov
	This instruction belongs to groups: arm 
0x1018:	strb		r3, [r1, r2] // insn-ID: 241, insn-mnem: strb
	This instruction belongs to groups: arm 
0x101c:	cmp		r3, #0 // insn-ID: 29, insn-mnem: cmp
	Implicit registers modified: cpsr 
	This instruction belongs to groups: arm 
0x1020:

****************
Platform: THUMB-2
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 
Disasm:
0x1000:	mov.w		r1, #0 // insn-ID: 106, insn-mnem: mov
	This instruction belongs to groups: thumb2 
0x1004:	pop.w		{fp, pc} // insn-ID: 127, insn-mnem: pop
	Implicit registers read: sp 
	Implicit registers modified: sp 
	This instruction belongs to groups: thumb2 
0x1008:	tbb		[r1, r0] // insn-ID: 263, insn-mnem: tbb
	This instruction belongs to groups: thumb2 jump 
0x100c:

****************
Platform: ARM: Cortex-A15 + NEON
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 
Disasm:
0x1000:	sdiv		r0, r0, r1 // insn-ID: 156, insn-mnem: sdiv
	This instruction belongs to groups: arm 
0x1004:	udiv		r1, r1, r2 // insn-ID: 278, insn-mnem: udiv
	This instruction belongs to groups: arm 
0x1008:	vbit		q5, q15, q6 // insn-ID: 323, insn-mnem: vbit
	This instruction belongs to groups: neon 
0x100c:	vcgt.f32		q10, q9, q12 // insn-ID: 328, insn-mnem: vcgt
	This instruction belongs to groups: neon 
0x1010:

****************
Platform: THUMB
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 
Disasm:
0x1000:	bx		lr // insn-ID: 19, insn-mnem: bx
	Implicit registers modified: pc 
	This instruction belongs to groups: thumb jump 
0x1002:	mov		fp, sp // insn-ID: 106, insn-mnem: mov
	This instruction belongs to groups: thumb thumb1only 
0x1004:	sub		sp, #0xc // insn-ID: 251, insn-mnem: sub
	This instruction belongs to groups: thumb thumb1only 
0x1006:	ldr		r1, [r1, #0xc] // insn-ID: 83, insn-mnem: ldr
	This instruction belongs to groups: thumb thumb1only 
0x1008:

****************
Platform: Thumb-MClass
Code: 0xef 0xf3 0x02 0x80 
Disasm:
0x1000:	mrs		r0, eapsr // insn-ID: 114, insn-mnem: mrs
	This instruction belongs to groups: thumb mclass 
0x1004:

****************
Platform: Arm-V8
Code: 0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
Disasm:
0x1000:	vcvtt.f64.f16		d3, s1 // insn-ID: 344, insn-mnem: vcvtt
	This instruction belongs to groups: fparmv8 dpvfp 
0x1004:	crc32b		r0, r1, r2 // insn-ID: 31, insn-mnem: crc32b
	This instruction belongs to groups: arm v8 crc 
0x1008:	dmb		oshld // insn-ID: 43, insn-mnem: dmb
	This instruction belongs to groups: arm databarrier 
0x100c:

****************
Platform: MIPS-32 (Big-endian)
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 0x00 0x80 0x04 0x08 
Disasm:
0x1000:	jal		0x40025c // insn-ID: 337, insn-mnem: jal
	Implicit registers modified: ra 
	This instruction belongs to groups: stdenc 
0x1004:	nop		 // insn-ID: 622, insn-mnem: nop
	This instruction belongs to groups: stdenc notinmicromips 
0x1008:	addiu		$v0, $zero, 0xc // insn-ID: 26, insn-mnem: addiu
	This instruction belongs to groups: stdenc notinmicromips 
0x100c:	lw		$v0, ($sp) // insn-ID: 373, insn-mnem: lw
	This instruction belongs to groups: stdenc notinmicromips 
0x1010:	ori		$at, $at, 0x3456 // insn-ID: 473, insn-mnem: ori
	This instruction belongs to groups: stdenc 
0x1014:	jr.hb		$a0 // insn-ID: 345, insn-mnem: jr
	This instruction belongs to groups: stdenc mips32 notmips32r6 notmips64r6 jump 
0x1018:

****************
Platform: MIPS-64-EL (Little-endian)
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori		$at, $at, 0x3456 // insn-ID: 473, insn-mnem: ori
	This instruction belongs to groups: stdenc 
0x1004:	srl		$v0, $at, 0x1f // insn-ID: 557, insn-mnem: srl
	This instruction belongs to groups: stdenc notinmicromips 
0x1008:

****************
Platform: MIPS-32R6 | Micro (Big-endian)
Code: 0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 
Disasm:
0x1000:	break		7, 0 // insn-ID: 128, insn-mnem: break
	This instruction belongs to groups: micromips 
0x1004:	wait		0x11 // insn-ID: 616, insn-mnem: wait
	This instruction belongs to groups: micromips 
0x1008:	syscall		0x18c // insn-ID: 594, insn-mnem: syscall
	This instruction belongs to groups: micromips int 
0x100c:	rotrv		$t1, $a2, $a3 // insn-ID: 499, insn-mnem: rotrv
	This instruction belongs to groups: micromips 
0x1010:

****************
Platform: MIPS-32R6 (Big-endian)
Code: 0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 
Disasm:
0x1000:	addiupc		$a0, 0x64 // insn-ID: 3, insn-mnem: addiupc
	This instruction belongs to groups: stdenc mips32r6 
0x1004:	align		$a0, $v0, $v1, 2 // insn-ID: 27, insn-mnem: align
	This instruction belongs to groups: stdenc mips32r6 
0x1008:

****************
Platform: ARM-64
Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c 
Disasm:
0x1000:	mrs		x9, midr_el1 // insn-ID: 662, insn-mnem: mrs
	This instruction belongs to groups: privilege 
0x1004:	msr		spsel, #0 // insn-ID: 664, insn-mnem: msr
	Implicit registers modified: nzcv 
	This instruction belongs to groups: privilege 
0x1008:	msr		dbgdtrtx_el0, x12 // insn-ID: 664, insn-mnem: msr
	This instruction belongs to groups: privilege 
0x100c:	tbx		v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // insn-ID: 1120, insn-mnem: tbx
	This instruction belongs to groups: neon 
0x1010:	scvtf		v0.2s, v1.2s, #3 // insn-ID: 785, insn-mnem: scvtf
	This instruction belongs to groups: neon 
0x1014:	fmla		s0, s0, v0.s[3] // insn-ID: 366, insn-mnem: fmla
	This instruction belongs to groups: neon 
0x1018:	fmov		x2, v5.d[1] // insn-ID: 379, insn-mnem: fmov
	This instruction belongs to groups: fparmv8 
0x101c:	dsb		nsh // insn-ID: 284, insn-mnem: dsb
0x1020:	dmb		osh // insn-ID: 282, insn-mnem: dmb
0x1024:	isb		 // insn-ID: 430, insn-mnem: isb
0x1028:	mul		x1, x1, x2 // insn-ID: 666, insn-mnem: mul
0x102c:	lsr		w1, w1, #0 // insn-ID: 645, insn-mnem: lsr
0x1030:	sub		w0, w0, w1, uxtw // insn-ID: 1082, insn-mnem: sub
0x1034:	ldr		w1, [sp, #8] // insn-ID: 558, insn-mnem: ldr
0x1038:	cneg		x0, x1, ne // insn-ID: 149, insn-mnem: cneg
	Implicit registers read: nzcv 
0x103c:	add		x0, x1, x2, lsl #2 // insn-ID: 6, insn-mnem: add
0x1040:	ldr		q16, [x24, w8, uxtw #4] // insn-ID: 558, insn-mnem: ldr
0x1044:

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 
Disasm:
0x1000:	lwz		r1, 0(0) // insn-ID: 651, insn-mnem: lwz
0x1004:	lwz		r1, 0(r31) // insn-ID: 651, insn-mnem: lwz
0x1008:	vpkpx		v2, v3, v4 // insn-ID: 1350, insn-mnem: vpkpx
	This instruction belongs to groups: altivec 
0x100c:	stfs		f2, 0x80(r4) // insn-ID: 1046, insn-mnem: stfs
0x1010:	crand		cr0eq, cr0un, cr1lt // insn-ID: 223, insn-mnem: crand
0x1014:	cmpwi		cr2, r3, 0x80 // insn-ID: 206, insn-mnem: cmpi
0x1018:	addc		r2, r3, r4 // insn-ID: 2, insn-mnem: addc
	Implicit registers modified: ca 
0x101c:	mulhd.		r2, r3, r4 // insn-ID: 830, insn-mnem: mulhd
	Implicit registers modified: cr0 
0x1020:	bdnzlrl+		 // insn-ID: 51, insn-mnem: bdnzlrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: ctr 
	This instruction belongs to groups: jump 
0x1024:	bgelrl-		cr2 // insn-ID: 99, insn-mnem: bgelrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: lr ctr 
	This instruction belongs to groups: jump 
0x1028:	bne		0x103c // insn-ID: 128, insn-mnem: bne
	Implicit registers read: ctr rm 
	Implicit registers modified: ctr 
	This instruction belongs to groups: jump 
0x102c:

****************
Platform: PPC-64 + QPX
Code: 0x10 0x60 0x2a 0x10 0x10 0x64 0x28 0x88 0x7c 0x4a 0x5d 0x0f 
Disasm:
0x1000:	qvfabs		q3, q5 // insn-ID: 855, insn-mnem: qvfabs
	Implicit registers read: rm 
	This instruction belongs to groups: qpx 
0x1004:	qvfand		q3, q4, q5 // insn-ID: 858, insn-mnem: qvfand
	Implicit registers read: rm 
	This instruction belongs to groups: qpx 
0x1008:	qvstfsxa		q2, r10, r11 // insn-ID: 980, insn-mnem: qvstfsxa
	Implicit registers read: rm 
	This instruction belongs to groups: qpx 
0x100c:

****************
Platform: Sparc
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp		%g1, %g2 // insn-ID: 33, insn-mnem: cmp
	Implicit registers modified: icc 
0x1004:	jmpl		%o1+8, %g2 // insn-ID: 194, insn-mnem: jmpl
0x1008:	restore		%g0, 1, %g2 // insn-ID: 226, insn-mnem: restore
0x100c:	restore		 // insn-ID: 226, insn-mnem: restore
0x1010:	mov		1, %o0 // insn-ID: 221, insn-mnem: or
0x1014:	casx		[%i0], %l6, %o2 // insn-ID: 28, insn-mnem: casx
	This instruction belongs to groups: 64bit 
0x1018:	sethi		0xa, %l0 // insn-ID: 232, insn-mnem: sethi
0x101c:	add		%g1, %g2, %g3 // insn-ID: 6, insn-mnem: add
0x1020:	nop		 // insn-ID: 217, insn-mnem: nop
0x1024:	bne		0x1020 // insn-ID: 16, insn-mnem: b
	Implicit registers read: icc 
	This instruction belongs to groups: jump 
0x1028:	ba		0x1024 // insn-ID: 16, insn-mnem: b
	This instruction belongs to groups: jump 
0x102c:	add		%o0, %o1, %l0 // insn-ID: 6, insn-mnem: add
0x1030:	fbg		0x102c // insn-ID: 19, insn-mnem: fb
	Implicit registers read: fcc0 
	This instruction belongs to groups: jump 
0x1034:	st		%o2, [%g1] // insn-ID: 246, insn-mnem: st
0x1038:	ldsb		[%i0+%l6], %o2 // insn-ID: 198, insn-mnem: ldsb
0x103c:	brnz,a,pn		%o2, 0x1048 // insn-ID: 24, insn-mnem: brnz
	This instruction belongs to groups: 64bit jump 
0x1040:

****************
Platform: SparcV9
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps		%f0, %f4 // insn-ID: 70, insn-mnem: fcmps
0x1004:	fstox		%f0, %f4 // insn-ID: 181, insn-mnem: fstox
	This instruction belongs to groups: 64bit 
0x1008:	fqtoi		%f0, %f4 // insn-ID: 159, insn-mnem: fqtoi
	This instruction belongs to groups: hardquad 
0x100c:	fnegq		%f0, %f4 // insn-ID: 127, insn-mnem: fnegq
	This instruction belongs to groups: v9 
0x1010:

****************
Platform: SystemZ
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	adb		%f0, 0 // insn-ID: 2, insn-mnem: adb
	Implicit registers modified: cc 
0x1006:	a		%r0, 0xfff(%r15, %r1) // insn-ID: 1, insn-mnem: a
	Implicit registers modified: cc 
0x100a:	afi		%r0, -0x80000000 // insn-ID: 6, insn-mnem: afi
	Implicit registers modified: cc 
0x1010:	br		%r7 // insn-ID: 283, insn-mnem: br
	This instruction belongs to groups: jump 
0x1012:	xiy		0x7ffff(%r15), 0x2a // insn-ID: 678, insn-mnem: xiy
	Implicit registers modified: cc 
0x1018:	xy		%r0, 0x7ffff(%r1, %r15) // insn-ID: 681, insn-mnem: xy
	Implicit registers modified: cc 
0x101e:	stmg		%r0, %r0, 0(%r15) // insn-ID: 657, insn-mnem: stmg
0x1024:	ear		%r7, %a8 // insn-ID: 383, insn-mnem: ear
0x1028:

****************
Platform: XCore
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 
Disasm:
0x1000:	get		r11, ed // insn-ID: 43, insn-mnem: get
	Implicit registers modified: r11 
0x1002:	ldw		et, sp[4] // insn-ID: 66, insn-mnem: ldw
	Implicit registers read: sp 
0x1004:	setd		res[r3], r4 // insn-ID: 93, insn-mnem: setd
0x1006:	init		t[r2]:lr, r1 // insn-ID: 50, insn-mnem: init
0x100a:	divu		r9, r1, r3 // insn-ID: 26, insn-mnem: divu
0x100e:	lda16		r9, r3[-r11] // insn-ID: 62, insn-mnem: lda16
0x1012:	ldw		dp, dp[0x81c5] // insn-ID: 66, insn-mnem: ldw
0x1016:	lmul		r11, r0, r2, r5, r8, r10 // insn-ID: 68, insn-mnem: lmul
0x101a:	add		r1, r2, r3 // insn-ID: 1, insn-mnem: add
0x101c:

****************
Platform: M68K
Code: 0xd4 0x40 0x87 0x5a 0x4e 0x71 0x02 0xb4 0xc0 0xde 0xc0 0xde 0x5c 0x00 0x1d 0x80 0x71 0x12 0x01 0x23 0xf2 0x3c 0x44 0x22 0x40 0x49 0x0e 0x56 0x54 0xc5 0xf2 0x3c 0x44 0x00 0x44 0x7a 0x00 0x00 0xf2 0x00 0x0a 0x28 
Disasm:
0x1000:	add.w		d0, d2 // insn-ID: 2, insn-mnem: add
	Implicit registers read: d0 
	Implicit registers modified: d2 
0x1002:	or.w		d3, (a2)+ // insn-ID: 296, insn-mnem: or
	Implicit registers read: d3 
	Implicit registers modified: a2 
0x1004:	nop		 // insn-ID: 294, insn-mnem: nop
0x1006:	andi.l		#$c0dec0de, (a4, d5.l * 4) // insn-ID: 8, insn-mnem: andi
	Implicit registers read: d5 a4 
0x100e:	move.b		d0, ([a6, d7.w], $123) // insn-ID: 281, insn-mnem: move
	Implicit registers read: d0 d7 a6 
0x1014:	fadd.s		#3.141500, fp0 // insn-ID: 89, insn-mnem: fadd
	Implicit registers modified: fp0 
0x101c:	scc.b		d5 // insn-ID: 330, insn-mnem: scc
	Implicit registers modified: d5 
0x101e:	fmove.s		#1000.000000, fp0 // insn-ID: 176, insn-mnem: fmove
	Implicit registers modified: fp0 
0x1026:	fsub		fp2, fp4 // insn-ID: 232, insn-mnem: fsub
	Implicit registers read: fp2 
	Implicit registers modified: fp4 
0x102a:

****************
Platform: M680X_M6809
Code: 0x06 0x10 0x19 0x1a 0x55 0x1e 0x01 0x23 0xe9 0x31 0x06 0x34 0x55 0xa6 0x81 0xa7 0x89 0x7f 0xff 0xa6 0x9d 0x10 0x00 0xa7 0x91 0xa6 0x9f 0x10 0x00 0x11 0xac 0x99 0x10 0x00 0x39 
Disasm:
0x1000:	ror		$10 // insn-ID: 276, insn-mnem: ror
	Implicit registers read: cc 
	Implicit registers modified: cc 
0x1002:	daa		 // insn-ID: 117, insn-mnem: daa
	Implicit registers read: cc a 
	Implicit registers modified: cc a 
0x1003:	orcc		#85 // insn-ID: 243, insn-mnem: orcc
	Implicit registers read: cc 
	Implicit registers modified: cc 
0x1005:	exg		d, x // insn-ID: 153, insn-mnem: exg
	Implicit registers read: d x 
	Implicit registers modified: d x 
0x1007:	bls		$0ff2 // insn-ID: 58, insn-mnem: bls
	Implicit registers read: cc 
	This instruction belongs to groups: branch_relative jump 
0x1009:	leay		6, x // insn-ID: 209, insn-mnem: leay
	Implicit registers read: cc x 
	Implicit registers modified: cc y 
0x100b:	pshs		cc, b, x, u // insn-ID: 251, insn-mnem: pshs
	Implicit registers read: s cc b x u 
	Implicit registers modified: s 
0x100d:	lda		, x++ // insn-ID: 190, insn-mnem: lda
	Implicit registers read: cc x 
	Implicit registers modified: cc a x 
0x100f:	sta		32767, x // insn-ID: 298, insn-mnem: sta
	Implicit registers read: cc a x 
	Implicit registers modified: cc 
0x1013:	lda		[$2017, pcr] // insn-ID: 190, insn-mnem: lda
	Implicit registers read: cc pc 
	Implicit registers modified: cc a 
0x1017:	sta		[, x++] // insn-ID: 298, insn-mnem: sta
	Implicit registers read: cc a x 
	Implicit registers modified: cc x 
0x1019:	lda		[$1000] // insn-ID: 190, insn-mnem: lda
	Implicit registers read: cc 
	Implicit registers modified: cc a 
0x101d:	cmps		[4096, x] // insn-ID: 98, insn-mnem: cmps
	Implicit registers read: cc s x 
	Implicit registers modified: cc 
0x1022:	rts		 // insn-ID: 285, insn-mnem: rts
	Implicit registers read: s 
	Implicit registers modified: s pc 
	This instruction belongs to groups: return 
0x1023:

****************
Platform: MOS65XX
Code: 0x0a 0x00 0xfe 0x34 0x12 0xd0 0xff 0xea 0x19 0x56 0x34 0x46 0x80 
Disasm:
0x1000:	asl		a // insn-ID: 3, insn-mnem: asl
	Implicit registers read: A 
	Implicit registers modified: A P 
0x1001:	brk		0xfe // insn-ID: 14, insn-mnem: brk
	This instruction belongs to groups: int 
0x1003:

****************
Platform: eBPF
Code: 0x97 0x09 0x00 0x00 0x37 0x13 0x03 0x00 0xdc 0x02 0x00 0x00 0x20 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xdb 0x3a 0x00 0x01 0x00 0x00 0x00 0x00 0x84 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x6d 0x33 0x17 0x02 0x00 0x00 0x00 0x00 
Disasm:
0x1000:	mod64		r9, 0x31337 // insn-ID: 23, insn-mnem: mod64
	This instruction belongs to groups: alu 
0x1008:	be32		r2 // insn-ID: 31, insn-mnem: be32
	This instruction belongs to groups: alu 
0x1010:	ldb		[0x0] // insn-ID: 35, insn-mnem: ldb
	Implicit registers modified: r0 
	This instruction belongs to groups: load 
0x1018:	xadddw		[r10+0x100], r3 // insn-ID: 50, insn-mnem: xadddw
	This instruction belongs to groups: store 
0x1020:	neg		r2 // insn-ID: 9, insn-mnem: neg
	This instruction belongs to groups: alu 
0x1028:	jsgt		r3, r3, +0x217 // insn-ID: 57, insn-mnem: jsgt
	This instruction belongs to groups: jump 
0x1030:

<end of output>
Test time =   0.04 sec
----------------------------------------------------------
Test Passed.
"capstone_test_detail" end time: Feb 18 14:55 CET
"capstone_test_detail" time elapsed: 00:00:00
----------------------------------------------------------

3/24 Testing: capstone_test_skipdata
3/24 Test: capstone_test_skipdata
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_skipdata"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_skipdata" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: X86 32 (Intel syntax) - Skip data
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x00 0x91 0x92 
Disasm:
0x1000:	lea		ecx, [edx + esi + 8]
0x1004:	add		eax, ebx
0x1006:	add		esi, 0x1234
0x100c:	.byte		0x00
0x100d:	xchg		ecx, eax
0x100e:	xchg		edx, eax
0x100f:

****************
Platform: X86 32 (Intel syntax) - Skip data with custom mnemonic
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x00 0x91 0x92 
Disasm:
0x1000:	lea		ecx, [edx + esi + 8]
0x1004:	add		eax, ebx
0x1006:	add		esi, 0x1234
0x100c:	db		0x00
0x100d:	xchg		ecx, eax
0x100e:	xchg		edx, eax
0x100f:

****************
Platform: Arm - Skip data
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	andeq		r0, r0, sp, ror #1
0x1004:	svceq		#0x5a1a00
0x1008:	stmibeq		r2, {r0, r1, r2, r3, r4, r8, sb, sl, fp, ip, sp, lr, pc} ^
0x100c:	andeq		r0, r0, r0, lsl #1
0x1010:	bhs		#0xffafec34
0x1014:	.byte		0xff, 0xff, 0x7f, 0x57
0x1018:	.byte		0xe3, 0x01, 0xff, 0xff
0x101c:	rsceq		r5, fp, pc, ror r7
0x1020:	strhs		r0, [r0], #-0xf0
0x1024:	stmdavc		r0, {r1, r4, r5, r7, r8, sb, sl, fp, lr}
0x1028:

****************
Platform: Arm - Skip data with callback
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	andeq		r0, r0, sp, ror #1
0x1004:	svceq		#0x5a1a00
0x1008:	stmibeq		r2, {r0, r1, r2, r3, r4, r8, sb, sl, fp, ip, sp, lr, pc} ^
0x100c:	andeq		r0, r0, r0, lsl #1
0x1010:	bhs		#0xffafec34
0x1014:	db		0xff, 0xff
0x1016:	mvneq		r5, pc, ror r7
0x101a:	db		0xff, 0xff
0x101c:	rsceq		r5, fp, pc, ror r7
0x1020:	strhs		r0, [r0], #-0xf0
0x1024:	stmdavc		r0, {r1, r4, r5, r7, r8, sb, sl, fp, lr}
0x1028:

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_skipdata" end time: Feb 18 14:55 CET
"capstone_test_skipdata" time elapsed: 00:00:00
----------------------------------------------------------

4/24 Testing: capstone_test_iter
4/24 Test: capstone_test_iter
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_iter"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_iter" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: X86 16bit (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		cx, [si + 0x32] // insn-ID: 332, insn-mnem: lea
0x1003:	or		byte ptr [bx + di], al // insn-ID: 512, insn-mnem: or
	Implicit registers modified: flags 
0x1005:	fadd		dword ptr [bx + di + 0x34c6] // insn-ID: 15, insn-mnem: fadd
	Implicit registers modified: fpsw 
	This instruction belongs to groups: fpu 
0x1009:	adc		al, byte ptr [bx + si] // insn-ID: 6, insn-mnem: adc
	Implicit registers read: flags 
	Implicit registers modified: flags 

****************
Platform: X86 32bit (ATT syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	leal		8(%edx, %esi), %ecx // insn-ID: 332, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	addl		%ebx, %eax // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	addl		$0x1234, %esi // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 

****************
Platform: X86 32 (Intel syntax)
Code: 0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 
Disasm:
0x1000:	lea		ecx, [edx + esi + 8] // insn-ID: 332, insn-mnem: lea
	This instruction belongs to groups: not64bitmode 
0x1004:	add		eax, ebx // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 
0x1006:	add		esi, 0x1234 // insn-ID: 8, insn-mnem: add
	Implicit registers modified: eflags 

****************
Platform: X86 64 (Intel syntax)
Code: 0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 
Disasm:
0x1000:	push		rbp // insn-ID: 609, insn-mnem: push
	Implicit registers read: rsp 
	Implicit registers modified: rsp 
	This instruction belongs to groups: mode64 
0x1001:	mov		rax, qword ptr [rip + 0x13b8] // insn-ID: 460, insn-mnem: mov

****************
Platform: ARM
Code: 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 
Disasm:
0x1000:	bl		#0xfbc // insn-ID: 16, insn-mnem: bl
	Implicit registers read: pc 
	Implicit registers modified: lr pc 
	This instruction belongs to groups: call branch_relative arm jump 
0x1004:	str		lr, [sp, #-4]! // insn-ID: 240, insn-mnem: str
	This instruction belongs to groups: arm 
0x1008:	andeq		r0, r0, r0 // insn-ID: 9, insn-mnem: and
	This instruction belongs to groups: arm 
0x100c:	str		r8, [r2, #-0x3e0]! // insn-ID: 240, insn-mnem: str
	This instruction belongs to groups: arm 
0x1010:	mcreq		p2, #0, r0, c3, c1, #7 // insn-ID: 100, insn-mnem: mcr
	This instruction belongs to groups: privilege arm 
0x1014:	mov		r0, #0 // insn-ID: 106, insn-mnem: mov
	This instruction belongs to groups: arm 
0x1018:	strb		r3, [r1, r2] // insn-ID: 241, insn-mnem: strb
	This instruction belongs to groups: arm 
0x101c:	cmp		r3, #0 // insn-ID: 29, insn-mnem: cmp
	Implicit registers modified: cpsr 
	This instruction belongs to groups: arm 

****************
Platform: THUMB-2
Code: 0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 
Disasm:
0x1000:	mov.w		r1, #0 // insn-ID: 106, insn-mnem: mov
	This instruction belongs to groups: thumb2 
0x1004:	pop.w		{fp, pc} // insn-ID: 127, insn-mnem: pop
	Implicit registers read: sp 
	Implicit registers modified: sp 
	This instruction belongs to groups: thumb2 
0x1008:	tbb		[r1, r0] // insn-ID: 263, insn-mnem: tbb
	This instruction belongs to groups: thumb2 jump 

****************
Platform: ARM: Cortex-A15 + NEON
Code: 0x10 0xf1 0x10 0xe7 0x11 0xf2 0x31 0xe7 0xdc 0xa1 0x2e 0xf3 0xe8 0x4e 0x62 0xf3 
Disasm:
0x1000:	sdiv		r0, r0, r1 // insn-ID: 156, insn-mnem: sdiv
	This instruction belongs to groups: arm 
0x1004:	udiv		r1, r1, r2 // insn-ID: 278, insn-mnem: udiv
	This instruction belongs to groups: arm 
0x1008:	vbit		q5, q15, q6 // insn-ID: 323, insn-mnem: vbit
	This instruction belongs to groups: neon 
0x100c:	vcgt.f32		q10, q9, q12 // insn-ID: 328, insn-mnem: vcgt
	This instruction belongs to groups: neon 

****************
Platform: THUMB
Code: 0x70 0x47 0xeb 0x46 0x83 0xb0 0xc9 0x68 
Disasm:
0x1000:	bx		lr // insn-ID: 19, insn-mnem: bx
	Implicit registers modified: pc 
	This instruction belongs to groups: thumb jump 
0x1002:	mov		fp, sp // insn-ID: 106, insn-mnem: mov
	This instruction belongs to groups: thumb thumb1only 
0x1004:	sub		sp, #0xc // insn-ID: 251, insn-mnem: sub
	This instruction belongs to groups: thumb thumb1only 
0x1006:	ldr		r1, [r1, #0xc] // insn-ID: 83, insn-mnem: ldr
	This instruction belongs to groups: thumb thumb1only 

****************
Platform: MIPS-32 (Big-endian)
Code: 0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 0x00 0x80 0x04 0x08 
Disasm:
0x1000:	jal		0x40025c // insn-ID: 337, insn-mnem: jal
	Implicit registers modified: ra 
	This instruction belongs to groups: stdenc 
0x1004:	nop		 // insn-ID: 622, insn-mnem: nop
	This instruction belongs to groups: stdenc notinmicromips 
0x1008:	addiu		$v0, $zero, 0xc // insn-ID: 26, insn-mnem: addiu
	This instruction belongs to groups: stdenc notinmicromips 
0x100c:	lw		$v0, ($sp) // insn-ID: 373, insn-mnem: lw
	This instruction belongs to groups: stdenc notinmicromips 
0x1010:	ori		$at, $at, 0x3456 // insn-ID: 473, insn-mnem: ori
	This instruction belongs to groups: stdenc 
0x1014:	jr.hb		$a0 // insn-ID: 345, insn-mnem: jr
	This instruction belongs to groups: stdenc mips32 notmips32r6 notmips64r6 jump 

****************
Platform: MIPS-64-EL (Little-endian)
Code: 0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori		$at, $at, 0x3456 // insn-ID: 473, insn-mnem: ori
	This instruction belongs to groups: stdenc 
0x1004:	srl		$v0, $at, 0x1f // insn-ID: 557, insn-mnem: srl
	This instruction belongs to groups: stdenc notinmicromips 

****************
Platform: ARM-64
Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c 
Disasm:
0x1000:	mrs		x9, midr_el1 // insn-ID: 662, insn-mnem: mrs
	This instruction belongs to groups: privilege 
0x1004:	msr		spsel, #0 // insn-ID: 664, insn-mnem: msr
	Implicit registers modified: nzcv 
	This instruction belongs to groups: privilege 
0x1008:	msr		dbgdtrtx_el0, x12 // insn-ID: 664, insn-mnem: msr
	This instruction belongs to groups: privilege 
0x100c:	tbx		v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // insn-ID: 1120, insn-mnem: tbx
	This instruction belongs to groups: neon 
0x1010:	scvtf		v0.2s, v1.2s, #3 // insn-ID: 785, insn-mnem: scvtf
	This instruction belongs to groups: neon 
0x1014:	fmla		s0, s0, v0.s[3] // insn-ID: 366, insn-mnem: fmla
	This instruction belongs to groups: neon 
0x1018:	fmov		x2, v5.d[1] // insn-ID: 379, insn-mnem: fmov
	This instruction belongs to groups: fparmv8 
0x101c:	dsb		nsh // insn-ID: 284, insn-mnem: dsb
0x1020:	dmb		osh // insn-ID: 282, insn-mnem: dmb
0x1024:	isb		 // insn-ID: 430, insn-mnem: isb
0x1028:	mul		x1, x1, x2 // insn-ID: 666, insn-mnem: mul
0x102c:	lsr		w1, w1, #0 // insn-ID: 645, insn-mnem: lsr
0x1030:	sub		w0, w0, w1, uxtw // insn-ID: 1082, insn-mnem: sub
0x1034:	ldr		w1, [sp, #8] // insn-ID: 558, insn-mnem: ldr
0x1038:	cneg		x0, x1, ne // insn-ID: 149, insn-mnem: cneg
	Implicit registers read: nzcv 
0x103c:	add		x0, x1, x2, lsl #2 // insn-ID: 6, insn-mnem: add
0x1040:	ldr		q16, [x24, w8, uxtw #4] // insn-ID: 558, insn-mnem: ldr

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 
Disasm:
0x1000:	lwz		r1, 0(0) // insn-ID: 651, insn-mnem: lwz
0x1004:	lwz		r1, 0(r31) // insn-ID: 651, insn-mnem: lwz
0x1008:	vpkpx		v2, v3, v4 // insn-ID: 1350, insn-mnem: vpkpx
	This instruction belongs to groups: altivec 
0x100c:	stfs		f2, 0x80(r4) // insn-ID: 1046, insn-mnem: stfs
0x1010:	crand		cr0eq, cr0un, cr1lt // insn-ID: 223, insn-mnem: crand
0x1014:	cmpwi		cr2, r3, 0x80 // insn-ID: 206, insn-mnem: cmpi
0x1018:	addc		r2, r3, r4 // insn-ID: 2, insn-mnem: addc
	Implicit registers modified: ca 
0x101c:	mulhd.		r2, r3, r4 // insn-ID: 830, insn-mnem: mulhd
	Implicit registers modified: cr0 
0x1020:	bdnzlrl+		 // insn-ID: 51, insn-mnem: bdnzlrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: ctr 
	This instruction belongs to groups: jump 
0x1024:	bgelrl-		cr2 // insn-ID: 99, insn-mnem: bgelrl
	Implicit registers read: ctr lr rm 
	Implicit registers modified: lr ctr 
	This instruction belongs to groups: jump 
0x1028:	bne		0x103c // insn-ID: 128, insn-mnem: bne
	Implicit registers read: ctr rm 
	Implicit registers modified: ctr 
	This instruction belongs to groups: jump 

****************
Platform: Sparc
Code: 0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp		%g1, %g2 // insn-ID: 33, insn-mnem: cmp
	Implicit registers modified: icc 
0x1004:	jmpl		%o1+8, %g2 // insn-ID: 194, insn-mnem: jmpl
0x1008:	restore		%g0, 1, %g2 // insn-ID: 226, insn-mnem: restore
0x100c:	restore		 // insn-ID: 226, insn-mnem: restore
0x1010:	mov		1, %o0 // insn-ID: 221, insn-mnem: or
0x1014:	casx		[%i0], %l6, %o2 // insn-ID: 28, insn-mnem: casx
	This instruction belongs to groups: 64bit 
0x1018:	sethi		0xa, %l0 // insn-ID: 232, insn-mnem: sethi
0x101c:	add		%g1, %g2, %g3 // insn-ID: 6, insn-mnem: add
0x1020:	nop		 // insn-ID: 217, insn-mnem: nop
0x1024:	bne		0x1020 // insn-ID: 16, insn-mnem: b
	Implicit registers read: icc 
	This instruction belongs to groups: jump 
0x1028:	ba		0x1024 // insn-ID: 16, insn-mnem: b
	This instruction belongs to groups: jump 
0x102c:	add		%o0, %o1, %l0 // insn-ID: 6, insn-mnem: add
0x1030:	fbg		0x102c // insn-ID: 19, insn-mnem: fb
	Implicit registers read: fcc0 
	This instruction belongs to groups: jump 
0x1034:	st		%o2, [%g1] // insn-ID: 246, insn-mnem: st
0x1038:	ldsb		[%i0+%l6], %o2 // insn-ID: 198, insn-mnem: ldsb
0x103c:	brnz,a,pn		%o2, 0x1048 // insn-ID: 24, insn-mnem: brnz
	This instruction belongs to groups: 64bit jump 

****************
Platform: SparcV9
Code: 0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps		%f0, %f4 // insn-ID: 70, insn-mnem: fcmps
0x1004:	fstox		%f0, %f4 // insn-ID: 181, insn-mnem: fstox
	This instruction belongs to groups: 64bit 
0x1008:	fqtoi		%f0, %f4 // insn-ID: 159, insn-mnem: fqtoi
	This instruction belongs to groups: hardquad 
0x100c:	fnegq		%f0, %f4 // insn-ID: 127, insn-mnem: fnegq
	This instruction belongs to groups: v9 

****************
Platform: SystemZ
Code: 0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 
Disasm:
0x1000:	adb		%f0, 0 // insn-ID: 2, insn-mnem: adb
	Implicit registers modified: cc 
0x1006:	a		%r0, 0xfff(%r15, %r1) // insn-ID: 1, insn-mnem: a
	Implicit registers modified: cc 
0x100a:	afi		%r0, -0x80000000 // insn-ID: 6, insn-mnem: afi
	Implicit registers modified: cc 
0x1010:	br		%r7 // insn-ID: 283, insn-mnem: br
	This instruction belongs to groups: jump 
0x1012:	xiy		0x7ffff(%r15), 0x2a // insn-ID: 678, insn-mnem: xiy
	Implicit registers modified: cc 
0x1018:	xy		%r0, 0x7ffff(%r1, %r15) // insn-ID: 681, insn-mnem: xy
	Implicit registers modified: cc 
0x101e:	stmg		%r0, %r0, 0(%r15) // insn-ID: 657, insn-mnem: stmg
0x1024:	ear		%r7, %a8 // insn-ID: 383, insn-mnem: ear

****************
Platform: XCore
Code: 0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 
Disasm:
0x1000:	get		r11, ed // insn-ID: 43, insn-mnem: get
	Implicit registers modified: r11 
0x1002:	ldw		et, sp[4] // insn-ID: 66, insn-mnem: ldw
	Implicit registers read: sp 
0x1004:	setd		res[r3], r4 // insn-ID: 93, insn-mnem: setd
0x1006:	init		t[r2]:lr, r1 // insn-ID: 50, insn-mnem: init
0x100a:	divu		r9, r1, r3 // insn-ID: 26, insn-mnem: divu
0x100e:	lda16		r9, r3[-r11] // insn-ID: 62, insn-mnem: lda16
0x1012:	ldw		dp, dp[0x81c5] // insn-ID: 66, insn-mnem: ldw
0x1016:	lmul		r11, r0, r2, r5, r8, r10 // insn-ID: 68, insn-mnem: lmul
0x101a:	add		r1, r2, r3 // insn-ID: 1, insn-mnem: add

****************
Platform: M680X_6809
Code: 0x06 0x10 0x19 0x1a 0x55 0x1e 0x01 0x23 0xe9 0x31 0x06 0x34 0x55 0xa6 0x81 0xa7 0x89 0x7f 0xff 0xa6 0x9d 0x10 0x00 0xa7 0x91 0xa6 0x9f 0x10 0x00 0x11 0xac 0x99 0x10 0x00 0x39 
Disasm:
0x1000:	ror		$10 // insn-ID: 276, insn-mnem: ror
	Implicit registers read: cc 
	Implicit registers modified: cc 
0x1002:	daa		 // insn-ID: 117, insn-mnem: daa
	Implicit registers read: cc a 
	Implicit registers modified: cc a 
0x1003:	orcc		#85 // insn-ID: 243, insn-mnem: orcc
	Implicit registers read: cc 
	Implicit registers modified: cc 
0x1005:	exg		d, x // insn-ID: 153, insn-mnem: exg
	Implicit registers read: d x 
	Implicit registers modified: d x 
0x1007:	bls		$0ff2 // insn-ID: 58, insn-mnem: bls
	Implicit registers read: cc 
	This instruction belongs to groups: branch_relative jump 
0x1009:	leay		6, x // insn-ID: 209, insn-mnem: leay
	Implicit registers read: cc x 
	Implicit registers modified: cc y 
0x100b:	pshs		cc, b, x, u // insn-ID: 251, insn-mnem: pshs
	Implicit registers read: s cc b x u 
	Implicit registers modified: s 
0x100d:	lda		, x++ // insn-ID: 190, insn-mnem: lda
	Implicit registers read: cc x 
	Implicit registers modified: cc a x 
0x100f:	sta		32767, x // insn-ID: 298, insn-mnem: sta
	Implicit registers read: cc a x 
	Implicit registers modified: cc 
0x1013:	lda		[$2017, pcr] // insn-ID: 190, insn-mnem: lda
	Implicit registers read: cc pc 
	Implicit registers modified: cc a 
0x1017:	sta		[, x++] // insn-ID: 298, insn-mnem: sta
	Implicit registers read: cc a x 
	Implicit registers modified: cc x 
0x1019:	lda		[$1000] // insn-ID: 190, insn-mnem: lda
	Implicit registers read: cc 
	Implicit registers modified: cc a 
0x101d:	cmps		[4096, x] // insn-ID: 98, insn-mnem: cmps
	Implicit registers read: cc s x 
	Implicit registers modified: cc 
0x1022:	rts		 // insn-ID: 285, insn-mnem: rts
	Implicit registers read: s 
	Implicit registers modified: s pc 
	This instruction belongs to groups: return 

****************
Platform: MOS65XX
Code: 0x0d 0x34 0x12 0x08 0x09 0xff 0x10 0x80 0x20 0x00 0x00 0x98 
Disasm:
0x1000:	ora		0x1234 // insn-ID: 44, insn-mnem: ora
	Implicit registers read: A 
	Implicit registers modified: A P 
0x1003:	php		 // insn-ID: 52, insn-mnem: php
	Implicit registers read: P SP 
	Implicit registers modified: SP 
0x1004:	ora		#0xff // insn-ID: 44, insn-mnem: ora
	Implicit registers read: A 
	Implicit registers modified: A P 
0x1006:	bpl		0x0f88 // insn-ID: 12, insn-mnem: bpl
	Implicit registers read: P 
	This instruction belongs to groups: jump branch_relative 
0x1008:	jsr		0x0000 // insn-ID: 36, insn-mnem: jsr
	Implicit registers read: SP 
	Implicit registers modified: SP 
	This instruction belongs to groups: call 
0x100b:	tya		 // insn-ID: 91, insn-mnem: tya
	Implicit registers read: Y 
	Implicit registers modified: A P 

****************
Platform: eBPF
Code: 0x97 0x09 0x00 0x00 0x37 0x13 0x03 0x00 0xdc 0x02 0x00 0x00 0x20 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xdb 0x3a 0x00 0x01 0x00 0x00 0x00 0x00 0x84 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x6d 0x33 0x17 0x02 0x00 0x00 0x00 0x00 
Disasm:
0x1000:	mod64		r9, 0x31337 // insn-ID: 23, insn-mnem: mod64
	This instruction belongs to groups: alu 
0x1008:	be32		r2 // insn-ID: 31, insn-mnem: be32
	This instruction belongs to groups: alu 
0x1010:	ldb		[0x0] // insn-ID: 35, insn-mnem: ldb
	Implicit registers modified: r0 
	This instruction belongs to groups: load 
0x1018:	xadddw		[r10+0x100], r3 // insn-ID: 50, insn-mnem: xadddw
	This instruction belongs to groups: store 
0x1020:	neg		r2 // insn-ID: 9, insn-mnem: neg
	This instruction belongs to groups: alu 
0x1028:	jsgt		r3, r3, +0x217 // insn-ID: 57, insn-mnem: jsgt
	This instruction belongs to groups: jump 

****************
Platform: RISCV32
Code: 0x37 0x34 0x00 0x00 0x97 0x82 0x00 0x00 0xef 0x00 0x80 0x00 0xef 0xf0 0x1f 0xff 0xe7 0x00 0x45 0x00 0xe7 0x00 0xc0 0xff 0x63 0x05 0x41 0x00 0xe3 0x9d 0x61 0xfe 0x63 0xca 0x93 0x00 0x63 0x53 0xb5 0x00 0x63 0x65 0xd6 0x00 0x63 0x76 0xf7 0x00 0x03 0x88 0x18 0x00 0x03 0x99 0x49 0x00 0x03 0xaa 0x6a 0x00 0x03 0xcb 0x2b 0x01 0x03 0xdc 0x8c 0x01 0x23 0x86 0xad 0x03 0x23 0x9a 0xce 0x03 0x23 0x8f 0xef 0x01 0x93 0x00 0xe0 0x00 0x13 0xa1 0x01 0x01 0x13 0xb2 0x02 0x7d 0x13 0xc3 0x03 0xdd 0x13 0xe4 0xc4 0x12 0x13 0xf5 0x85 0x0c 0x13 0x96 0xe6 0x01 0x13 0xd7 0x97 0x01 0x13 0xd8 0xf8 0x40 0x33 0x89 0x49 0x01 0xb3 0x0a 0x7b 0x41 0x33 0xac 0xac 0x01 0xb3 0x3d 0xde 0x01 0x33 0xd2 0x62 0x40 0xb3 0x43 0x94 0x00 0x33 0xe5 0xc5 0x00 0xb3 0x76 0xf7 0x00 0xb3 0x54 0x39 0x01 0xb3 0x50 0x31 0x00 0x33 0x9f 0x0f 0x00 
Disasm:
0x1000:	lui		s0, 3 // insn-ID: 221, insn-mnem: lui
0x1004:	auipc		t0, 8 // insn-ID: 79, insn-mnem: auipc
0x1008:	jal		8 // insn-ID: 206, insn-mnem: jal
	This instruction belongs to groups: call 
0x100c:	jal		-0x10 // insn-ID: 206, insn-mnem: jal
	This instruction belongs to groups: call 
0x1010:	jalr		ra, a0, 4 // insn-ID: 207, insn-mnem: jalr
	This instruction belongs to groups: call 
0x1014:	jalr		ra, zero, -4 // insn-ID: 207, insn-mnem: jalr
	This instruction belongs to groups: call 
0x1018:	beq		sp, tp, 0xa // insn-ID: 80, insn-mnem: beq
	This instruction belongs to groups: branch_relative jump 
0x101c:	bne		gp, t1, -6 // insn-ID: 85, insn-mnem: bne
	This instruction belongs to groups: branch_relative jump 
0x1020:	blt		t2, s1, 0x14 // insn-ID: 83, insn-mnem: blt
	This instruction belongs to groups: branch_relative jump 
0x1024:	bge		a0, a1, 6 // insn-ID: 81, insn-mnem: bge
	This instruction belongs to groups: branch_relative jump 
0x1028:	bltu		a2, a3, 0xa // insn-ID: 84, insn-mnem: bltu
	This instruction belongs to groups: branch_relative jump 
0x102c:	bgeu		a4, a5, 0xc // insn-ID: 82, insn-mnem: bgeu
	This instruction belongs to groups: branch_relative jump 
0x1030:	lb		a6, 1(a7) // insn-ID: 208, insn-mnem: lb
0x1034:	lh		s2, 4(s3) // insn-ID: 211, insn-mnem: lh
0x1038:	lw		s4, 6(s5) // insn-ID: 222, insn-mnem: lw
0x103c:	lbu		s6, 0x12(s7) // insn-ID: 209, insn-mnem: lbu
0x1040:	lhu		s8, 0x18(s9) // insn-ID: 212, insn-mnem: lhu
0x1044:	sb		s10, 0x2c(s11) // insn-ID: 236, insn-mnem: sb
0x1048:	sh		t3, 0x34(t4) // insn-ID: 247, insn-mnem: sh
0x104c:	sb		t5, 0x1e(t6) // insn-ID: 236, insn-mnem: sb
0x1050:	addi		ra, zero, 0xe // insn-ID: 2, insn-mnem: addi
0x1054:	slti		sp, gp, 0x10 // insn-ID: 253, insn-mnem: slti
0x1058:	sltiu		tp, t0, 0x7d0 // insn-ID: 254, insn-mnem: sltiu
0x105c:	xori		t1, t2, -0x230 // insn-ID: 272, insn-mnem: xori
0x1060:	ori		s0, s1, 0x12c // insn-ID: 231, insn-mnem: ori
0x1064:	andi		a0, a1, 0xc8 // insn-ID: 78, insn-mnem: andi
0x1068:	slli		a2, a3, 0x1e // insn-ID: 249, insn-mnem: slli
0x106c:	srli		a4, a5, 0x19 // insn-ID: 262, insn-mnem: srli
0x1070:	srai		a6, a7, 0xf // insn-ID: 257, insn-mnem: srai
0x1074:	add		s2, s3, s4 // insn-ID: 1, insn-mnem: add
0x1078:	sub		s5, s6, s7 // insn-ID: 265, insn-mnem: sub
0x107c:	slt		s8, s9, s10 // insn-ID: 252, insn-mnem: slt
0x1080:	sltu		s11, t3, t4 // insn-ID: 255, insn-mnem: sltu
0x1084:	sra		tp, t0, t1 // insn-ID: 256, insn-mnem: sra
0x1088:	xor		t2, s0, s1 // insn-ID: 271, insn-mnem: xor
0x108c:	or		a0, a1, a2 // insn-ID: 230, insn-mnem: or
0x1090:	and		a3, a4, a5 // insn-ID: 77, insn-mnem: and
0x1094:	srl		s1, s2, s3 // insn-ID: 261, insn-mnem: srl
0x1098:	srl		ra, sp, gp // insn-ID: 261, insn-mnem: srl
0x109c:	sll		t5, t6, zero // insn-ID: 248, insn-mnem: sll

****************
Platform: RISCV64
Code: 0x13 0x04 0xa8 0x7a 
Disasm:
0x1000:	addi		s0, a6, 0x7aa // insn-ID: 2, insn-mnem: addi

****************
Platform: TriCore
Code: 0x16 0x01 0x20 0x01 0x1d 0x00 0x02 0x00 0x8f 0x70 0x00 0x11 0x40 0xae 0x89 0xee 0x04 0x09 0x42 0xf2 0xe2 0xf2 0xc2 0x11 0x19 0xff 0xc0 0x70 0x19 0xff 0x20 0x10 
Disasm:
0x1000:	and		d15, #1 // insn-ID: 45, insn-mnem: and
0x1002:	sub.a		sp, #1 // insn-ID: 360, insn-mnem: sub.a
0x1004:	j		#0x1008 // insn-ID: 161, insn-mnem: j
	This instruction belongs to groups: (null) 
0x1008:	and		d1, d0, #7 // insn-ID: 45, insn-mnem: and
	Implicit registers read: d0 
	Implicit registers modified: d1 
0x100c:	mov.aa		a14, sp // insn-ID: 229, insn-mnem: mov.aa
	Implicit registers read: sp 
	Implicit registers modified: a14 
0x100e:	st.w		[a14]#4, d14 // insn-ID: 350, insn-mnem: st.w
	Implicit registers read: d14 
	Implicit registers modified: a14 
0x1012:	add		d2, d15 // insn-ID: 31, insn-mnem: add
	Implicit registers read: d15 
	Implicit registers modified: d2 
	This instruction belongs to groups: (null) 
0x1014:	mul		d2, d15 // insn-ID: 273, insn-mnem: mul
	Implicit registers read: d15 
	Implicit registers modified: d2 
	This instruction belongs to groups: (null) 
0x1016:	add		d1, #1 // insn-ID: 31, insn-mnem: add
	Implicit registers modified: d1 
0x1018:	ld.w		d15, [a15]#0xdc0 // insn-ID: 173, insn-mnem: ld.w
	Implicit registers read: a15 
	Implicit registers modified: d15 
0x101c:	ld.w		d15, [a15]#0x60 // insn-ID: 173, insn-mnem: ld.w
	Implicit registers read: a15 
	Implicit registers modified: d15 

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_iter" end time: Feb 18 14:55 CET
"capstone_test_iter" time elapsed: 00:00:00
----------------------------------------------------------

5/24 Testing: capstone_test_arm
5/24 Test: capstone_test_arm
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_arm"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_arm" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: ARM
Code:0x86 0x48 0x60 0xf4 0x4d 0x0f 0xe2 0xf4 0xed 0xff 0xff 0xeb 0x04 0xe0 0x2d 0xe5 0x00 0x00 0x00 0x00 0xe0 0x83 0x22 0xe5 0xf1 0x02 0x03 0x0e 0x00 0x00 0xa0 0xe3 0x02 0x30 0xc1 0xe7 0x00 0x00 0x53 0xe3 0x00 0x02 0x01 0xf1 0x05 0x40 0xd0 0xe8 0xf4 0x80 0x00 0x00 
Disasm:
0x80001000:	vld2.32	{d20, d21}, [r0], r6
	op_count: 4
		operands[0].type: REG = d20
		operands[0].access: WRITE
		operands[1].type: REG = d21
		operands[1].access: WRITE
		operands[2].type: MEM
			operands[2].mem.base: REG = r0
		operands[2].access: READ
		operands[3].type: REG = r6
		operands[3].access: READ
	Vector-size: 32
	Registers read: r0 r6
	Registers modified: d20 d21

0x80001004:	vld4.16	{d16[], d17[], d18[], d19[]}, [r2]!
	op_count: 5
		operands[0].type: REG = d16
		operands[0].access: WRITE
		operands[1].type: REG = d17
		operands[1].access: WRITE
		operands[2].type: REG = d18
		operands[2].access: WRITE
		operands[3].type: REG = d19
		operands[3].access: WRITE
		operands[4].type: MEM
			operands[4].mem.base: REG = r2
		operands[4].access: READ
	Write-back: True
	Vector-size: 16
	Registers read: r2
	Registers modified: d16 d17 d18 d19 r2

0x80001008:	bl	#0x80000fc4
	op_count: 1
		operands[0].type: IMM = 0x80000fc4
	Registers read: pc
	Registers modified: lr pc

0x8000100c:	str	lr, [sp, #-4]!
	op_count: 2
		operands[0].type: REG = lr
		operands[0].access: READ
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0xfffffffc
		operands[1].access: WRITE
	Write-back: True
	Registers read: lr sp
	Registers modified: sp

0x80001010:	andeq	r0, r0, r0
	op_count: 3
		operands[0].type: REG = r0
		operands[0].access: WRITE
		operands[1].type: REG = r0
		operands[1].access: READ
		operands[2].type: REG = r0
		operands[2].access: READ
	Code condition: 1
	Registers read: r0
	Registers modified: r0

0x80001014:	str	r8, [r2, #-0x3e0]!
	op_count: 2
		operands[0].type: REG = r8
		operands[0].access: READ
		operands[1].type: MEM
			operands[1].mem.base: REG = r2
			operands[1].mem.disp: 0xfffffc20
		operands[1].access: WRITE
	Write-back: True
	Registers read: r8 r2
	Registers modified: r2

0x80001018:	mcreq	p2, #0, r0, c3, c1, #7
	op_count: 6
		operands[0].type: P-IMM = 2
		operands[1].type: IMM = 0x0
		operands[2].type: REG = r0
		operands[2].access: READ
		operands[3].type: C-IMM = 3
		operands[4].type: C-IMM = 1
		operands[5].type: IMM = 0x7
	Code condition: 1
	Registers read: r0

0x8000101c:	mov	r0, #0
	op_count: 2
		operands[0].type: REG = r0
		operands[0].access: WRITE
		operands[1].type: IMM = 0x0
	Registers modified: r0

0x80001020:	strb	r3, [r1, r2]
	op_count: 2
		operands[0].type: REG = r3
		operands[0].access: READ
		operands[1].type: MEM
			operands[1].mem.base: REG = r1
			operands[1].mem.index: REG = r2
		operands[1].access: WRITE
	Registers read: r3 r1 r2

0x80001024:	cmp	r3, #0
	op_count: 2
		operands[0].type: REG = r3
		operands[0].access: READ
		operands[1].type: IMM = 0x0
	Update-flags: True
	Registers read: r3
	Registers modified: cpsr

0x80001028:	setend	be
	op_count: 1
		operands[0].type: SETEND = be

0x8000102c:	ldm	r0, {r0, r2, lr} ^
	op_count: 4
		operands[0].type: REG = r0
		operands[0].access: READ
		operands[1].type: REG = r0
		operands[1].access: WRITE
		operands[2].type: REG = r2
		operands[2].access: WRITE
		operands[3].type: REG = lr
		operands[3].access: WRITE
	User-mode: True
	Registers read: r0
	Registers modified: r0 r2 lr

0x80001030:	strdeq	r8, sb, [r0], -r4
	op_count: 4
		operands[0].type: REG = r8
		operands[0].access: READ
		operands[1].type: REG = sb
		operands[1].access: READ
		operands[2].type: MEM
			operands[2].mem.base: REG = r0
		operands[2].access: READ
		operands[3].type: REG = r4
		operands[3].access: READ
		Subtracted: True
	Code condition: 1
	Write-back: True
	Registers read: r8 sb r0 r4
	Registers modified: r0

0x80001034:

****************
Platform: Thumb
Code:0x60 0xf9 0x1f 0x04 0xe0 0xf9 0x4f 0x07 0x70 0x47 0x00 0xf0 0x10 0xe8 0xeb 0x46 0x83 0xb0 0xc9 0x68 0x1f 0xb1 0x30 0xbf 0xaf 0xf3 0x20 0x84 0x52 0xf8 0x23 0xf0 
Disasm:
0x80001000:	vld3.8	{d16, d17, d18}, [r0:0x40]
	op_count: 4
		operands[0].type: REG = d16
		operands[0].access: WRITE
		operands[1].type: REG = d17
		operands[1].access: WRITE
		operands[2].type: REG = d18
		operands[2].access: WRITE
		operands[3].type: MEM
			operands[3].mem.base: REG = r0
			operands[3].mem.disp: 0x40
		operands[3].access: READ
	Vector-size: 8
	Registers read: r0
	Registers modified: d16 d17 d18

0x80001004:	vld4.16	{d16[1], d17[1], d18[1], d19[1]}, [r0]
	op_count: 5
		operands[0].type: REG = d16
		operands[0].neon_lane = 1
		operands[0].access: WRITE
		operands[1].type: REG = d17
		operands[1].neon_lane = 1
		operands[1].access: WRITE
		operands[2].type: REG = d18
		operands[2].neon_lane = 1
		operands[2].access: WRITE
		operands[3].type: REG = d19
		operands[3].neon_lane = 1
		operands[3].access: WRITE
		operands[4].type: MEM
			operands[4].mem.base: REG = r0
		operands[4].access: READ
	Vector-size: 16
	Registers read: r0
	Registers modified: d16 d17 d18 d19

0x80001008:	bx	lr
	op_count: 1
		operands[0].type: REG = lr
		operands[0].access: READ
	Registers read: lr
	Registers modified: pc

0x8000100a:	blx	#0x8000102c
	op_count: 1
		operands[0].type: IMM = 0x8000102c
	Registers read: pc
	Registers modified: lr pc

0x8000100e:	mov	fp, sp
	op_count: 2
		operands[0].type: REG = fp
		operands[0].access: WRITE
		operands[1].type: REG = sp
		operands[1].access: READ
	Registers read: sp
	Registers modified: fp

0x80001010:	sub	sp, #0xc
	op_count: 2
		operands[0].type: REG = sp
		operands[0].access: READ | WRITE
		operands[1].type: IMM = 0xc
	Registers read: sp
	Registers modified: sp

0x80001012:	ldr	r1, [r1, #0xc]
	op_count: 2
		operands[0].type: REG = r1
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = r1
			operands[1].mem.disp: 0xc
		operands[1].access: READ
	Registers read: r1
	Registers modified: r1

0x80001014:	cbz	r7, #0x8000101e
	op_count: 2
		operands[0].type: REG = r7
		operands[0].access: READ
		operands[1].type: IMM = 0x8000101e
	Registers read: r7

0x80001016:	wfi	

0x80001018:	cpsie.w	f
	CPSI-mode: 2
	CPSI-flag: 1

0x8000101c:	ldr.w	pc, [r2, r3, lsl #2]
	op_count: 2
		operands[0].type: REG = pc
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = r2
			operands[1].mem.index: REG = r3
		operands[1].access: READ
			Shift: 2 = 2
	Registers read: r2 r3
	Registers modified: pc

0x80001020:

****************
Platform: Thumb-mixed
Code:0xd1 0xe8 0x00 0xf0 0xf0 0x24 0x04 0x07 0x1f 0x3c 0xf2 0xc0 0x00 0x00 0x4f 0xf0 0x00 0x01 0x46 0x6c 
Disasm:
0x80001000:	tbb	[r1, r0]
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = r1
			operands[0].mem.index: REG = r0
		operands[0].access: READ
	Registers read: r1 r0

0x80001004:	movs	r4, #0xf0
	op_count: 2
		operands[0].type: REG = r4
		operands[0].access: WRITE
		operands[1].type: IMM = 0xf0
	Update-flags: True
	Registers modified: r4

0x80001006:	lsls	r4, r0, #0x1c
	op_count: 3
		operands[0].type: REG = r4
		operands[0].access: WRITE
		operands[1].type: REG = r0
		operands[1].access: READ
		operands[2].type: IMM = 0x1c
	Update-flags: True
	Registers read: r0
	Registers modified: r4

0x80001008:	subs	r4, #0x1f
	op_count: 2
		operands[0].type: REG = r4
		operands[0].access: READ | WRITE
		operands[1].type: IMM = 0x1f
	Update-flags: True
	Registers read: r4
	Registers modified: r4

0x8000100a:	stm	r0!, {r1, r4, r5, r6, r7}
	op_count: 6
		operands[0].type: REG = r0
		operands[0].access: READ | WRITE
		operands[1].type: REG = r1
		operands[1].access: READ
		operands[2].type: REG = r4
		operands[2].access: READ
		operands[3].type: REG = r5
		operands[3].access: READ
		operands[4].type: REG = r6
		operands[4].access: READ
		operands[5].type: REG = r7
		operands[5].access: READ
	Write-back: True
	Registers read: r0 r1 r4 r5 r6 r7
	Registers modified: r0

0x8000100c:	movs	r0, r0
	op_count: 2
		operands[0].type: REG = r0
		operands[0].access: WRITE
		operands[1].type: REG = r0
		operands[1].access: READ
	Update-flags: True
	Registers read: r0
	Registers modified: cpsr r0

0x8000100e:	mov.w	r1, #0
	op_count: 2
		operands[0].type: REG = r1
		operands[0].access: WRITE
		operands[1].type: IMM = 0x0
	Registers modified: r1

0x80001012:	ldr	r6, [r0, #0x44]
	op_count: 2
		operands[0].type: REG = r6
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = r0
			operands[1].mem.disp: 0x44
		operands[1].access: READ
	Registers read: r0
	Registers modified: r6

0x80001014:

****************
Platform: Thumb-2 & register named with numbers
Code:0x4f 0xf0 0x00 0x01 0xbd 0xe8 0x00 0x88 0xd1 0xe8 0x00 0xf0 0x18 0xbf 0xad 0xbf 0xf3 0xff 0x0b 0x0c 0x86 0xf3 0x00 0x89 0x80 0xf3 0x00 0x8c 0x4f 0xfa 0x99 0xf6 0xd0 0xff 0xa2 0x01 
Disasm:
0x80001000:	mov.w	r1, #0
	op_count: 2
		operands[0].type: REG = r1
		operands[0].access: WRITE
		operands[1].type: IMM = 0x0
	Registers modified: r1

0x80001004:	pop.w	{r11, pc}
	op_count: 2
		operands[0].type: REG = r11
		operands[0].access: WRITE
		operands[1].type: REG = pc
		operands[1].access: WRITE
	Registers read: sp
	Registers modified: sp r11 pc

0x80001008:	tbb	[r1, r0]
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = r1
			operands[0].mem.index: REG = r0
		operands[0].access: READ
	Registers read: r1 r0

0x8000100c:	it	ne
	Code condition: 2
	Registers modified: itstate

0x8000100e:	iteet	ge
	Code condition: 11
	Registers modified: itstate

0x80001010:	vdupne.8	d16, d11[1]
	op_count: 2
		operands[0].type: REG = d16
		operands[0].access: WRITE
		operands[1].type: REG = d11
		operands[1].access: READ
		operands[1].vector_index = 1
	Code condition: 2
	Vector-size: 8
	Registers read: d11
	Registers modified: d16

0x80001014:	msr	cpsr_fc, r6
	op_count: 2
		operands[0].type: SYSREG = 9
		operands[1].type: REG = r6
		operands[1].access: READ
	Registers read: r6

0x80001018:	msr	apsr_nzcvqg, r0
	op_count: 2
		operands[0].type: SYSREG = 259
		operands[1].type: REG = r0
		operands[1].access: READ
	Registers read: r0

0x8000101c:	sxtb.w	r6, r9, ror #8
	op_count: 2
		operands[0].type: REG = r6
		operands[0].access: WRITE
		operands[1].type: REG = r9
		operands[1].access: READ
			Shift: 4 = 8
	Registers read: r9
	Registers modified: r6

0x80001020:	vaddw.u16	q8, q8, d18
	op_count: 3
		operands[0].type: REG = q8
		operands[0].access: WRITE
		operands[1].type: REG = q8
		operands[1].access: READ
		operands[2].type: REG = d18
		operands[2].access: READ
	Vector-data: 10
	Registers read: q8 d18
	Registers modified: q8

0x80001024:

****************
Platform: Thumb-MClass
Code:0xef 0xf3 0x02 0x80 
Disasm:
0x80001000:	mrs	r0, eapsr
	op_count: 2
		operands[0].type: REG = r0
		operands[0].access: WRITE
		operands[1].type: SYSREG = 264
	Registers modified: r0

0x80001004:

****************
Platform: Arm-V8
Code:0xe0 0x3b 0xb2 0xee 0x42 0x00 0x01 0xe1 0x51 0xf0 0x7f 0xf5 
Disasm:
0x80001000:	vcvtt.f64.f16	d3, s1
	op_count: 2
		operands[0].type: REG = d3
		operands[0].access: WRITE
		operands[1].type: REG = s1
		operands[1].access: READ
	Vector-data: 18
	Registers read: s1
	Registers modified: d3

0x80001004:	crc32b	r0, r1, r2
	op_count: 3
		operands[0].type: REG = r0
		operands[0].access: WRITE
		operands[1].type: REG = r1
		operands[1].access: READ
		operands[2].type: REG = r2
		operands[2].access: READ
	Registers read: r1 r2
	Registers modified: r0

0x80001008:	dmb	oshld
	Memory-barrier: 2

0x8000100c:

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_arm" end time: Feb 18 14:55 CET
"capstone_test_arm" time elapsed: 00:00:00
----------------------------------------------------------

6/24 Testing: capstone_test_arm64
6/24 Test: capstone_test_arm64
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_arm64"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_arm64" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: ARM-64
Code: 0x09 0x00 0x38 0xd5 0xbf 0x40 0x00 0xd5 0x0c 0x05 0x13 0xd5 0x20 0x50 0x02 0x0e 0x20 0xe4 0x3d 0x0f 0x00 0x18 0xa0 0x5f 0xa2 0x00 0xae 0x9e 0x9f 0x37 0x03 0xd5 0xbf 0x33 0x03 0xd5 0xdf 0x3f 0x03 0xd5 0x21 0x7c 0x02 0x9b 0x21 0x7c 0x00 0x53 0x00 0x40 0x21 0x4b 0xe1 0x0b 0x40 0xb9 0x20 0x04 0x81 0xda 0x20 0x08 0x02 0x8b 0x10 0x5b 0xe8 0x3c 0xfd 0x7b 0xba 0xa9 0xfd 0xc7 0x43 0xf8 
Disasm:
0x2c:	mrs	x9, midr_el1
	op_count: 2
		operands[0].type: REG = x9
		operands[0].access: WRITE
		operands[1].type: SYS = 0xc000
		operands[1].access: READ
	Registers modified: x9

0x30:	msr	spsel, #0
	op_count: 2
		operands[0].type: PSTATE = 0x5
		operands[0].access: WRITE
		operands[1].type: IMM = 0x0
		operands[1].access: READ
	Update-flags: True
	Registers modified: nzcv

0x34:	msr	dbgdtrtx_el0, x12
	op_count: 2
		operands[0].type: SYS = 0x9828
		operands[0].access: WRITE
		operands[1].type: REG = x12
		operands[1].access: READ
	Registers read: x12

0x38:	tbx	v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b
	op_count: 5
		operands[0].type: REG = v0
		operands[0].access: READ | WRITE
			Vector Arrangement Specifier: 0x2
		operands[1].type: REG = v1
		operands[1].access: READ
			Vector Arrangement Specifier: 0x1
		operands[2].type: REG = v2
		operands[2].access: READ
			Vector Arrangement Specifier: 0x1
		operands[3].type: REG = v3
		operands[3].access: READ
			Vector Arrangement Specifier: 0x1
		operands[4].type: REG = v2
			Vector Arrangement Specifier: 0x2
	Registers read: v0 v1 v2 v3
	Registers modified: v0

0x3c:	scvtf	v0.2s, v1.2s, #3
	op_count: 3
		operands[0].type: REG = v0
		operands[0].access: WRITE
			Vector Arrangement Specifier: 0xa
		operands[1].type: REG = v1
		operands[1].access: READ
			Vector Arrangement Specifier: 0xa
		operands[2].type: IMM = 0x3
		operands[2].access: READ
	Registers read: v1
	Registers modified: v0

0x40:	fmla	s0, s0, v0.s[3]
	op_count: 3
		operands[0].type: REG = s0
		operands[0].access: READ | WRITE
		operands[1].type: REG = s0
		operands[1].access: READ
		operands[2].type: REG = v0
		operands[2].access: READ
			Vector Arrangement Specifier: 0xb
			Vector Index: 3
	Registers read: s0 v0
	Registers modified: s0

0x44:	fmov	x2, v5.d[1]
	op_count: 2
		operands[0].type: REG = x2
		operands[0].access: WRITE
		operands[1].type: REG = v5
		operands[1].access: READ
			Vector Index: 1
	Registers read: v5
	Registers modified: x2

0x48:	dsb	nsh
	op_count: 1
		operands[0].type: BARRIER = 0x7
		operands[0].access: READ

0x4c:	dmb	osh
	op_count: 1
		operands[0].type: BARRIER = 0x3
		operands[0].access: READ

0x50:	isb	

0x54:	mul	x1, x1, x2
	op_count: 3
		operands[0].type: REG = x1
		operands[0].access: WRITE
		operands[1].type: REG = x1
		operands[1].access: READ
		operands[2].type: REG = x2
		operands[2].access: READ
	Registers read: x1 x2
	Registers modified: x1

0x58:	lsr	w1, w1, #0
	op_count: 3
		operands[0].type: REG = w1
		operands[0].access: READ | WRITE
		operands[1].type: REG = w1
		operands[1].access: READ
		operands[2].type: IMM = 0x0
		operands[2].access: READ
	Registers read: w1
	Registers modified: w1

0x5c:	sub	w0, w0, w1, uxtw
	op_count: 3
		operands[0].type: REG = w0
		operands[0].access: WRITE
		operands[1].type: REG = w0
		operands[1].access: READ
		operands[2].type: REG = w1
		operands[2].access: READ
			Ext: 3
	Registers read: w0 w1
	Registers modified: w0

0x60:	ldr	w1, [sp, #8]
	op_count: 2
		operands[0].type: REG = w1
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x8
		operands[1].access: READ
	Registers read: sp
	Registers modified: w1

0x64:	cneg	x0, x1, ne
	op_count: 2
		operands[0].type: REG = x0
		operands[0].access: WRITE
		operands[1].type: REG = x1
		operands[1].access: READ
	Code-condition: 2
	Registers read: nzcv x1
	Registers modified: x0

0x68:	add	x0, x1, x2, lsl #2
	op_count: 3
		operands[0].type: REG = x0
		operands[0].access: WRITE
		operands[1].type: REG = x1
		operands[1].access: READ
		operands[2].type: REG = x2
		operands[2].access: READ
			Shift: type = 1, value = 2
	Registers read: x1 x2
	Registers modified: x0

0x6c:	ldr	q16, [x24, w8, uxtw #4]
	op_count: 2
		operands[0].type: REG = q16
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = x24
			operands[1].mem.index: REG = w8
		operands[1].access: READ
			Shift: type = 1, value = 4
			Ext: 3
	Registers read: x24 w8
	Registers modified: q16

0x70:	stp	x29, x30, [sp, #-0x60]!
	op_count: 3
		operands[0].type: REG = fp
		operands[0].access: READ
		operands[1].type: REG = lr
		operands[1].access: READ
		operands[2].type: MEM
			operands[2].mem.base: REG = sp
			operands[2].mem.disp: 0xffffffa0
		operands[2].access: READ | WRITE
	Write-back: Pre
	Registers read: fp lr sp
	Registers modified: sp

0x74:	ldr	x29, [sp], #0x3c
	op_count: 3
		operands[0].type: REG = fp
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
		operands[1].access: READ
		operands[2].type: IMM = 0x3c
		operands[2].access: READ
	Write-back: Post
	Registers read: sp
	Registers modified: fp sp

0x78:

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_arm64" end time: Feb 18 14:55 CET
"capstone_test_arm64" time elapsed: 00:00:00
----------------------------------------------------------

7/24 Testing: capstone_test_mips
7/24 Test: capstone_test_mips
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_mips"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_mips" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: MIPS-32 (Big-endian)
Code:0x0c 0x10 0x00 0x97 0x00 0x00 0x00 0x00 0x24 0x02 0x00 0x0c 0x8f 0xa2 0x00 0x00 0x34 0x21 0x34 0x56 
Disasm:
0x1000:	jal	0x40025c
	op_count: 1
		operands[0].type: IMM = 0x40025c

0x1004:	nop	

0x1008:	addiu	$v0, $zero, 0xc
	op_count: 3
		operands[0].type: REG = v0
		operands[1].type: REG = zero
		operands[2].type: IMM = 0xc

0x100c:	lw	$v0, ($sp)
	op_count: 2
		operands[0].type: REG = v0
		operands[1].type: MEM
			operands[1].mem.base: REG = sp

0x1010:	ori	$at, $at, 0x3456
	op_count: 3
		operands[0].type: REG = at
		operands[1].type: REG = at
		operands[2].type: IMM = 0x3456

0x1014:

****************
Platform: MIPS-64-EL (Little-endian)
Code:0x56 0x34 0x21 0x34 0xc2 0x17 0x01 0x00 
Disasm:
0x1000:	ori	$at, $at, 0x3456
	op_count: 3
		operands[0].type: REG = at
		operands[1].type: REG = at
		operands[2].type: IMM = 0x3456

0x1004:	srl	$v0, $at, 0x1f
	op_count: 3
		operands[0].type: REG = v0
		operands[1].type: REG = at
		operands[2].type: IMM = 0x1f

0x1008:

****************
Platform: MIPS-32R6 | Micro (Big-endian)
Code:0x00 0x07 0x00 0x07 0x00 0x11 0x93 0x7c 0x01 0x8c 0x8b 0x7c 0x00 0xc7 0x48 0xd0 
Disasm:
0x1000:	break	7, 0
	op_count: 2
		operands[0].type: IMM = 0x7
		operands[1].type: IMM = 0x0

0x1004:	wait	0x11
	op_count: 1
		operands[0].type: IMM = 0x11

0x1008:	syscall	0x18c
	op_count: 1
		operands[0].type: IMM = 0x18c

0x100c:	rotrv	$t1, $a2, $a3
	op_count: 3
		operands[0].type: REG = t1
		operands[1].type: REG = a2
		operands[2].type: REG = a3

0x1010:

****************
Platform: MIPS-32R6 (Big-endian)
Code:0xec 0x80 0x00 0x19 0x7c 0x43 0x22 0xa0 
Disasm:
0x1000:	addiupc	$a0, 0x64
	op_count: 2
		operands[0].type: REG = a0
		operands[1].type: IMM = 0x64

0x1004:	align	$a0, $v0, $v1, 2
	op_count: 4
		operands[0].type: REG = a0
		operands[1].type: REG = v0
		operands[2].type: REG = v1
		operands[3].type: IMM = 0x2

0x1008:

****************
Platform: MIPS-64-EL + Mips II (Little-endian)
Code:0x70 0x00 0xb2 0xff 
Disasm:
0x1000:	sdc3	$18, 0x70($sp)
	op_count: 2
		operands[0].type: REG = s2
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x70

0x1004:

****************
Platform: MIPS-64-EL (Little-endian)
Code:0x70 0x00 0xb2 0xff 
Disasm:
0x1000:	sd	$s2, 0x70($sp)
	op_count: 2
		operands[0].type: REG = s2
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x70

0x1004:

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_mips" end time: Feb 18 14:55 CET
"capstone_test_mips" time elapsed: 00:00:00
----------------------------------------------------------

8/24 Testing: capstone_test_ppc
8/24 Test: capstone_test_ppc
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_ppc"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_ppc" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: PPC-64
Code:0x43 0x20 0x0c 0x07 0x41 0x56 0xff 0x17 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14 
Disasm:
0x1000:	bdnzla+	0xc04
	op_count: 1
		operands[0].type: IMM = 0xc04
	Branch hint: 1

0x1004:	bdztla	4*cr5+eq, 0xffffffffffffff14
	op_count: 2
		operands[0].type: REG = cr5eq
		operands[1].type: IMM = 0xffffffffffffff14
	Branch code: 76
	Branch hint: 1

0x1008:	lwz	r1, 0(0)
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: MEM

0x100c:	lwz	r1, 0(r31)
	op_count: 2
		operands[0].type: REG = r1
		operands[1].type: MEM
			operands[1].mem.base: REG = r31

0x1010:	vpkpx	v2, v3, v4
	op_count: 3
		operands[0].type: REG = v2
		operands[1].type: REG = v3
		operands[2].type: REG = v4

0x1014:	stfs	f2, 0x80(r4)
	op_count: 2
		operands[0].type: REG = f2
		operands[1].type: MEM
			operands[1].mem.base: REG = r4
			operands[1].mem.disp: 0x80

0x1018:	crand	cr0eq, cr0un, cr1lt
	op_count: 3
		operands[0].type: REG = cr0eq
		operands[1].type: REG = cr0un
		operands[2].type: REG = cr1lt

0x101c:	cmpwi	cr2, r3, 0x80
	op_count: 3
		operands[0].type: REG = cr2
		operands[1].type: REG = r3
		operands[2].type: IMM = 0x80

0x1020:	addc	r2, r3, r4
	op_count: 3
		operands[0].type: REG = r2
		operands[1].type: REG = r3
		operands[2].type: REG = r4

0x1024:	mulhd.	r2, r3, r4
	op_count: 3
		operands[0].type: REG = r2
		operands[1].type: REG = r3
		operands[2].type: REG = r4
	Update-CR0: True

0x1028:	bdnzlrl+	
	Branch hint: 1

0x102c:	bgelrl-	cr2
	op_count: 1
		operands[0].type: REG = cr2
	Branch code: 4
	Branch hint: 2

0x1030:	bne	0x1044
	op_count: 1
		operands[0].type: IMM = 0x1044
	Branch code: 68

0x1034:

****************
Platform: PPC-64 + QPX
Code:0x10 0x60 0x2a 0x10 0x10 0x64 0x28 0x88 0x7c 0x4a 0x5d 0x0f 
Disasm:
0x1000:	qvfabs	q3, q5
	op_count: 2
		operands[0].type: REG = q3
		operands[1].type: REG = q5

0x1004:	qvfand	q3, q4, q5
	op_count: 3
		operands[0].type: REG = q3
		operands[1].type: REG = q4
		operands[2].type: REG = q5

0x1008:	qvstfsxa	q2, r10, r11
	op_count: 3
		operands[0].type: REG = q2
		operands[1].type: REG = r10
		operands[2].type: REG = r11

0x100c:

****************
Platform: PPC + PS
Code:0x10 0x00 0x1f 0xec 0xe0 0x6d 0x80 0x04 0xe4 0x6d 0x80 0x04 0x10 0x60 0x1c 0x4c 0x10 0x60 0x1c 0x0c 0xf0 0x6d 0x80 0x04 0xf4 0x6d 0x80 0x04 0x10 0x60 0x1c 0x4e 0x10 0x60 0x1c 0x0e 0x10 0x60 0x1a 0x10 0x10 0x60 0x1a 0x11 0x10 0x63 0x20 0x2a 0x10 0x63 0x20 0x2b 0x10 0x83 0x20 0x40 0x10 0x83 0x20 0xc0 0x10 0x83 0x20 0x00 0x10 0x83 0x20 0x80 0x10 0x63 0x20 0x24 0x10 0x63 0x20 0x25 0x10 0x63 0x29 0x3a 0x10 0x63 0x29 0x3b 0x10 0x63 0x29 0x1c 0x10 0x63 0x29 0x1d 0x10 0x63 0x29 0x1e 0x10 0x63 0x29 0x1f 0x10 0x63 0x24 0x20 0x10 0x63 0x24 0x21 0x10 0x63 0x24 0x60 0x10 0x63 0x24 0x61 0x10 0x63 0x24 0xa0 0x10 0x63 0x24 0xa1 0x10 0x63 0x24 0xe0 0x10 0x63 0x24 0xe1 0x10 0x60 0x20 0x90 0x10 0x60 0x20 0x91 0x10 0x63 0x29 0x38 0x10 0x63 0x29 0x39 0x10 0x63 0x01 0x32 0x10 0x63 0x01 0x33 0x10 0x63 0x01 0x18 0x10 0x63 0x01 0x19 0x10 0x63 0x01 0x1a 0x10 0x63 0x01 0x1b 0x10 0x60 0x19 0x10 0x10 0x60 0x19 0x11 0x10 0x60 0x18 0x50 0x10 0x60 0x18 0x51 0x10 0x63 0x29 0x3e 0x10 0x63 0x29 0x3f 0x10 0x63 0x29 0x3c 0x10 0x63 0x29 0x3d 0x10 0x60 0x18 0x30 0x10 0x60 0x18 0x31 0x10 0x60 0x18 0x34 0x10 0x60 0x18 0x35 0x10 0x63 0x29 0x2e 0x10 0x63 0x29 0x2f 0x10 0x63 0x20 0x28 0x10 0x63 0x20 0x29 0x10 0x63 0x29 0x14 0x10 0x63 0x29 0x15 0x10 0x63 0x29 0x16 0x10 0x63 0x29 0x17 
Disasm:
0x1000:	dcbz_l	r0, r3
	op_count: 2
		operands[0].type: REG = r0
		operands[1].type: REG = r3

0x1004:	psq_l	f3, 4(r13), 1, 0
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: MEM
			operands[1].mem.base: REG = r13
			operands[1].mem.disp: 0x4
		operands[2].type: IMM = 0x1
		operands[3].type: IMM = 0x0

0x1008:	psq_lu	f3, 4(r13), 1, 0
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: MEM
			operands[1].mem.base: REG = r13
			operands[1].mem.disp: 0x4
		operands[2].type: IMM = 0x1
		operands[3].type: IMM = 0x0

0x100c:	psq_lux	f3, r0, r3, 1, 0
	op_count: 5
		operands[0].type: REG = f3
		operands[1].type: REG = r0
		operands[2].type: REG = r3
		operands[3].type: IMM = 0x1
		operands[4].type: IMM = 0x0

0x1010:	psq_lx	f3, r0, r3, 1, 0
	op_count: 5
		operands[0].type: REG = f3
		operands[1].type: REG = r0
		operands[2].type: REG = r3
		operands[3].type: IMM = 0x1
		operands[4].type: IMM = 0x0

0x1014:	psq_st	f3, 4(r13), 1, 0
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: MEM
			operands[1].mem.base: REG = r13
			operands[1].mem.disp: 0x4
		operands[2].type: IMM = 0x1
		operands[3].type: IMM = 0x0

0x1018:	psq_stu	f3, 4(r13), 1, 0
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: MEM
			operands[1].mem.base: REG = r13
			operands[1].mem.disp: 0x4
		operands[2].type: IMM = 0x1
		operands[3].type: IMM = 0x0

0x101c:	psq_stux	f3, r0, r3, 1, 0
	op_count: 5
		operands[0].type: REG = f3
		operands[1].type: REG = r0
		operands[2].type: REG = r3
		operands[3].type: IMM = 0x1
		operands[4].type: IMM = 0x0

0x1020:	psq_stx	f3, r0, r3, 1, 0
	op_count: 5
		operands[0].type: REG = f3
		operands[1].type: REG = r0
		operands[2].type: REG = r3
		operands[3].type: IMM = 0x1
		operands[4].type: IMM = 0x0

0x1024:	ps_abs	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3

0x1028:	ps_abs.	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3
	Update-CR0: True

0x102c:	ps_add	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1030:	ps_add.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x1034:	ps_cmpo0	cr1, f3, f4
	op_count: 3
		operands[0].type: REG = cr1
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1038:	ps_cmpo1	cr1, f3, f4
	op_count: 3
		operands[0].type: REG = cr1
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x103c:	ps_cmpu0	cr1, f3, f4
	op_count: 3
		operands[0].type: REG = cr1
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1040:	ps_cmpu1	cr1, f3, f4
	op_count: 3
		operands[0].type: REG = cr1
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1044:	ps_div	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1048:	ps_div.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x104c:	ps_madd	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x1050:	ps_madd.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x1054:	ps_madds0	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x1058:	ps_madds0.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x105c:	ps_madds1	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x1060:	ps_madds1.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x1064:	ps_merge00	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1068:	ps_merge00.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x106c:	ps_merge01	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1070:	ps_merge01.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x1074:	ps_merge10	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1078:	ps_merge10.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x107c:	ps_merge11	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1080:	ps_merge11.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x1084:	ps_mr	f3, f4
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f4

0x1088:	ps_mr.	f3, f4
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f4
	Update-CR0: True

0x108c:	ps_msub	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x1090:	ps_msub.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x1094:	ps_mul	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x1098:	ps_mul.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x109c:	ps_muls0	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x10a0:	ps_muls0.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x10a4:	ps_muls1	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x10a8:	ps_muls1.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x10ac:	ps_nabs	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3

0x10b0:	ps_nabs.	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3
	Update-CR0: True

0x10b4:	ps_neg	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3

0x10b8:	ps_neg.	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3
	Update-CR0: True

0x10bc:	ps_nmadd	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x10c0:	ps_nmadd.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x10c4:	ps_nmsub	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x10c8:	ps_nmsub.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x10cc:	ps_res	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3

0x10d0:	ps_res.	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3
	Update-CR0: True

0x10d4:	ps_rsqrte	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3

0x10d8:	ps_rsqrte.	f3, f3
	op_count: 2
		operands[0].type: REG = f3
		operands[1].type: REG = f3
	Update-CR0: True

0x10dc:	ps_sel	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x10e0:	ps_sel.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x10e4:	ps_sub	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4

0x10e8:	ps_sub.	f3, f3, f4
	op_count: 3
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
	Update-CR0: True

0x10ec:	ps_sum0	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x10f0:	ps_sum0.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x10f4:	ps_sum1	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5

0x10f8:	ps_sum1.	f3, f3, f4, f5
	op_count: 4
		operands[0].type: REG = f3
		operands[1].type: REG = f3
		operands[2].type: REG = f4
		operands[3].type: REG = f5
	Update-CR0: True

0x10fc:

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_ppc" end time: Feb 18 14:55 CET
"capstone_test_ppc" time elapsed: 00:00:00
----------------------------------------------------------

9/24 Testing: capstone_test_x86
9/24 Test: capstone_test_x86
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_x86"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_x86" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: X86 16bit (Intel syntax)
Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 0x66 0xe9 0xb8 0x00 0x00 0x00 0x67 0xff 0xa0 0x23 0x01 0x00 0x00 0x66 0xe8 0xcb 0x00 0x00 0x00 0x74 0xfc 
Disasm:
0x1000:	lea	cx, [si + 0x32]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x4c
	modrm_offset: 0x1
	disp: 0x32
	disp_offset: 0x2
	disp_size: 0x1
	op_count: 2
		operands[0].type: REG = cx
		operands[0].size: 2
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = si
			operands[1].mem.disp: 0x32
		operands[1].size: 2
		operands[1].access: READ
	Registers read: si
	Registers modified: cx

0x1003:	or	byte ptr [bx + di], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x08 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x1
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: REG = al
		operands[1].size: 1
		operands[1].access: READ
	Registers read: bx di al
	Registers modified: flags
	EFLAGS: MOD_SF MOD_ZF MOD_PF RESET_OF RESET_CF UNDEF_AF

0x1005:	fadd	dword ptr [bx + di + 0x34c6]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xd8 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x81
	modrm_offset: 0x1
	disp: 0x34c6
	disp_offset: 0x2
	disp_size: 0x2
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
			operands[0].mem.disp: 0x34c6
		operands[0].size: 4
		operands[0].access: READ
	Registers read: bx di
	Registers modified: fpsw
	FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3

0x1009:	adc	al, byte ptr [bx + si]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x12 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: REG = al
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = bx
			operands[1].mem.index: REG = si
		operands[1].size: 1
		operands[1].access: READ
	Registers read: flags al bx si
	Registers modified: flags al
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF TEST_CF

0x100b:	add	byte ptr [di], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x5
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = di
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: REG = al
		operands[1].size: 1
		operands[1].access: READ
	Registers read: di al
	Registers modified: flags
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x100d:	and	ax, word ptr [bx + di]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x23 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x1
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: REG = ax
		operands[0].size: 2
		operands[0].access: READ | WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = bx
			operands[1].mem.index: REG = di
		operands[1].size: 2
		operands[1].access: READ
	Registers read: ax bx di
	Registers modified: flags ax
	EFLAGS: MOD_SF MOD_ZF MOD_PF RESET_OF RESET_CF UNDEF_AF

0x100f:	add	byte ptr [bx + si], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = si
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: REG = al
		operands[1].size: 1
		operands[1].access: READ
	Registers read: bx si al
	Registers modified: flags
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1011:	mov	ax, word ptr ss:[si + 0x2391]
	Prefix:0x00 0x36 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x84
	modrm_offset: 0x2
	disp: 0x2391
	disp_offset: 0x3
	disp_size: 0x2
	op_count: 2
		operands[0].type: REG = ax
		operands[0].size: 2
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.segment: REG = ss
			operands[1].mem.base: REG = si
			operands[1].mem.disp: 0x2391
		operands[1].size: 2
		operands[1].access: READ
	Registers read: ss si
	Registers modified: ax

0x1016:	add	word ptr [bx + si], ax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x01 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = si
		operands[0].size: 2
		operands[0].access: READ | WRITE
		operands[1].type: REG = ax
		operands[1].size: 2
		operands[1].access: READ
	Registers read: bx si ax
	Registers modified: flags
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1018:	add	byte ptr [bx + di - 0x73], al
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x41
	modrm_offset: 0x1
	disp: 0xffffffffffffff8d
	disp_offset: 0x2
	disp_size: 0x1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
			operands[0].mem.disp: 0xffffffffffffff8d
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: REG = al
		operands[1].size: 1
		operands[1].access: READ
	Registers read: bx di al
	Registers modified: flags
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x101b:	test	byte ptr [bx + di], bh
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x84 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x39
	modrm_offset: 0x1
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
			operands[0].mem.index: REG = di
		operands[0].size: 1
		operands[1].type: REG = bh
		operands[1].size: 1
	Registers read: bx di

0x101d:	mov	word ptr [bx], sp
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x89 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x67
	modrm_offset: 0x1
	disp: 0x0
	disp_offset: 0x2
	disp_size: 0x1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = bx
		operands[0].size: 2
		operands[0].access: WRITE
		operands[1].type: REG = sp
		operands[1].size: 2
		operands[1].access: READ
	Registers read: bx sp

0x1020:	add	byte ptr [di - 0x7679], cl
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x8d
	modrm_offset: 0x1
	disp: 0xffffffffffff8987
	disp_offset: 0x2
	disp_size: 0x2
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = di
			operands[0].mem.disp: 0xffffffffffff8987
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: REG = cl
		operands[1].size: 1
		operands[1].access: READ
	Registers read: di cl
	Registers modified: flags
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1024:	add	byte ptr [eax], al
	Prefix:0x00 0x00 0x00 0x67 
	Opcode:0x00 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	modrm_offset: 0x2
	disp: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = eax
		operands[0].size: 1
		operands[0].access: READ | WRITE
		operands[1].type: REG = al
		operands[1].size: 1
		operands[1].access: READ
	Registers read: eax al
	Registers modified: flags
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1027:	mov	ah, 0xc6
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xb4 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	imm_count: 1
		imms[1]: 0xc6
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 2
		operands[0].type: REG = ah
		operands[0].size: 1
		operands[0].access: WRITE
		operands[1].type: IMM = 0xc6
		operands[1].size: 1
	Registers modified: ah

0x1029:	jmp	0x10e7
	Prefix:0x00 0x00 0x66 0x00 
	Opcode:0xe9 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	imm_count: 1
		imms[1]: 0x10e7
	imm_offset: 0x2
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0x10e7
		operands[0].size: 4

0x102f:	jmp	word ptr [eax + 0x123]
	Prefix:0x00 0x00 0x00 0x67 
	Opcode:0xff 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xa0
	modrm_offset: 0x2
	disp: 0x123
	disp_offset: 0x3
	disp_size: 0x4
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = eax
			operands[0].mem.disp: 0x123
		operands[0].size: 2
		operands[0].access: READ
	Registers read: eax

0x1036:	call	0x1107
	Prefix:0x00 0x00 0x66 0x00 
	Opcode:0xe8 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	imm_count: 1
		imms[1]: 0x1107
	imm_offset: 0x2
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0x1107
		operands[0].size: 4
	Registers read: esp eip
	Registers modified: esp

0x103c:	je	0x103a
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x74 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 2
	modrm: 0x0
	disp: 0x0
	imm_count: 1
		imms[1]: 0x103a
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 1
		operands[0].type: IMM = 0x103a
		operands[0].size: 2
	Registers read: flags
	EFLAGS: TEST_ZF

0x103e:

****************
Platform: X86 32 (AT&T syntax)
Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 0xe9 0xea 0xbe 0xad 0xde 0xff 0xa0 0x23 0x01 0x00 0x00 0xe8 0xdf 0xbe 0xad 0xde 0x74 0xff 
Disasm:
0x1000:	leal	8(%edx, %esi), %ecx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x4c
	modrm_offset: 0x1
	disp: 0x8
	disp_offset: 0x3
	disp_size: 0x1
	sib: 0x32
		sib_base: edx
		sib_index: esi
		sib_scale: 1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = edx
			operands[0].mem.index: REG = esi
			operands[0].mem.disp: 0x8
		operands[0].size: 4
		operands[0].access: READ
		operands[1].type: REG = ecx
		operands[1].size: 4
		operands[1].access: WRITE
	Registers read: edx esi
	Registers modified: ecx

0x1004:	addl	%ebx, %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x01 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xd8
	modrm_offset: 0x1
	disp: 0x0
	sib: 0x0
	op_count: 2
		operands[0].type: REG = ebx
		operands[0].size: 4
		operands[0].access: READ
		operands[1].type: REG = eax
		operands[1].size: 4
		operands[1].access: READ | WRITE
	Registers read: ebx eax
	Registers modified: eflags eax
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1006:	addl	$0x1234, %esi
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x81 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xc6
	modrm_offset: 0x1
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x1234
	imm_offset: 0x2
	imm_size: 0x4
	op_count: 2
		operands[0].type: IMM = 0x1234
		operands[0].size: 4
		operands[1].type: REG = esi
		operands[1].size: 4
		operands[1].access: READ | WRITE
	Registers read: esi
	Registers modified: eflags esi
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x100c:	addl	$0x123, %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x05 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x123
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 2
		operands[0].type: IMM = 0x123
		operands[0].size: 4
		operands[1].type: REG = eax
		operands[1].size: 4
		operands[1].access: READ | WRITE
	Registers read: eax
	Registers modified: eflags eax
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1011:	movl	%ss:0x123(%ecx, %edx, 4), %eax
	Prefix:0x00 0x36 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	modrm_offset: 0x2
	disp: 0x123
	disp_offset: 0x4
	disp_size: 0x4
	sib: 0x91
		sib_base: ecx
		sib_index: edx
		sib_scale: 4
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.segment: REG = ss
			operands[0].mem.base: REG = ecx
			operands[0].mem.index: REG = edx
			operands[0].mem.scale: 4
			operands[0].mem.disp: 0x123
		operands[0].size: 4
		operands[0].access: READ
		operands[1].type: REG = eax
		operands[1].size: 4
		operands[1].access: WRITE
	Registers read: ss ecx edx
	Registers modified: eax

0x1019:	incl	%ecx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x41 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: REG = ecx
		operands[0].size: 4
		operands[0].access: READ | WRITE
	Registers read: ecx
	Registers modified: eflags ecx
	EFLAGS: MOD_AF MOD_SF MOD_ZF MOD_PF MOD_OF

0x101a:	leal	0x6789(%ecx, %edi), %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	modrm_offset: 0x1
	disp: 0x6789
	disp_offset: 0x3
	disp_size: 0x4
	sib: 0x39
		sib_base: ecx
		sib_index: edi
		sib_scale: 1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = ecx
			operands[0].mem.index: REG = edi
			operands[0].mem.disp: 0x6789
		operands[0].size: 4
		operands[0].access: READ
		operands[1].type: REG = eax
		operands[1].size: 4
		operands[1].access: WRITE
	Registers read: ecx edi
	Registers modified: eax

0x1021:	leal	0x6789(%edi), %eax
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x87
	modrm_offset: 0x1
	disp: 0x6789
	disp_offset: 0x2
	disp_size: 0x4
	sib: 0x0
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = edi
			operands[0].mem.disp: 0x6789
		operands[0].size: 4
		operands[0].access: READ
		operands[1].type: REG = eax
		operands[1].size: 4
		operands[1].access: WRITE
	Registers read: edi
	Registers modified: eax

0x1027:	movb	$0xc6, %ah
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xb4 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xc6
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 2
		operands[0].type: IMM = 0xc6
		operands[0].size: 1
		operands[1].type: REG = ah
		operands[1].size: 1
		operands[1].access: WRITE
	Registers modified: ah

0x1029:	jmp	0xdeadcf18
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xe9 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xdeadcf18
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0xdeadcf18
		operands[0].size: 4

0x102e:	jmpl	*0x123(%eax)
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xff 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xa0
	modrm_offset: 0x1
	disp: 0x123
	disp_offset: 0x2
	disp_size: 0x4
	sib: 0x0
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = eax
			operands[0].mem.disp: 0x123
		operands[0].size: 4
		operands[0].access: READ
	Registers read: eax

0x1034:	calll	0xdeadcf18
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xe8 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xdeadcf18
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0xdeadcf18
		operands[0].size: 4
	Registers read: esp eip
	Registers modified: esp

0x1039:	je	0x103a
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x74 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x103a
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 1
		operands[0].type: IMM = 0x103a
		operands[0].size: 4
	Registers read: eflags
	EFLAGS: TEST_ZF

0x103b:

****************
Platform: X86 32 (Intel syntax)
Code:0x8d 0x4c 0x32 0x08 0x01 0xd8 0x81 0xc6 0x34 0x12 0x00 0x00 0x05 0x23 0x01 0x00 0x00 0x36 0x8b 0x84 0x91 0x23 0x01 0x00 0x00 0x41 0x8d 0x84 0x39 0x89 0x67 0x00 0x00 0x8d 0x87 0x89 0x67 0x00 0x00 0xb4 0xc6 0xe9 0xea 0xbe 0xad 0xde 0xff 0xa0 0x23 0x01 0x00 0x00 0xe8 0xdf 0xbe 0xad 0xde 0x74 0xff 
Disasm:
0x1000:	lea	ecx, [edx + esi + 8]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x4c
	modrm_offset: 0x1
	disp: 0x8
	disp_offset: 0x3
	disp_size: 0x1
	sib: 0x32
		sib_base: edx
		sib_index: esi
		sib_scale: 1
	op_count: 2
		operands[0].type: REG = ecx
		operands[0].size: 4
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = edx
			operands[1].mem.index: REG = esi
			operands[1].mem.disp: 0x8
		operands[1].size: 4
		operands[1].access: READ
	Registers read: edx esi
	Registers modified: ecx

0x1004:	add	eax, ebx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x01 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xd8
	modrm_offset: 0x1
	disp: 0x0
	sib: 0x0
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[0].access: READ | WRITE
		operands[1].type: REG = ebx
		operands[1].size: 4
		operands[1].access: READ
	Registers read: eax ebx
	Registers modified: eflags eax
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1006:	add	esi, 0x1234
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x81 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xc6
	modrm_offset: 0x1
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x1234
	imm_offset: 0x2
	imm_size: 0x4
	op_count: 2
		operands[0].type: REG = esi
		operands[0].size: 4
		operands[0].access: READ | WRITE
		operands[1].type: IMM = 0x1234
		operands[1].size: 4
	Registers read: esi
	Registers modified: eflags esi
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x100c:	add	eax, 0x123
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x05 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x123
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[0].access: READ | WRITE
		operands[1].type: IMM = 0x123
		operands[1].size: 4
	Registers read: eax
	Registers modified: eflags eax
	EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF

0x1011:	mov	eax, dword ptr ss:[ecx + edx*4 + 0x123]
	Prefix:0x00 0x36 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	modrm_offset: 0x2
	disp: 0x123
	disp_offset: 0x4
	disp_size: 0x4
	sib: 0x91
		sib_base: ecx
		sib_index: edx
		sib_scale: 4
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.segment: REG = ss
			operands[1].mem.base: REG = ecx
			operands[1].mem.index: REG = edx
			operands[1].mem.scale: 4
			operands[1].mem.disp: 0x123
		operands[1].size: 4
		operands[1].access: READ
	Registers read: ss ecx edx
	Registers modified: eax

0x1019:	inc	ecx
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x41 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: REG = ecx
		operands[0].size: 4
		operands[0].access: READ | WRITE
	Registers read: ecx
	Registers modified: eflags ecx
	EFLAGS: MOD_AF MOD_SF MOD_ZF MOD_PF MOD_OF

0x101a:	lea	eax, [ecx + edi + 0x6789]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x84
	modrm_offset: 0x1
	disp: 0x6789
	disp_offset: 0x3
	disp_size: 0x4
	sib: 0x39
		sib_base: ecx
		sib_index: edi
		sib_scale: 1
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = ecx
			operands[1].mem.index: REG = edi
			operands[1].mem.disp: 0x6789
		operands[1].size: 4
		operands[1].access: READ
	Registers read: ecx edi
	Registers modified: eax

0x1021:	lea	eax, [edi + 0x6789]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8d 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x87
	modrm_offset: 0x1
	disp: 0x6789
	disp_offset: 0x2
	disp_size: 0x4
	sib: 0x0
	op_count: 2
		operands[0].type: REG = eax
		operands[0].size: 4
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = edi
			operands[1].mem.disp: 0x6789
		operands[1].size: 4
		operands[1].access: READ
	Registers read: edi
	Registers modified: eax

0x1027:	mov	ah, 0xc6
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xb4 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xc6
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 2
		operands[0].type: REG = ah
		operands[0].size: 1
		operands[0].access: WRITE
		operands[1].type: IMM = 0xc6
		operands[1].size: 1
	Registers modified: ah

0x1029:	jmp	0xdeadcf18
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xe9 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xdeadcf18
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0xdeadcf18
		operands[0].size: 4

0x102e:	jmp	dword ptr [eax + 0x123]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xff 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0xa0
	modrm_offset: 0x1
	disp: 0x123
	disp_offset: 0x2
	disp_size: 0x4
	sib: 0x0
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = eax
			operands[0].mem.disp: 0x123
		operands[0].size: 4
		operands[0].access: READ
	Registers read: eax

0x1034:	call	0xdeadcf18
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xe8 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xdeadcf18
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0xdeadcf18
		operands[0].size: 4
	Registers read: esp eip
	Registers modified: esp

0x1039:	je	0x103a
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x74 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 4
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x103a
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 1
		operands[0].type: IMM = 0x103a
		operands[0].size: 4
	Registers read: eflags
	EFLAGS: TEST_ZF

0x103b:

****************
Platform: X86 64 (Intel syntax)
Code:0x55 0x48 0x8b 0x05 0xb8 0x13 0x00 0x00 0xe9 0xea 0xbe 0xad 0xde 0xff 0x25 0x23 0x01 0x00 0x00 0xe8 0xdf 0xbe 0xad 0xde 0x74 0xff 
Disasm:
0x1000:	push	rbp
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x55 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 8
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	op_count: 1
		operands[0].type: REG = rbp
		operands[0].size: 8
		operands[0].access: READ
	Registers read: rsp rbp
	Registers modified: rsp

0x1001:	mov	rax, qword ptr [rip + 0x13b8]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x8b 0x00 0x00 0x00 
	rex: 0x48
	addr_size: 8
	modrm: 0x5
	modrm_offset: 0x2
	disp: 0x13b8
	disp_offset: 0x3
	disp_size: 0x4
	sib: 0x0
	op_count: 2
		operands[0].type: REG = rax
		operands[0].size: 8
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = rip
			operands[1].mem.disp: 0x13b8
		operands[1].size: 8
		operands[1].access: READ
	Registers read: rip
	Registers modified: rax

0x1008:	jmp	0xffffffffdeadcef7
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xe9 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 8
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xffffffffdeadcef7
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0xffffffffdeadcef7
		operands[0].size: 8

0x100d:	jmp	qword ptr [rip + 0x123]
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xff 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 8
	modrm: 0x25
	modrm_offset: 0x1
	disp: 0x123
	disp_offset: 0x2
	disp_size: 0x4
	sib: 0x0
	op_count: 1
		operands[0].type: MEM
			operands[0].mem.base: REG = rip
			operands[0].mem.disp: 0x123
		operands[0].size: 8
		operands[0].access: READ
	Registers read: rip

0x1013:	call	0xffffffffdeadcef7
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0xe8 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 8
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0xffffffffdeadcef7
	imm_offset: 0x1
	imm_size: 0x4
	op_count: 1
		operands[0].type: IMM = 0xffffffffdeadcef7
		operands[0].size: 8
	Registers read: rsp rip
	Registers modified: rsp

0x1018:	je	0x1019
	Prefix:0x00 0x00 0x00 0x00 
	Opcode:0x74 0x00 0x00 0x00 
	rex: 0x0
	addr_size: 8
	modrm: 0x0
	disp: 0x0
	sib: 0x0
	imm_count: 1
		imms[1]: 0x1019
	imm_offset: 0x1
	imm_size: 0x1
	op_count: 1
		operands[0].type: IMM = 0x1019
		operands[0].size: 8
	Registers read: rflags
	EFLAGS: TEST_ZF

0x101a:

<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_x86" end time: Feb 18 14:55 CET
"capstone_test_x86" time elapsed: 00:00:00
----------------------------------------------------------

10/24 Testing: capstone_test_customized_mnem
10/24 Test: capstone_test_customized_mnem
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_customized_mnem"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_customized_mnem" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
Disassemble X86 code with default instruction mnemonic
75 01 		jne	0x1003

Now customize engine to change mnemonic from 'JNE' to 'JNZ'
75 01 		jnz	0x1003

Reset engine to use the default mnemonic
75 01 		jne	0x1003
<end of output>
Test time =   0.05 sec
----------------------------------------------------------
Test Passed.
"capstone_test_customized_mnem" end time: Feb 18 14:55 CET
"capstone_test_customized_mnem" time elapsed: 00:00:00
----------------------------------------------------------

11/24 Testing: capstone_test_sparc
11/24 Test: capstone_test_sparc
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_sparc"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_sparc" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: Sparc
Code:0x80 0xa0 0x40 0x02 0x85 0xc2 0x60 0x08 0x85 0xe8 0x20 0x01 0x81 0xe8 0x00 0x00 0x90 0x10 0x20 0x01 0xd5 0xf6 0x10 0x16 0x21 0x00 0x00 0x0a 0x86 0x00 0x40 0x02 0x01 0x00 0x00 0x00 0x12 0xbf 0xff 0xff 0x10 0xbf 0xff 0xff 0xa0 0x02 0x00 0x09 0x0d 0xbf 0xff 0xff 0xd4 0x20 0x60 0x00 0xd4 0x4e 0x00 0x16 0x2a 0xc2 0x80 0x03 
Disasm:
0x1000:	cmp	%g1, %g2
	op_count: 2
		operands[0].type: REG = g1
		operands[1].type: REG = g2

0x1004:	jmpl	%o1+8, %g2
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = o1
			operands[0].mem.disp: 0x8
		operands[1].type: REG = g2

0x1008:	restore	%g0, 1, %g2
	op_count: 3
		operands[0].type: REG = g0
		operands[1].type: IMM = 0x1
		operands[2].type: REG = g2

0x100c:	restore	

0x1010:	mov	1, %o0
	op_count: 2
		operands[0].type: IMM = 0x1
		operands[1].type: REG = o0

0x1014:	casx	[%i0], %l6, %o2
	op_count: 3
		operands[0].type: MEM
			operands[0].mem.base: REG = i0
		operands[1].type: REG = l6
		operands[2].type: REG = o2

0x1018:	sethi	0xa, %l0
	op_count: 2
		operands[0].type: IMM = 0xa
		operands[1].type: REG = l0

0x101c:	add	%g1, %g2, %g3
	op_count: 3
		operands[0].type: REG = g1
		operands[1].type: REG = g2
		operands[2].type: REG = g3

0x1020:	nop	

0x1024:	bne	0x1020
	op_count: 1
		operands[0].type: IMM = 0x1020
	Code condition: 256

0x1028:	ba	0x1024
	op_count: 1
		operands[0].type: IMM = 0x1024

0x102c:	add	%o0, %o1, %l0
	op_count: 3
		operands[0].type: REG = o0
		operands[1].type: REG = o1
		operands[2].type: REG = l0

0x1030:	fbg	0x102c
	op_count: 1
		operands[0].type: IMM = 0x102c
	Code condition: 278

0x1034:	st	%o2, [%g1]
	op_count: 2
		operands[0].type: REG = o2
		operands[1].type: MEM
			operands[1].mem.base: REG = g1

0x1038:	ldsb	[%i0+%l6], %o2
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = i0
			operands[0].mem.index: REG = l6
		operands[1].type: REG = o2

0x103c:	brnz,a,pn	%o2, 0x1048
	op_count: 2
		operands[0].type: REG = o2
		operands[1].type: IMM = 0x1048
	Hint code: 5

0x1040:

****************
Platform: SparcV9
Code:0x81 0xa8 0x0a 0x24 0x89 0xa0 0x10 0x20 0x89 0xa0 0x1a 0x60 0x89 0xa0 0x00 0xe0 
Disasm:
0x1000:	fcmps	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x1004:	fstox	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x1008:	fqtoi	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x100c:	fnegq	%f0, %f4
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: REG = f4

0x1010:

<end of output>
Test time =   0.04 sec
----------------------------------------------------------
Test Passed.
"capstone_test_sparc" end time: Feb 18 14:55 CET
"capstone_test_sparc" time elapsed: 00:00:00
----------------------------------------------------------

12/24 Testing: capstone_test_systemz
12/24 Test: capstone_test_systemz
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_systemz"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_systemz" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: SystemZ
Code:0xed 0x00 0x00 0x00 0x00 0x1a 0x5a 0x0f 0x1f 0xff 0xc2 0x09 0x80 0x00 0x00 0x00 0x07 0xf7 0xeb 0x2a 0xff 0xff 0x7f 0x57 0xe3 0x01 0xff 0xff 0x7f 0x57 0xeb 0x00 0xf0 0x00 0x00 0x24 0xb2 0x4f 0x00 0x78 0xec 0x18 0x00 0x00 0xc1 0x7f 
Disasm:
0x1000:	adb	%f0, 0
	op_count: 2
		operands[0].type: REG = f0
		operands[1].type: IMM = 0x0

0x1006:	a	%r0, 0xfff(%r15, %r1)
	op_count: 2
		operands[0].type: REG = 0
		operands[1].type: MEM
			operands[1].mem.base: REG = 1
			operands[1].mem.index: REG = 15
			operands[1].mem.disp: 0xfff

0x100a:	afi	%r0, -0x80000000
	op_count: 2
		operands[0].type: REG = 0
		operands[1].type: IMM = 0xffffffff80000000

0x1010:	br	%r7
	op_count: 1
		operands[0].type: REG = 7

0x1012:	xiy	0x7ffff(%r15), 0x2a
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = 15
			operands[0].mem.disp: 0x7ffff
		operands[1].type: IMM = 0x2a

0x1018:	xy	%r0, 0x7ffff(%r1, %r15)
	op_count: 2
		operands[0].type: REG = 0
		operands[1].type: MEM
			operands[1].mem.base: REG = 15
			operands[1].mem.index: REG = 1
			operands[1].mem.disp: 0x7ffff

0x101e:	stmg	%r0, %r0, 0(%r15)
	op_count: 3
		operands[0].type: REG = 0
		operands[1].type: REG = 0
		operands[2].type: MEM
			operands[2].mem.base: REG = 15

0x1024:	ear	%r7, %a8
	op_count: 2
		operands[0].type: REG = 7
		operands[1].type: REG = a8

0x1028:	clije	%r1, 0xc1, 0x1028
	op_count: 3
		operands[0].type: REG = 1
		operands[1].type: IMM = 0xc1
		operands[2].type: IMM = 0x1028

0x102e:

<end of output>
Test time =   0.04 sec
----------------------------------------------------------
Test Passed.
"capstone_test_systemz" end time: Feb 18 14:55 CET
"capstone_test_systemz" time elapsed: 00:00:00
----------------------------------------------------------

13/24 Testing: capstone_test_xcore
13/24 Test: capstone_test_xcore
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_xcore"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_xcore" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: XCore
Code:0xfe 0x0f 0xfe 0x17 0x13 0x17 0xc6 0xfe 0xec 0x17 0x97 0xf8 0xec 0x4f 0x1f 0xfd 0xec 0x37 0x07 0xf2 0x45 0x5b 0xf9 0xfa 0x02 0x06 0x1b 0x10 0x09 0xfd 0xec 0xa7 
Disasm:
0x1000:	get	r11, ed
	op_count: 2
		operands[0].type: REG = r11
		operands[1].type: REG = ed

0x1002:	ldw	et, sp[4]
	op_count: 2
		operands[0].type: REG = et
		operands[1].type: MEM
			operands[1].mem.base: REG = sp
			operands[1].mem.disp: 0x4

0x1004:	setd	res[r3], r4
	op_count: 1
		operands[0].type: REG = r4

0x1006:	init	t[r2]:lr, r1
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = r2
			operands[0].mem.index: REG = lr
		operands[1].type: REG = r1

0x100a:	divu	r9, r1, r3
	op_count: 3
		operands[0].type: REG = r9
		operands[1].type: REG = r1
		operands[2].type: REG = r3

0x100e:	lda16	r9, r3[-r11]
	op_count: 1
		operands[0].type: REG = r9

0x1012:	ldw	dp, dp[0x81c5]
	op_count: 1
		operands[0].type: REG = dp

0x1016:	lmul	r11, r0, r2, r5, r8, r10
	op_count: 6
		operands[0].type: REG = r11
		operands[1].type: REG = r0
		operands[2].type: REG = r2
		operands[3].type: REG = r5
		operands[4].type: REG = r8
		operands[5].type: REG = r10

0x101a:	add	r1, r2, r3
	op_count: 3
		operands[0].type: REG = r1
		operands[1].type: REG = r2
		operands[2].type: REG = r3

0x101c:	ldaw	r8, r2[-9]
	op_count: 1
		operands[0].type: REG = r8

0x1020:

<end of output>
Test time =   0.04 sec
----------------------------------------------------------
Test Passed.
"capstone_test_xcore" end time: Feb 18 14:55 CET
"capstone_test_xcore" time elapsed: 00:00:00
----------------------------------------------------------

14/24 Testing: capstone_test_m68k
14/24 Test: capstone_test_m68k
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_m68k"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_m68k" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: M68K
Code: 0xf0 0x10 0xf0 0x00 0x48 0xaf 0xff 0xff 0x7f 0xff 0x11 0xb0 0x01 0x37 0x7f 0xff 0xff 0xff 0x12 0x34 0x56 0x78 0x01 0x33 0x10 0x10 0x10 0x10 0x32 0x32 0x32 0x32 0x4c 0x00 0x54 0x04 0x48 0xe7 0xe0 0x30 0x4c 0xdf 0x0c 0x07 0xd4 0x40 0x87 0x5a 0x4e 0x71 0x02 0xb4 0xc0 0xde 0xc0 0xde 0x5c 0x00 0x1d 0x80 0x71 0x12 0x01 0x23 0xf2 0x3c 0x44 0x22 0x40 0x49 0x0e 0x56 0x54 0xc5 0xf2 0x3c 0x44 0x00 0x44 0x7a 0x00 0x00 0xf2 0x00 0x0a 0x28 0x4e 0xb9 0x00 0x00 0x00 0x12 0x4e 0x75 
Disasm:
0x1000:	fmovem	#$0, (a0)
	op_count: 2
	reading from reg: a0
	groups_count: 0
		operands[0].type: REG_BITS = $0
		operands[1].type: MEM
		address mode: Register Indirect - Address

0x1004:	movem.w	d0-d7/a0-a7, $7fff(a7)
	op_count: 2
	reading from reg: d0
	reading from reg: d1
	reading from reg: d2
	reading from reg: d3
	reading from reg: d4
	reading from reg: d5
	reading from reg: d6
	reading from reg: d7
	reading from reg: a0
	reading from reg: a1
	reading from reg: a2
	reading from reg: a3
	reading from reg: a4
	reading from reg: a5
	reading from reg: a6
	reading from reg: a7
	groups_count: 0
		operands[0].type: REG_BITS = $ffff
		operands[1].type: MEM
			operands[1].mem.base: REG = a7
			operands[1].mem.disp: 0x7fff
		address mode: Register Indirect - Address with Displacement

0x100a:	move.b	([$7fffffff, a0], d0.w, $12345678), ([$10101010, a0, d0.w], $32323232)
	op_count: 2
	reading from reg: d0
	reading from reg: a0
	groups_count: 0
		operands[0].type: MEM
			operands[0].mem.base: REG = a0
			operands[0].mem.index: REG = d0
			operands[0].mem.index: size = w
		address mode: Memory indirect - Postindex
		operands[1].type: MEM
			operands[1].mem.base: REG = a0
			operands[1].mem.index: REG = d0
			operands[1].mem.index: size = w
		address mode: Memory indirect - Preindex

0x1020:	mulu.l	d0, d4:d5
	op_count: 2
	reading from reg: d0
	writing to reg:   d4
	writing to reg:   d5
	groups_count: 0
		operands[0].type: REG = d0
		operands[1].type: REG_PAIR = (d4, d5)

0x1024:	movem.l	d0-d2/a2-a3, -(a7)
	op_count: 2
	reading from reg: d0
	reading from reg: d1
	reading from reg: d2
	reading from reg: a2
	reading from reg: a3
	writing to reg:   a7
	groups_count: 0
		operands[0].type: REG_BITS = $c07
		operands[1].type: MEM
		address mode: Register Indirect - Address with Predecrement

0x1028:	movem.l	(a7)+, d0-d2/a2-a3
	op_count: 2
	writing to reg:   a7
	writing to reg:   d0
	writing to reg:   d1
	writing to reg:   d2
	writing to reg:   a2
	writing to reg:   a3
	groups_count: 0
		operands[0].type: MEM
		address mode: Register Indirect - Address with Postincrement
		operands[1].type: REG_BITS = $c07

0x102c:	add.w	d0, d2
	op_count: 2
	reading from reg: d0
	writing to reg:   d2
	groups_count: 0
		operands[0].type: REG = d0
		operands[1].type: REG = d2

0x102e:	or.w	d3, (a2)+
	op_count: 2
	reading from reg: d3
	writing to reg:   a2
	groups_count: 0
		operands[0].type: REG = d3
		operands[1].type: MEM
		address mode: Register Indirect - Address with Postincrement

0x1030:	nop	
	groups_count: 0

0x1032:	andi.l	#$c0dec0de, (a4, d5.l * 4)
	op_count: 2
	reading from reg: d5
	reading from reg: a4
	groups_count: 0
		operands[0].type: IMM = 0xc0dec0de
		operands[1].type: MEM
			operands[1].mem.base: REG = a4
			operands[1].mem.index: REG = d5
			operands[1].mem.index: size = l
			operands[1].mem.scale: 4
		address mode: Address Register Indirect With Index - Base displacement

0x103a:	move.b	d0, ([a6, d7.w], $123)
	op_count: 2
	reading from reg: d0
	reading from reg: d7
	reading from reg: a6
	groups_count: 0
		operands[0].type: REG = d0
		operands[1].type: MEM
			operands[1].mem.base: REG = a6
			operands[1].mem.index: REG = d7
			operands[1].mem.index: size = w
		address mode: Memory indirect - Preindex

0x1040:	fadd.s	#3.141500, fp0
	op_count: 2
	writing to reg:   fp0
	groups_count: 0
		operands[0].type: FP_SINGLE
			operands[0].simm: 3.141500
		operands[1].type: REG = fp0

0x1048:	scc.b	d5
	op_count: 1
	writing to reg:   d5
	groups_count: 0
		operands[0].type: REG = d5

0x104a:	fmove.s	#1000.000000, fp0
	op_count: 2
	writing to reg:   fp0
	groups_count: 0
		operands[0].type: FP_SINGLE
			operands[0].simm: 1000.000000
		operands[1].type: REG = fp0

0x1052:	fsub	fp2, fp4
	op_count: 2
	reading from reg: fp2
	writing to reg:   fp4
	groups_count: 0
		operands[0].type: REG = fp2
		operands[1].type: REG = fp4

0x1056:	jsr	$12.l
	op_count: 1
	groups_count: 1
		operands[0].type: MEM
		address mode: Absolute Data Addressing  - Long

0x105c:	rts	
	groups_count: 1

0x105e:

<end of output>
Test time =   0.04 sec
----------------------------------------------------------
Test Passed.
"capstone_test_m68k" end time: Feb 18 14:55 CET
"capstone_test_m68k" time elapsed: 00:00:00
----------------------------------------------------------

15/24 Testing: capstone_test_tms320c64x
15/24 Test: capstone_test_tms320c64x
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_tms320c64x"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_tms320c64x" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: TMS320C64x
Code:0x01 0xac 0x88 0x40 0x81 0xac 0x88 0x43 0x00 0x00 0x00 0x00 0x02 0x90 0x32 0x96 0x02 0x80 0x46 0x9e 0x05 0x3c 0x83 0xe6 0x0b 0x0c 0x8b 0x24 
Disasm:
0x1000:	add.D1	a11, a4, a3
	op_count: 3
		operands[0].type: REG = a11
		operands[1].type: REG = a4
		operands[2].type: REG = a3
	Functional unit: D1
	Parallel: false

0x1004:	[ a1] add.D2	b11, b4, b3	||
	op_count: 3
		operands[0].type: REG = b11
		operands[1].type: REG = b4
		operands[2].type: REG = b3
	Functional unit: D2
	Condition: [ a1]
	Parallel: true

0x1008:	NOP	
	Functional unit: No Functional Unit
	Parallel: false

0x100c:	ldbu.D1T2	*++a4[1], b5
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = a4
			operands[0].mem.disptype: Constant
			operands[0].mem.disp: 1
			operands[0].mem.unit: 2
			operands[0].mem.direction: Forward
			operands[0].mem.modify: Pre
			operands[0].mem.scaled: 1
		operands[1].type: REG = b5
	Functional unit: D2
	Parallel: false

0x1010:	ldbu.D2T2	*+b15[0x46], b5
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = b15
			operands[0].mem.disptype: Constant
			operands[0].mem.disp: 70
			operands[0].mem.unit: 2
			operands[0].mem.direction: Forward
			operands[0].mem.modify: No
			operands[0].mem.scaled: 0
		operands[1].type: REG = b5
	Functional unit: D2
	Parallel: false

0x1014:	lddw.D1T2	*+a15[4], b11:b10
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = a15
			operands[0].mem.disptype: Constant
			operands[0].mem.disp: 4
			operands[0].mem.unit: 2
			operands[0].mem.direction: Forward
			operands[0].mem.modify: No
			operands[0].mem.scaled: 1
		operands[1].type: REGPAIR = b11:b10
	Functional unit: D2
	Parallel: false

0x1018:	ldndw.D1T1	*+a3(a4), a23:a22
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = a3
			operands[0].mem.disptype: Register
			operands[0].mem.disp: a4
			operands[0].mem.unit: 1
			operands[0].mem.direction: Forward
			operands[0].mem.modify: No
			operands[0].mem.scaled: 0
		operands[1].type: REGPAIR = a23:a22
	Functional unit: D1
	Parallel: false

0x101c:

<end of output>
Test time =   0.03 sec
----------------------------------------------------------
Test Passed.
"capstone_test_tms320c64x" end time: Feb 18 14:55 CET
"capstone_test_tms320c64x" time elapsed: 00:00:00
----------------------------------------------------------

16/24 Testing: capstone_test_m680x
16/24 Test: capstone_test_m680x
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_m680x"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_m680x" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
********************
Platform: M680X_HD6301
Code: 0x6b 0x10 0x00 0x71 0x10 0x00 0x72 0x10 0x10 0x39 
Disasm:
0x1000: 6b1000     tim   #16; 0, x
	op_count: 2
		operands[0].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 0
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc

0x1003: 711000     aim   #16, $00
	op_count: 2
		operands[0].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[1].type: DIRECT = 0x00
			size: 1
			access: READ | WRITE
	Registers read: cc
	Registers modified: cc

0x1006: 721010     oim   #16, $10
	op_count: 2
		operands[0].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[1].type: DIRECT = 0x10
			size: 1
			access: READ | WRITE
	Registers read: cc
	Registers modified: cc

0x1009: 39         rts   
	Registers read: s
	Registers modified: s pc
	groups_count: 1

********************
Platform: M680X_HD6309
Code: 0x01 0x10 0x10 0x62 0x10 0x10 0x7b 0x10 0x10 0x00 0xcd 0x49 0x96 0x02 0xd2 0x10 0x30 0x23 0x10 0x38 0x10 0x3b 0x10 0x53 0x10 0x5d 0x11 0x30 0x43 0x10 0x11 0x37 0x25 0x10 0x11 0x38 0x12 0x11 0x39 0x23 0x11 0x3b 0x34 0x11 0x8e 0x10 0x00 0x11 0xaf 0x10 0x11 0xab 0x10 0x11 0xf6 0x80 0x00 
Disasm:
0x1000: 011010     oim   #16, $10
	op_count: 2
		operands[0].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[1].type: DIRECT = 0x10
			size: 1
			access: READ | WRITE
	Registers read: cc
	Registers modified: cc

0x1003: 621010     aim   #16; -16, x
	op_count: 2
		operands[0].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: -16
			offset bits: 5
			size: 1
			access: READ | WRITE
	Registers read: cc x
	Registers modified: cc

0x1006: 7b101000   tim   #16, $1000
	op_count: 2
		operands[0].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[1].type: EXTENDED  = 0x1000
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc

0x100a: cd499602d2 ldq   #1234567890
	op_count: 2
		operands[0].type: REGISTER = q (in mnemonic)
			size: 4
			access: WRITE
		operands[1].type: IMMEDIATE = #1234567890
			size: 4
			access: READ
	Registers read: cc
	Registers modified: cc q

0x100f: 103023     addr  y, u
	op_count: 2
		operands[0].type: REGISTER = y
			size: 2
			access: READ
		operands[1].type: REGISTER = u
			size: 2
			access: READ | WRITE
	Registers read: cc y u
	Registers modified: cc u

0x1012: 1038       pshsw 
	op_count: 2
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = w (in mnemonic)
			size: 2
			access: READ
	Registers read: s w
	Registers modified: s

0x1014: 103b       puluw 
	op_count: 2
		operands[0].type: REGISTER = u (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = w (in mnemonic)
			size: 2
			access: WRITE
	Registers read: u
	Registers modified: u w

0x1016: 1053       comw  
	op_count: 1
		operands[0].type: REGISTER = w (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: cc w
	Registers modified: cc w

0x1018: 105d       tstw  
	op_count: 1
		operands[0].type: REGISTER = w (in mnemonic)
			size: 2
			access: READ
	Registers read: cc w
	Registers modified: cc

0x101a: 11304310   band  a, 0, 3, $10
	op_count: 4
		operands[0].type: REGISTER = a
			size: 1
			access: READ | WRITE
		operands[1].type: CONSTANT = 0
			access: READ
		operands[2].type: CONSTANT = 3
			access: READ
		operands[3].type: DIRECT = 0x10
			size: 1
			access: READ
	Registers read: a
	Registers modified: a

0x101e: 11372510   stbt  cc, 4, 5, $10
	op_count: 4
		operands[0].type: REGISTER = cc
			size: 1
			access: READ
		operands[1].type: CONSTANT = 4
			access: READ
		operands[2].type: CONSTANT = 5
			access: READ
		operands[3].type: DIRECT = 0x10
			size: 1
			access: READ | WRITE
	Registers read: cc

0x1022: 113812     tfm   x+, y+
	op_count: 2
		operands[0].type: INDEXED
			base register: x
			post increment: 1
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: y
			post increment: 1
			size: 1
			access: WRITE
	Registers read: w x y
	Registers modified: w x y

0x1025: 113923     tfm   y-, u-
	op_count: 2
		operands[0].type: INDEXED
			base register: y
			post decrement: 1
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: u
			post decrement: 1
			size: 1
			access: WRITE
	Registers read: w y u
	Registers modified: w y u

0x1028: 113b34     tfm   u, s+
	op_count: 2
		operands[0].type: INDEXED
			base register: u
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: s
			post increment: 1
			size: 1
			access: WRITE
	Registers read: w u s
	Registers modified: w s

0x102b: 118e1000   divq  #4096
	op_count: 2
		operands[0].type: REGISTER = q (in mnemonic)
			size: 4
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #4096
			size: 2
			access: READ
	Registers read: cc q
	Registers modified: cc q

0x102f: 11af10     muld  -16, x
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: INDEXED
			base register: x
			offset: -16
			offset bits: 5
			size: 2
			access: READ
	Registers read: cc d x
	Registers modified: cc d w

0x1032: 11ab10     adde  -16, x
	op_count: 2
		operands[0].type: REGISTER = e (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: INDEXED
			base register: x
			offset: -16
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc e x
	Registers modified: cc e

0x1035: 11f68000   ldf   $8000
	op_count: 2
		operands[0].type: REGISTER = f (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: EXTENDED  = 0x8000
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc f

********************
Platform: M680X_M6800
Code: 0x01 0x09 0x36 0x64 0x7f 0x74 0x10 0x00 0x90 0x10 0xa4 0x10 0xb6 0x10 0x00 0x39 
Disasm:
0x1000: 01         nop   

0x1001: 09         dex   
	op_count: 1
		operands[0].type: REGISTER = x (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: cc x
	Registers modified: cc x

0x1002: 36         psha  
	op_count: 1
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
	Registers read: a s
	Registers modified: s

0x1003: 647f       lsr   127, x
	op_count: 1
		operands[0].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 1
			access: READ | WRITE
	Registers read: cc x
	Registers modified: cc

0x1005: 741000     lsr   $1000
	op_count: 1
		operands[0].type: EXTENDED  = 0x1000
			size: 1
			access: READ | WRITE
	Registers read: cc
	Registers modified: cc

0x1008: 9010       suba  $10
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: DIRECT = 0x10
			size: 1
			access: READ
	Registers read: cc a
	Registers modified: cc a

0x100a: a410       anda  16, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 16
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc a x
	Registers modified: cc a

0x100c: b61000     ldaa  $1000
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: EXTENDED  = 0x1000
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc a

0x100f: 39         rts   
	Registers read: s
	Registers modified: s pc
	groups_count: 1

********************
Platform: M680X_M6801
Code: 0x04 0x05 0x3c 0x3d 0x38 0x93 0x10 0xec 0x10 0xed 0x10 0x39 
Disasm:
0x1000: 04         lsrd  
	op_count: 1
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: cc d
	Registers modified: cc d

0x1001: 05         asld  
	op_count: 1
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: cc d
	Registers modified: cc d

0x1002: 3c         pshx  
	op_count: 1
		operands[0].type: REGISTER = x (in mnemonic)
			size: 2
			access: READ
	Registers read: x s
	Registers modified: s

0x1003: 3d         mul   
	Registers read: cc a b
	Registers modified: cc a b

0x1004: 38         pulx  
	op_count: 1
		operands[0].type: REGISTER = x (in mnemonic)
			size: 2
			access: WRITE
	Registers read: s
	Registers modified: x s

0x1005: 9310       subd  $10
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: DIRECT = 0x10
			size: 2
			access: READ
	Registers read: cc d
	Registers modified: cc d

0x1007: ec10       ldd   16, x
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 16
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc x
	Registers modified: cc d

0x1009: ed10       std   16, x
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 16
			offset bits: 8
			size: 2
			access: WRITE
	Registers read: cc d x
	Registers modified: cc

0x100b: 39         rts   
	Registers read: s
	Registers modified: s pc
	groups_count: 1

********************
Platform: M680X_M68HC05
Code: 0x04 0x7f 0x00 0x17 0x22 0x28 0x00 0x2e 0x00 0x40 0x42 0x5a 0x70 0x8e 0x97 0x9c 0xa0 0x15 0xad 0x00 0xc3 0x10 0x00 0xda 0x12 0x34 0xe5 0x7f 0xfe 
Disasm:
0x1000: 047f00     brset 2, $7f, $1003
	op_count: 3
		operands[0].type: CONSTANT = 2
			access: READ
		operands[1].type: DIRECT = 0x7f
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x1003
	Registers read: cc
	Registers modified: cc
	groups_count: 2

0x1003: 1722       bset  3, $22
	op_count: 2
		operands[0].type: CONSTANT = 3
			access: READ
		operands[1].type: DIRECT = 0x22
			size: 1
			access: READ | WRITE

0x1005: 2800       bhcc  $1007
	op_count: 1
		operands[0].type: RELATIVE = 0x1007
	Registers read: cc
	groups_count: 2

0x1007: 2e00       bil   $1009
	op_count: 1
		operands[0].type: RELATIVE = 0x1009
	Registers read: cc
	groups_count: 2

0x1009: 40         nega  
	op_count: 1
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
	Registers read: cc a
	Registers modified: cc a

0x100a: 42         mul   
	Registers read: cc a x
	Registers modified: cc a x

0x100b: 5a         decx  
	op_count: 1
		operands[0].type: REGISTER = x (in mnemonic)
			size: 1
			access: READ | WRITE
	Registers read: cc x
	Registers modified: cc x

0x100c: 70         neg   , x
	op_count: 1
		operands[0].type: INDEXED
			base register: x
			size: 1
			access: READ | WRITE
	Registers read: cc x
	Registers modified: cc

0x100d: 8e         stop  

0x100e: 97         tax   
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
		operands[1].type: REGISTER = x (in mnemonic)
			size: 1
			access: WRITE
	Registers read: a
	Registers modified: x

0x100f: 9c         rsp   
	op_count: 1
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: WRITE
	Registers modified: s

0x1010: a015       sub   #21
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #21
			size: 1
			access: READ
	Registers read: cc a
	Registers modified: cc a

0x1012: ad00       bsr   $1014
	op_count: 1
		operands[0].type: RELATIVE = 0x1014
	Registers read: s
	Registers modified: s
	groups_count: 2

0x1014: c31000     cpx   $1000
	op_count: 2
		operands[0].type: REGISTER = x (in mnemonic)
			size: 1
			access: READ
		operands[1].type: EXTENDED  = 0x1000
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc

0x1017: da1234     ora   4660, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 4660
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc a x
	Registers modified: cc a

0x101a: e57f       bit   127, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc a x
	Registers modified: cc

0x101c: fe         ldx   , x
	op_count: 2
		operands[0].type: REGISTER = x (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc x

********************
Platform: M680X_M68HC08
Code: 0x31 0x22 0x00 0x35 0x22 0x45 0x10 0x00 0x4b 0x00 0x51 0x10 0x52 0x5e 0x22 0x62 0x65 0x12 0x34 0x72 0x84 0x85 0x86 0x87 0x8a 0x8b 0x8c 0x94 0x95 0xa7 0x10 0xaf 0x10 0x9e 0x60 0x7f 0x9e 0x6b 0x7f 0x00 0x9e 0xd6 0x10 0x00 0x9e 0xe6 0x7f 
Disasm:
0x1000: 312200     cbeq  $22, $1003
	op_count: 3
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
		operands[1].type: DIRECT = 0x22
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x1003
	Registers read: cc a
	groups_count: 2

0x1003: 3522       sthx  $22
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: DIRECT = 0x22
			size: 2
			access: WRITE
	Registers read: cc hx
	Registers modified: cc

0x1005: 451000     ldhx  #4096
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: IMMEDIATE = #4096
			size: 2
			access: READ
	Registers read: cc
	Registers modified: cc hx

0x1008: 4b00       dbnza $100a
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: RELATIVE = 0x100a
	Registers read: cc a
	Registers modified: a
	groups_count: 2

0x100a: 511052     cbeqx #16, $105f
	op_count: 3
		operands[0].type: REGISTER = x (in mnemonic)
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x105f
	Registers read: cc x
	groups_count: 2

0x100d: 5e22       mov   $22; x+
	op_count: 2
		operands[0].type: DIRECT = 0x22
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: x
			post increment: 1
			size: 1
			access: WRITE
	Registers read: cc x h
	Registers modified: cc x h

0x100f: 62         nsa   
	op_count: 1
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
	Registers read: cc a
	Registers modified: cc a

0x1010: 651234     cphx  #4660
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: IMMEDIATE = #4660
			size: 2
			access: READ
	Registers read: cc hx
	Registers modified: cc

0x1013: 72         daa   
	Registers read: cc a
	Registers modified: cc a

0x1014: 84         tap   
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
		operands[1].type: REGISTER = cc (in mnemonic)
			size: 1
			access: WRITE
	Registers read: a
	Registers modified: cc

0x1015: 85         tpa   
	op_count: 2
		operands[0].type: REGISTER = cc (in mnemonic)
			size: 1
			access: READ
		operands[1].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
	Registers read: cc
	Registers modified: a

0x1016: 86         pula  
	op_count: 1
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
	Registers read: s
	Registers modified: a s

0x1017: 87         psha  
	op_count: 1
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
	Registers read: a s
	Registers modified: s

0x1018: 8a         pulh  
	op_count: 1
		operands[0].type: REGISTER = h (in mnemonic)
			size: 1
			access: WRITE
	Registers read: s
	Registers modified: h s

0x1019: 8b         pshh  
	op_count: 1
		operands[0].type: REGISTER = h (in mnemonic)
			size: 1
			access: READ
	Registers read: h s
	Registers modified: s

0x101a: 8c         clrh  
	op_count: 1
		operands[0].type: REGISTER = h (in mnemonic)
			size: 1
			access: WRITE
	Registers read: cc
	Registers modified: cc h

0x101b: 94         txs   
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: REGISTER = s (in mnemonic)
			size: 2
			access: WRITE
	Registers read: hx
	Registers modified: s

0x101c: 95         tsx   
	op_count: 2
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ
		operands[1].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
	Registers read: s
	Registers modified: hx

0x101d: a710       ais   #16
	op_count: 2
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #16
			size: 1
			access: READ
	Registers read: s
	Registers modified: s

0x101f: af10       aix   #16
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #16
			size: 1
			access: READ
	Registers read: hx
	Registers modified: hx

0x1021: 9e607f     neg   127, s
	op_count: 1
		operands[0].type: INDEXED
			base register: s
			offset: 127
			offset bits: 8
			size: 1
			access: READ | WRITE
	Registers read: cc s
	Registers modified: cc

0x1024: 9e6b7f00   dbnz  127, s; $1028
	op_count: 2
		operands[0].type: INDEXED
			base register: s
			offset: 127
			offset bits: 8
			size: 1
			access: READ | WRITE
		operands[1].type: RELATIVE = 0x1028
	Registers read: cc s
	groups_count: 2

0x1028: 9ed61000   lda   4096, s
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: s
			offset: 4096
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc s
	Registers modified: cc a

0x102c: 9ee67f     lda   127, s
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: s
			offset: 127
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc s
	Registers modified: cc a

********************
Platform: M680X_M6809
Code: 0x06 0x10 0x19 0x1a 0x55 0x1e 0x01 0x23 0xe9 0x31 0x06 0x34 0x55 0xa6 0x81 0xa7 0x89 0x7f 0xff 0xa6 0x9d 0x10 0x00 0xa7 0x91 0xa6 0x9f 0x10 0x00 0x11 0xac 0x99 0x10 0x00 0x39 0xa6 0x07 0xa6 0x27 0xa6 0x47 0xa6 0x67 0xa6 0x0f 0xa6 0x10 0xa6 0x80 0xa6 0x81 0xa6 0x82 0xa6 0x83 0xa6 0x84 0xa6 0x85 0xa6 0x86 0xa6 0x88 0x7f 0xa6 0x88 0x80 0xa6 0x89 0x7f 0xff 0xa6 0x89 0x80 0x00 0xa6 0x8b 0xa6 0x8c 0x10 0xa6 0x8d 0x10 0x00 0xa6 0x91 0xa6 0x93 0xa6 0x94 0xa6 0x95 0xa6 0x96 0xa6 0x98 0x7f 0xa6 0x98 0x80 0xa6 0x99 0x7f 0xff 0xa6 0x99 0x80 0x00 0xa6 0x9b 0xa6 0x9c 0x10 0xa6 0x9d 0x10 0x00 0xa6 0x9f 0x10 0x00 
Disasm:
0x1000: 0610       ror   $10
	op_count: 1
		operands[0].type: DIRECT = 0x10
			size: 1
			access: READ | WRITE
	Registers read: cc
	Registers modified: cc

0x1002: 19         daa   
	Registers read: cc a
	Registers modified: cc a

0x1003: 1a55       orcc  #85
	op_count: 2
		operands[0].type: REGISTER = cc (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #85
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc

0x1005: 1e01       exg   d, x
	op_count: 2
		operands[0].type: REGISTER = d
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = x
			size: 2
			access: READ | WRITE
	Registers read: d x
	Registers modified: d x

0x1007: 23e9       bls   $0ff2
	op_count: 1
		operands[0].type: RELATIVE = 0x0ff2
	Registers read: cc
	groups_count: 2

0x1009: 3106       leay  6, x
	op_count: 2
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 6
			offset bits: 5
			size: 2
			access: READ
	Registers read: cc x
	Registers modified: cc y

0x100b: 3455       pshs  cc, b, x, u
	op_count: 5
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = cc
			size: 1
			access: READ
		operands[2].type: REGISTER = b
			size: 1
			access: READ
		operands[3].type: REGISTER = x
			size: 2
			access: READ
		operands[4].type: REGISTER = u
			size: 2
			access: READ
	Registers read: s cc b x u
	Registers modified: s

0x100d: a681       lda   , x++
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			post increment: 2
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x100f: a7897fff   sta   32767, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 32767
			offset bits: 16
			size: 1
			access: WRITE
	Registers read: cc a x
	Registers modified: cc

0x1013: a69d1000   lda   [$2017, pcr]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: pc
			offset: 4096
			offset address: 0x2017
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc pc
	Registers modified: cc a

0x1017: a791       sta   [, x++]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ
		operands[1].type: INDEXED INDIRECT
			base register: x
			post increment: 2
			size: 1
			access: WRITE
	Registers read: cc a x
	Registers modified: cc x

0x1019: a69f1000   lda   [$1000]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: EXTENDED INDIRECT = 0x1000
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc a

0x101d: 11ac991000 cmps  [4096, x]
	op_count: 2
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset: 4096
			offset bits: 16
			size: 2
			access: READ
	Registers read: cc s x
	Registers modified: cc

0x1022: 39         rts   
	Registers read: s
	Registers modified: s pc
	groups_count: 1

0x1023: a607       lda   7, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 7
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1025: a627       lda   7, y
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: y
			offset: 7
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc y
	Registers modified: cc a

0x1027: a647       lda   7, u
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: u
			offset: 7
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc u
	Registers modified: cc a

0x1029: a667       lda   7, s
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: s
			offset: 7
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc s
	Registers modified: cc a

0x102b: a60f       lda   15, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 15
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x102d: a610       lda   -16, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: -16
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x102f: a680       lda   , x+
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			post increment: 1
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x1031: a681       lda   , x++
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			post increment: 2
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x1033: a682       lda   , -x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			pre decrement: 1
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x1035: a683       lda   , --x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			pre decrement: 2
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x1037: a684       lda   , x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1039: a685       lda   b, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset register: b
			size: 1
			access: READ
	Registers read: cc x b
	Registers modified: cc a

0x103b: a686       lda   a, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset register: a
			size: 1
			access: READ
	Registers read: cc x a
	Registers modified: cc a

0x103d: a6887f     lda   127, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1040: a68880     lda   -128, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: -128
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1043: a6897fff   lda   32767, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 32767
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1047: a6898000   lda   -32768, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: -32768
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x104b: a68b       lda   d, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset register: d
			size: 1
			access: READ
	Registers read: cc x d
	Registers modified: cc a

0x104d: a68c10     lda   $1050, pcr
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: pc
			offset: 16
			offset address: 0x1050
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc pc
	Registers modified: cc a

0x1050: a68d1000   lda   $2054, pcr
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: pc
			offset: 4096
			offset address: 0x2054
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc pc
	Registers modified: cc a

0x1054: a691       lda   [, x++]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			post increment: 2
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x1056: a693       lda   [, --x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			pre decrement: 2
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a x

0x1058: a694       lda   [, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x105a: a695       lda   [b, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset register: b
			size: 1
			access: READ
	Registers read: cc x b
	Registers modified: cc a

0x105c: a696       lda   [a, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset register: a
			size: 1
			access: READ
	Registers read: cc x a
	Registers modified: cc a

0x105e: a6987f     lda   [127, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset: 127
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1061: a69880     lda   [-128, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset: -128
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1064: a6997fff   lda   [32767, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset: 32767
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x1068: a6998000   lda   [-32768, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset: -32768
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc a

0x106c: a69b       lda   [d, x]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: x
			offset register: d
			size: 1
			access: READ
	Registers read: cc x d
	Registers modified: cc a

0x106e: a69c10     lda   [$1071, pcr]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: pc
			offset: 16
			offset address: 0x1071
			offset bits: 8
			size: 1
			access: READ
	Registers read: cc pc
	Registers modified: cc a

0x1071: a69d1000   lda   [$2075, pcr]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: pc
			offset: 4096
			offset address: 0x2075
			offset bits: 16
			size: 1
			access: READ
	Registers read: cc pc
	Registers modified: cc a

0x1075: a69f1000   lda   [$1000]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: EXTENDED INDIRECT = 0x1000
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc a

********************
Platform: M680X_M68HC11
Code: 0x02 0x03 0x12 0x7f 0x10 0x00 0x13 0x99 0x08 0x00 0x14 0x7f 0x02 0x15 0x7f 0x01 0x1e 0x7f 0x20 0x00 0x8f 0xcf 0x18 0x08 0x18 0x30 0x18 0x3c 0x18 0x67 0x18 0x8c 0x10 0x00 0x18 0x8f 0x18 0xce 0x10 0x00 0x18 0xff 0x10 0x00 0x1a 0xa3 0x7f 0x1a 0xac 0x1a 0xee 0x7f 0x1a 0xef 0x7f 0xcd 0xac 0x7f 
Disasm:
0x1000: 02         idiv  
	Registers read: cc d x
	Registers modified: cc d x

0x1001: 03         fdiv  
	Registers read: cc d x
	Registers modified: cc d x

0x1002: 127f1000   brset $7f, #16, $1006
	op_count: 3
		operands[0].type: DIRECT = 0x7f
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #16
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x1006
	Registers read: cc
	groups_count: 2

0x1006: 13990800   brclr $99, #8, $100a
	op_count: 3
		operands[0].type: DIRECT = 0x99
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #8
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x100a
	Registers read: cc
	groups_count: 2

0x100a: 147f02     bset  $7f, #2
	op_count: 2
		operands[0].type: DIRECT = 0x7f
			size: 1
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #2
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc

0x100d: 157f01     bclr  $7f, #1
	op_count: 2
		operands[0].type: DIRECT = 0x7f
			size: 1
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #1
			size: 1
			access: READ
	Registers read: cc
	Registers modified: cc

0x1010: 1e7f2000   brset 127, x; #32; $1014
	op_count: 3
		operands[0].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #32
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x1014
	Registers read: cc x
	groups_count: 2

0x1014: 8f         xgdx  
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = x (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: d x
	Registers modified: d x

0x1015: cf         stop  

0x1016: 1808       iny   
	op_count: 1
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: cc y
	Registers modified: cc y

0x1018: 1830       tsy   
	op_count: 2
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ
		operands[1].type: REGISTER = y (in mnemonic)
			size: 2
			access: WRITE
	Registers read: s
	Registers modified: y

0x101a: 183c       pshy  
	op_count: 1
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: READ
	Registers read: y s
	Registers modified: s

0x101c: 186718     asr   24, y
	op_count: 1
		operands[0].type: INDEXED
			base register: y
			offset: 24
			offset bits: 8
			size: 1
			access: READ | WRITE
	Registers read: cc y
	Registers modified: cc

0x101f: 8c1000     cpx   #4096
	op_count: 2
		operands[0].type: REGISTER = x (in mnemonic)
			size: 2
			access: READ
		operands[1].type: IMMEDIATE = #4096
			size: 2
			access: READ
	Registers read: cc x
	Registers modified: cc

0x1022: 188f       xgdy  
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = y (in mnemonic)
			size: 2
			access: READ | WRITE
	Registers read: d y
	Registers modified: d y

0x1024: 18ce1000   ldy   #4096
	op_count: 2
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: IMMEDIATE = #4096
			size: 2
			access: READ
	Registers read: cc
	Registers modified: cc y

0x1028: 18ff1000   sty   $1000
	op_count: 2
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: READ
		operands[1].type: EXTENDED  = 0x1000
			size: 2
			access: WRITE
	Registers read: cc y
	Registers modified: cc

0x102c: 1aa37f     cpd   127, x
	op_count: 2
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc d x
	Registers modified: cc

0x102f: 1aac1a     cpy   26, x
	op_count: 2
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 26
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc y x
	Registers modified: cc

0x1032: ee7f       ldx   127, x
	op_count: 2
		operands[0].type: REGISTER = x (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc x
	Registers modified: cc x

0x1034: 1aef7f     sty   127, x
	op_count: 2
		operands[0].type: REGISTER = y (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 2
			access: WRITE
	Registers read: cc y x
	Registers modified: cc

0x1037: cdac7f     cpx   127, y
	op_count: 2
		operands[0].type: REGISTER = x (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: y
			offset: 127
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc x y
	Registers modified: cc

********************
Platform: M680X_CPU12
Code: 0x00 0x04 0x01 0x00 0x0c 0x00 0x80 0x0e 0x00 0x80 0x00 0x11 0x1e 0x10 0x00 0x80 0x00 0x3b 0x4a 0x10 0x00 0x04 0x4b 0x01 0x04 0x4f 0x7f 0x80 0x00 0x8f 0x10 0x00 0xb7 0x52 0xb7 0xb1 0xa6 0x67 0xa6 0xfe 0xa6 0xf7 0x18 0x02 0xe2 0x30 0x39 0xe2 0x10 0x00 0x18 0x0c 0x30 0x39 0x10 0x00 0x18 0x11 0x18 0x12 0x10 0x00 0x18 0x19 0x00 0x18 0x1e 0x00 0x18 0x3e 0x18 0x3f 0x00 
Disasm:
0x1000: 00         bgnd  

0x1001: 040100     dbeq  b, $1004
	op_count: 2
		operands[0].type: REGISTER = b
			size: 1
			access: READ | WRITE
		operands[1].type: RELATIVE = 0x1004
	Registers read: b
	Registers modified: b
	groups_count: 2

0x1004: 0c0080     bset  0, x; #-128
	op_count: 2
		operands[0].type: INDEXED
			base register: x
			offset: 0
			offset bits: 5
			size: 1
			access: READ | WRITE
		operands[1].type: IMMEDIATE = #-128
			size: 1
			access: READ
	Registers read: cc x
	Registers modified: cc

0x1007: 0e008000   brset 0, x; #-128; $100b
	op_count: 3
		operands[0].type: INDEXED
			base register: x
			offset: 0
			offset bits: 5
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #-128
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x100b
	Registers read: cc x
	groups_count: 2

0x100b: 11         ediv  
	Registers read: cc d y x
	Registers modified: cc d y

0x100c: 1e10008000 brset $1000, #-128, $1011
	op_count: 3
		operands[0].type: EXTENDED  = 0x1000
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #-128
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x1011
	Registers read: cc
	groups_count: 2

0x1011: 3b         pshd  
	op_count: 1
		operands[0].type: REGISTER = d (in mnemonic)
			size: 2
			access: READ
	Registers read: d s
	Registers modified: s

0x1012: 4a100004   call  $1000, 4
	op_count: 2
		operands[0].type: EXTENDED  = 0x1000
			size: 1
		operands[1].type: CONSTANT = 4
	Registers read: s
	Registers modified: s
	groups_count: 1

0x1016: 4b0104     call  1, x; 4
	op_count: 2
		operands[0].type: INDEXED
			base register: x
			offset: 1
			offset bits: 5
			size: 1
		operands[1].type: CONSTANT = 4
	Registers read: x s
	Registers modified: s
	groups_count: 1

0x1019: 4f7f8000   brclr $7f, #-128, $101d
	op_count: 3
		operands[0].type: DIRECT = 0x7f
			size: 1
			access: READ
		operands[1].type: IMMEDIATE = #-128
			size: 1
			access: READ
		operands[2].type: RELATIVE = 0x101d
	Registers read: cc
	groups_count: 2

0x101d: 8f1000     cps   #4096
	op_count: 2
		operands[0].type: REGISTER = s (in mnemonic)
			size: 2
			access: READ
		operands[1].type: IMMEDIATE = #4096
			size: 2
			access: READ
	Registers read: cc s
	Registers modified: cc

0x1020: b752       tfr   x, cc
	op_count: 2
		operands[0].type: REGISTER = x
			size: 2
			access: READ
		operands[1].type: REGISTER = cc
			size: 1
			access: WRITE
	Registers read: x
	Registers modified: cc

0x1022: b7b1       exg   tmp3, b
	op_count: 2
		operands[0].type: REGISTER = tmp3
			size: 2
			access: READ | WRITE
		operands[1].type: REGISTER = b
			size: 1
			access: READ | WRITE
	Registers read: tmp3 b
	Registers modified: tmp3 b

0x1024: a667       ldaa  8, +y
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: y
			pre increment: 8
			size: 1
			access: READ
	Registers read: cc y
	Registers modified: cc a y

0x1026: a6fe       ldaa  d, pc
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED
			base register: pc
			offset register: d
			size: 1
			access: READ
	Registers read: cc pc d
	Registers modified: cc a

0x1028: a6f7       ldaa  [d, s]
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: WRITE
		operands[1].type: INDEXED INDIRECT
			base register: s
			offset register: d
			size: 1
			access: READ
	Registers read: cc s d
	Registers modified: cc a

0x102a: 1802e23039e21000         movw  12345, x; 4096, x
	op_count: 2
		operands[0].type: INDEXED
			base register: x
			offset: 12345
			offset bits: 16
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: x
			offset: 4096
			offset bits: 16
			size: 2
			access: WRITE
	Registers read: x

0x1032: 180c30391000         movb  $3039, $1000
	op_count: 2
		operands[0].type: EXTENDED  = 0x3039
			size: 1
			access: READ
		operands[1].type: EXTENDED  = 0x1000
			size: 1
			access: WRITE

0x1038: 1811       fdiv  
	Registers read: cc d x
	Registers modified: cc d x

0x103a: 18121000   emacs $1000
	op_count: 1
		operands[0].type: EXTENDED  = 0x1000
			size: 4
			access: READ | WRITE
	Registers read: cc x y
	Registers modified: cc x

0x103e: 181900     mina  0, x
	op_count: 2
		operands[0].type: REGISTER = a (in mnemonic)
			size: 1
			access: READ | WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 0
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc a x
	Registers modified: cc a

0x1041: 181e00     emaxm 0, x
	op_count: 1
		operands[0].type: INDEXED
			base register: x
			offset: 0
			offset bits: 5
			size: 1
			access: READ | WRITE
	Registers read: cc x d
	Registers modified: cc

0x1044: 183e       stop  

0x1046: 183f00     etbl  0, x
	op_count: 1
		operands[0].type: INDEXED
			base register: x
			offset: 0
			offset bits: 5
			size: 1
			access: READ
	Registers read: cc x b
	Registers modified: cc a b

********************
Platform: M680X_HCS08
Code: 0x32 0x10 0x00 0x9e 0xae 0x9e 0xce 0x7f 0x9e 0xbe 0x10 0x00 0x9e 0xfe 0x7f 0x3e 0x10 0x00 0x9e 0xf3 0x7f 0x96 0x10 0x00 0x9e 0xff 0x7f 0x82 
Disasm:
0x1000: 321000     ldhx  $1000
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: EXTENDED  = 0x1000
			size: 2
			access: READ
	Registers read: cc
	Registers modified: cc hx

0x1003: 9eae       ldhx  , x
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			size: 2
			access: READ
	Registers read: cc x h
	Registers modified: cc hx

0x1005: 9ece7f     ldhx  127, x
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 127
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc x h
	Registers modified: cc hx

0x1008: 9ebe1000   ldhx  4096, x
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: x
			offset: 4096
			offset bits: 16
			size: 2
			access: READ
	Registers read: cc x h
	Registers modified: cc hx

0x100c: 9efe7f     ldhx  127, s
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: WRITE
		operands[1].type: INDEXED
			base register: s
			offset: 127
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc s
	Registers modified: cc hx

0x100f: 3e1000     cphx  $1000
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: EXTENDED  = 0x1000
			size: 2
			access: READ
	Registers read: cc hx
	Registers modified: cc

0x1012: 9ef37f     cphx  127, s
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: s
			offset: 127
			offset bits: 8
			size: 2
			access: READ
	Registers read: cc hx s
	Registers modified: cc

0x1015: 961000     sthx  $1000
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: EXTENDED  = 0x1000
			size: 2
			access: WRITE
	Registers read: cc hx
	Registers modified: cc

0x1018: 9eff7f     sthx  127, s
	op_count: 2
		operands[0].type: REGISTER = hx (in mnemonic)
			size: 2
			access: READ
		operands[1].type: INDEXED
			base register: s
			offset: 127
			offset bits: 8
			size: 2
			access: WRITE
	Registers read: cc hx s
	Registers modified: cc

0x101b: 82         bgnd  

<end of output>
Test time =   0.03 sec
----------------------------------------------------------
Test Passed.
"capstone_test_m680x" end time: Feb 18 14:55 CET
"capstone_test_m680x" time elapsed: 00:00:00
----------------------------------------------------------

17/24 Testing: capstone_test_evm
17/24 Test: capstone_test_evm
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_evm"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_evm" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: EVM
Code:0x60 0x61 0x50 
Disasm:
0x80001000:	push1	61
	Push:    1
	Gas fee: 3
	Groups: stack_write 
0x80001002:	pop	
	Pop:     1
	Gas fee: 2
	Groups: stack_read 
0x80001003:

<end of output>
Test time =   0.03 sec
----------------------------------------------------------
Test Passed.
"capstone_test_evm" end time: Feb 18 14:55 CET
"capstone_test_evm" time elapsed: 00:00:00
----------------------------------------------------------

18/24 Testing: capstone_test_wasm
18/24 Test: capstone_test_wasm
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_wasm"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_wasm" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: WASM
Code: 0x20 0x00 0x20 0x01 0x41 0x20 0x10 0xc9 0x01 0x45 0x0b 
Disasm:
0xffff:	get_local	0x0
	Groups: variable 
	Operand count: 1
		Operand[0] type: varuint32
		Operand[0] value: 0x0
		Operand[0] size: 1
0x10001:	get_local	0x1
	Groups: variable 
	Operand count: 1
		Operand[0] type: varuint32
		Operand[0] value: 0x1
		Operand[0] size: 1
0x10003:	i32.const	0x20
	Groups: numberic 
	Operand count: 1
		Operand[0] type: varuint32
		Operand[0] value: 0x20
		Operand[0] size: 1
0x10005:	call	0xc9
	Groups: control 
	Operand count: 1
		Operand[0] type: varuint32
		Operand[0] value: 0xc9
		Operand[0] size: 2
0x10008:	i32.eqz	
	Groups: numberic 
0x10009:	end	
	Groups: control 
0x1000a:

<end of output>
Test time =   0.02 sec
----------------------------------------------------------
Test Passed.
"capstone_test_wasm" end time: Feb 18 14:55 CET
"capstone_test_wasm" time elapsed: 00:00:00
----------------------------------------------------------

19/24 Testing: capstone_test_mos65xx
19/24 Test: capstone_test_mos65xx
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_mos65xx"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_mos65xx" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
<end of output>
Test time =   0.02 sec
----------------------------------------------------------
Test Failed.
"capstone_test_mos65xx" end time: Feb 18 14:55 CET
"capstone_test_mos65xx" time elapsed: 00:00:00
----------------------------------------------------------

20/24 Testing: capstone_test_bpf
20/24 Test: capstone_test_bpf
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_bpf"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_bpf" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: cBPF Le
Code: 0x94 0x09 0x00 0x00 0x37 0x13 0x03 0x00 0x87 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x07 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x16 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Disasm:
0x0:	mod	0x31337
	Groups: alu
	Operand count: 1
		operands[0].type: IMM = 0x31337
	Registers read: a
	Registers modified: a

0x8:	txa	
	Groups: misc
	Operand count: 0
	Registers read: x
	Registers modified: a

0x10:	tax	
	Groups: misc
	Operand count: 0
	Registers read: a
	Registers modified: x

0x18:	ret	a
	Groups: return
	Operand count: 1
		operands[0].type: REG = a
	Registers read: a

0x20:	ld	#len
	Groups: load
	Operand count: 1
		operands[0].type: EXT = #len
	Registers modified: a

****************
Platform: eBPF Le
Code: 0x97 0x09 0x00 0x00 0x37 0x13 0x03 0x00 0xdc 0x02 0x00 0x00 0x20 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xdb 0x3a 0x00 0x01 0x00 0x00 0x00 0x00 0x84 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x6d 0x33 0x17 0x02 0x00 0x00 0x00 0x00
Disasm:
0x0:	mod64	r9, 0x31337
	Groups: alu
	Operand count: 2
		operands[0].type: REG = r9
		operands[1].type: IMM = 0x31337
	Registers read: r9
	Registers modified: r9

0x8:	be32	r2
	Groups: alu
	Operand count: 1
		operands[0].type: REG = r2
	Registers read: r2
	Registers modified: r2

0x10:	ldb	[0x0]
	Groups: load
	Operand count: 1
		operands[0].type: MEM
			operands[0].mem.disp: 0x0
	Registers modified: r0

0x18:	xadddw	[r10+0x100], r3
	Groups: store
	Operand count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = r10
			operands[0].mem.disp: 0x100
		operands[1].type: REG = r3
	Registers read: r3 r10

0x20:	neg	r2
	Groups: alu
	Operand count: 1
		operands[0].type: REG = r2
	Registers read: r2
	Registers modified: r2

0x28:	jsgt	r3, r3, +0x217
	Groups: jump
	Operand count: 3
		operands[0].type: REG = r3
		operands[1].type: REG = r3
		operands[2].type: OFF = +0x217
	Registers read: r3

<end of output>
Test time =   0.02 sec
----------------------------------------------------------
Test Passed.
"capstone_test_bpf" end time: Feb 18 14:55 CET
"capstone_test_bpf" time elapsed: 00:00:00
----------------------------------------------------------

21/24 Testing: capstone_test_riscv
21/24 Test: capstone_test_riscv
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_riscv"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_riscv" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: riscv32
Code:0x37 0x34 0x00 0x00 0x97 0x82 0x00 0x00 0xef 0x00 0x80 0x00 0xef 0xf0 0x1f 0xff 0xe7 0x00 0x45 0x00 0xe7 0x00 0xc0 0xff 0x63 0x05 0x41 0x00 0xe3 0x9d 0x61 0xfe 0x63 0xca 0x93 0x00 0x63 0x53 0xb5 0x00 0x63 0x65 0xd6 0x00 0x63 0x76 0xf7 0x00 0x03 0x88 0x18 0x00 0x03 0x99 0x49 0x00 0x03 0xaa 0x6a 0x00 0x03 0xcb 0x2b 0x01 0x03 0xdc 0x8c 0x01 0x23 0x86 0xad 0x03 0x23 0x9a 0xce 0x03 0x23 0x8f 0xef 0x01 0x93 0x00 0xe0 0x00 0x13 0xa1 0x01 0x01 0x13 0xb2 0x02 0x7d 0x13 0xc3 0x03 0xdd 0x13 0xe4 0xc4 0x12 0x13 0xf5 0x85 0x0c 0x13 0x96 0xe6 0x01 0x13 0xd7 0x97 0x01 0x13 0xd8 0xf8 0x40 0x33 0x89 0x49 0x01 0xb3 0x0a 0x7b 0x41 0x33 0xac 0xac 0x01 0xb3 0x3d 0xde 0x01 0x33 0xd2 0x62 0x40 0xb3 0x43 0x94 0x00 0x33 0xe5 0xc5 0x00 0xb3 0x76 0xf7 0x00 0xb3 0x54 0x39 0x01 0xb3 0x50 0x31 0x00 0x33 0x9f 0x0f 0x00 
Disasm:
0x1000:	lui	s0, 3
	op_count: 2
		operands[0].type: REG = s0
		operands[1].type: IMM = 0x3

0x1004:	auipc	t0, 8
	op_count: 2
		operands[0].type: REG = t0
		operands[1].type: IMM = 0x8

0x1008:	jal	8
	op_count: 1
		operands[0].type: IMM = 0x8
	This instruction belongs to groups: call 

0x100c:	jal	-0x10
	op_count: 1
		operands[0].type: IMM = 0xfffffffffffffff0
	This instruction belongs to groups: call 

0x1010:	jalr	ra, a0, 4
	op_count: 3
		operands[0].type: REG = ra
		operands[1].type: REG = a0
		operands[2].type: IMM = 0x4
	This instruction belongs to groups: call 

0x1014:	jalr	ra, zero, -4
	op_count: 3
		operands[0].type: REG = ra
		operands[1].type: REG = zero
		operands[2].type: IMM = 0xfffffffffffffffc
	This instruction belongs to groups: call 

0x1018:	beq	sp, tp, 0xa
	op_count: 3
		operands[0].type: REG = sp
		operands[1].type: REG = tp
		operands[2].type: IMM = 0xa
	This instruction belongs to groups: branch_relative jump 

0x101c:	bne	gp, t1, -6
	op_count: 3
		operands[0].type: REG = gp
		operands[1].type: REG = t1
		operands[2].type: IMM = 0xfffffffffffffffa
	This instruction belongs to groups: branch_relative jump 

0x1020:	blt	t2, s1, 0x14
	op_count: 3
		operands[0].type: REG = t2
		operands[1].type: REG = s1
		operands[2].type: IMM = 0x14
	This instruction belongs to groups: branch_relative jump 

0x1024:	bge	a0, a1, 6
	op_count: 3
		operands[0].type: REG = a0
		operands[1].type: REG = a1
		operands[2].type: IMM = 0x6
	This instruction belongs to groups: branch_relative jump 

0x1028:	bltu	a2, a3, 0xa
	op_count: 3
		operands[0].type: REG = a2
		operands[1].type: REG = a3
		operands[2].type: IMM = 0xa
	This instruction belongs to groups: branch_relative jump 

0x102c:	bgeu	a4, a5, 0xc
	op_count: 3
		operands[0].type: REG = a4
		operands[1].type: REG = a5
		operands[2].type: IMM = 0xc
	This instruction belongs to groups: branch_relative jump 

0x1030:	lb	a6, 1(a7)
	op_count: 2
		operands[0].type: REG = a6
		operands[1].type: MEM
			operands[1].mem.base: REG = a7
			operands[1].mem.disp: 0x1

0x1034:	lh	s2, 4(s3)
	op_count: 2
		operands[0].type: REG = s2
		operands[1].type: MEM
			operands[1].mem.base: REG = s3
			operands[1].mem.disp: 0x4

0x1038:	lw	s4, 6(s5)
	op_count: 2
		operands[0].type: REG = s4
		operands[1].type: MEM
			operands[1].mem.base: REG = s5
			operands[1].mem.disp: 0x6

0x103c:	lbu	s6, 0x12(s7)
	op_count: 2
		operands[0].type: REG = s6
		operands[1].type: MEM
			operands[1].mem.base: REG = s7
			operands[1].mem.disp: 0x12

0x1040:	lhu	s8, 0x18(s9)
	op_count: 2
		operands[0].type: REG = s8
		operands[1].type: MEM
			operands[1].mem.base: REG = s9
			operands[1].mem.disp: 0x18

0x1044:	sb	s10, 0x2c(s11)
	op_count: 2
		operands[0].type: REG = s10
		operands[1].type: MEM
			operands[1].mem.base: REG = s11
			operands[1].mem.disp: 0x2c

0x1048:	sh	t3, 0x34(t4)
	op_count: 2
		operands[0].type: REG = t3
		operands[1].type: MEM
			operands[1].mem.base: REG = t4
			operands[1].mem.disp: 0x34

0x104c:	sb	t5, 0x1e(t6)
	op_count: 2
		operands[0].type: REG = t5
		operands[1].type: MEM
			operands[1].mem.base: REG = t6
			operands[1].mem.disp: 0x1e

0x1050:	addi	ra, zero, 0xe
	op_count: 3
		operands[0].type: REG = ra
		operands[1].type: REG = zero
		operands[2].type: IMM = 0xe

0x1054:	slti	sp, gp, 0x10
	op_count: 3
		operands[0].type: REG = sp
		operands[1].type: REG = gp
		operands[2].type: IMM = 0x10

0x1058:	sltiu	tp, t0, 0x7d0
	op_count: 3
		operands[0].type: REG = tp
		operands[1].type: REG = t0
		operands[2].type: IMM = 0x7d0

0x105c:	xori	t1, t2, -0x230
	op_count: 3
		operands[0].type: REG = t1
		operands[1].type: REG = t2
		operands[2].type: IMM = 0xfffffffffffffdd0

0x1060:	ori	s0, s1, 0x12c
	op_count: 3
		operands[0].type: REG = s0
		operands[1].type: REG = s1
		operands[2].type: IMM = 0x12c

0x1064:	andi	a0, a1, 0xc8
	op_count: 3
		operands[0].type: REG = a0
		operands[1].type: REG = a1
		operands[2].type: IMM = 0xc8

0x1068:	slli	a2, a3, 0x1e
	op_count: 3
		operands[0].type: REG = a2
		operands[1].type: REG = a3
		operands[2].type: IMM = 0x1e

0x106c:	srli	a4, a5, 0x19
	op_count: 3
		operands[0].type: REG = a4
		operands[1].type: REG = a5
		operands[2].type: IMM = 0x19

0x1070:	srai	a6, a7, 0xf
	op_count: 3
		operands[0].type: REG = a6
		operands[1].type: REG = a7
		operands[2].type: IMM = 0xf

0x1074:	add	s2, s3, s4
	op_count: 3
		operands[0].type: REG = s2
		operands[1].type: REG = s3
		operands[2].type: REG = s4

0x1078:	sub	s5, s6, s7
	op_count: 3
		operands[0].type: REG = s5
		operands[1].type: REG = s6
		operands[2].type: REG = s7

0x107c:	slt	s8, s9, s10
	op_count: 3
		operands[0].type: REG = s8
		operands[1].type: REG = s9
		operands[2].type: REG = s10

0x1080:	sltu	s11, t3, t4
	op_count: 3
		operands[0].type: REG = s11
		operands[1].type: REG = t3
		operands[2].type: REG = t4

0x1084:	sra	tp, t0, t1
	op_count: 3
		operands[0].type: REG = tp
		operands[1].type: REG = t0
		operands[2].type: REG = t1

0x1088:	xor	t2, s0, s1
	op_count: 3
		operands[0].type: REG = t2
		operands[1].type: REG = s0
		operands[2].type: REG = s1

0x108c:	or	a0, a1, a2
	op_count: 3
		operands[0].type: REG = a0
		operands[1].type: REG = a1
		operands[2].type: REG = a2

0x1090:	and	a3, a4, a5
	op_count: 3
		operands[0].type: REG = a3
		operands[1].type: REG = a4
		operands[2].type: REG = a5

0x1094:	srl	s1, s2, s3
	op_count: 3
		operands[0].type: REG = s1
		operands[1].type: REG = s2
		operands[2].type: REG = s3

0x1098:	srl	ra, sp, gp
	op_count: 3
		operands[0].type: REG = ra
		operands[1].type: REG = sp
		operands[2].type: REG = gp

0x109c:	sll	t5, t6, zero
	op_count: 3
		operands[0].type: REG = t5
		operands[1].type: REG = t6
		operands[2].type: REG = zero

0x10a0:

****************
Platform: riscv64
Code:0x13 0x04 0xa8 0x7a 
Disasm:
0x1000:	addi	s0, a6, 0x7aa
	op_count: 3
		operands[0].type: REG = s0
		operands[1].type: REG = a6
		operands[2].type: IMM = 0x7aa

0x1004:

<end of output>
Test time =   0.02 sec
----------------------------------------------------------
Test Passed.
"capstone_test_riscv" end time: Feb 18 14:55 CET
"capstone_test_riscv" time elapsed: 00:00:00
----------------------------------------------------------

22/24 Testing: capstone_test_sh
22/24 Test: capstone_test_sh
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_sh"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_sh" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
********************
Platform: SH_SH4A
Code: 0x0c 0x31 0x10 0x20 0x22 0x21 0x36 0x64 0x46 0x25 0x12 0x12 0x1c 0x02 0x08 0xc1 0x05 0xc7 0x0c 0x71 0x1f 0x02 0x22 0xcf 0x06 0x89 0x23 0x00 0x2b 0x41 0x0b 0x00 0x0e 0x40 0x32 0x00 0x0a 0xf1 0x09 0x00 
Disasm:
0x80000000: 0c31       add   r0,r1
	Registers read: r0
	Registers modified: r1

0x80000002: 1020       mov.b r1,@r0
	Registers read: r0 r1

0x80000004: 2221       mov.l r2,@r1
	Registers read: r1 r2

0x80000006: 3664       mov.l @r3+,r4
	Registers modified: r3 r4

0x80000008: 4625       mov.l r4,@-r5
	Registers read: r4
	Registers modified: r5

0x8000000a: 1212       mov.l r1,@(8,r2)
	Registers read: r2 r1

0x8000000c: 1c02       mov.b @(r0,r1),r2
	Registers read: r0 r1
	Registers modified: r2

0x8000000e: 08c1       mov.w r0,@(16,gbr)
	Registers read: gbr r0

0x80000010: 05c7       mova  0x80000028,r0
	Registers modified: r0

0x80000012: 0c71       add   #12,r1
	Registers modified: r1

0x80000014: 1f02       mac.l @r1+,@r2+
	Registers modified: r1 r2

0x80000016: 22cf       or.b  #34,@(r0,gbr)
	Registers read: gbr r0

0x80000018: 0689       bt    0x80000028
	groups_count: 2

0x8000001a: 2300       braf  r0
	Registers read: r0
	groups_count: 2

0x8000001c: 2b41       jmp   @r1
	Registers read: r1
	groups_count: 1

0x8000001e: 0b00       rts   

0x80000020: 0e40       ldc   r0,sr
	Registers read: r0
	Registers modified: sr

0x80000022: 3200       stc   ssr,r0
	Registers read: ssr
	Registers modified: r0

0x80000024: 0af1       fmov  fr0,@r1
	Registers read: r1 fr0

0x80000026: 0900       nop   

********************
Platform: SH_SH2A
Code: 0x32 0x11 0x92 0x00 0x32 0x49 0x31 0x00 
Disasm:
0x80000000: 32119200   movu.w@(1024,r1),r2
	Registers read: r1
	Registers modified: r2

0x80000004: 32493100   bld.b #4,@(256,r2)
	Registers read: r2

<end of output>
Test time =   0.01 sec
----------------------------------------------------------
Test Passed.
"capstone_test_sh" end time: Feb 18 14:55 CET
"capstone_test_sh" time elapsed: 00:00:00
----------------------------------------------------------

23/24 Testing: capstone_test_tricore
23/24 Test: capstone_test_tricore
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_tricore"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_tricore" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------
****************
Platform: TriCore
Code:0x09 0xcf 0xbc 0xf5 0x09 0xf4 0x01 0x00 0x89 0xfb 0x8f 0x74 0x89 0xfe 0x48 0x01 0x29 0x00 0x19 0x25 0x29 0x03 0x09 0xf4 0x85 0xf9 0x68 0x0f 0x16 0x01 
Disasm:
0x1000:	ld.a	a15, [+a12]#-4
	op_count: 2
		operands[0].type: REG = a15
		operands[1].type: MEM
			operands[1].mem.base: REG = a12
			operands[1].mem.disp: 0xfffffffc

0x1004:	ld.b	d4, [a15+]#1
	op_count: 2
		operands[0].type: REG = d4
		operands[1].type: MEM
			operands[1].mem.base: REG = a15
			operands[1].mem.disp: 0x1

0x1008:	st.h	[+a15]#0x1cf, d11
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = a15
			operands[0].mem.disp: 0x1cf
		operands[1].type: REG = d11

0x100c:	st.d	[a15+]#8, e14
	op_count: 2
		operands[0].type: MEM
			operands[0].mem.base: REG = a15
			operands[0].mem.disp: 0x8
		operands[1].type: REG = e14

0x1010:	ld.w	d0, [p0+c]#0x99
	op_count: 2
		operands[0].type: REG = d0
		operands[1].type: MEM
			operands[1].mem.base: REG = p0
			operands[1].mem.disp: 0x99

0x1014:	ld.b	d3, [p0+c]#-0x37
	op_count: 2
		operands[0].type: REG = d3
		operands[1].type: MEM
			operands[1].mem.base: REG = p0
			operands[1].mem.disp: 0xffffffc9

0x1018:	ld.da	p8, #0xf0003428
	op_count: 2
		operands[0].type: REG = p8
		operands[1].type: IMM = 0xf0003428

0x101c:	and	d15, #1
	op_count: 1
		operands[0].type: IMM = 0x1

0x101e:

<end of output>
Test time =   0.01 sec
----------------------------------------------------------
Test Passed.
"capstone_test_tricore" end time: Feb 18 14:55 CET
"capstone_test_tricore" time elapsed: 00:00:00
----------------------------------------------------------

24/24 Testing: capstone_test_arm_regression
24/24 Test: capstone_test_arm_regression
Command: "/var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build/test_arm_regression"
Directory: /var/tmp/portage/dev-libs/capstone-5.0.1/work/capstone-5.0.1_build
"capstone_test_arm_regression" start time: Feb 18 14:55 CET
Output:
----------------------------------------------------------

Should be invalid
-----------------
Thumb bde81eff: invalid thumb2 pop because sp used and because both pc and lr are present at the same time
    ERROR:
    0x1000:	pop.w	{r1, r2, r3, r4, r8, r9, r10, r11, r12, sp, lr, pc}
	op_count: 12
		operands[0].type: REG = r1
		operands[1].type: REG = r2
		operands[2].type: REG = r3
		operands[3].type: REG = r4
		operands[4].type: REG = r8
		operands[5].type: REG = r9
		operands[6].type: REG = r10
		operands[7].type: REG = r11
		operands[8].type: REG = r12
		operands[9].type: REG = sp
		operands[10].type: REG = lr
		operands[11].type: REG = pc


Should be valid
---------------
Thumb 00f026e8 @ 0x0352: thumb2 blx with misaligned immediate
    0x352:	blx	#0x3a0
	op_count: 1
		operands[0].type: IMM = 0x3a0
    SUCCESS: valid
Thumb 05dd @ 0x01f0: thumb b cc with thumb-aligned target
    0x1f0:	ble	#0x1fe
	op_count: 1
		operands[0].type: IMM = 0x1fe
	Code condition: 14
    SUCCESS: valid
Thumb bde8f08f @ 0x0000: thumb2 pop that should be valid
    0x0:	pop.w	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
	op_count: 9
		operands[0].type: REG = r4
		operands[1].type: REG = r5
		operands[2].type: REG = r6
		operands[3].type: REG = r7
		operands[4].type: REG = r8
		operands[5].type: REG = r9
		operands[6].type: REG = r10
		operands[7].type: REG = r11
		operands[8].type: REG = pc
    SUCCESS: valid
<end of output>
Test time =   0.01 sec
----------------------------------------------------------
Test Passed.
"capstone_test_arm_regression" end time: Feb 18 14:55 CET
"capstone_test_arm_regression" time elapsed: 00:00:00
----------------------------------------------------------

End testing: Feb 18 14:55 CET