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Lines 58-83
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* conflicts. we try to rely on the kernel's provided interfaces when possible, |
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* conflicts. we try to rely on the kernel's provided interfaces when possible, |
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* but need additional flushing on earlier kernels. |
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* but need additional flushing on earlier kernels. |
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*/ |
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*/ |
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#if defined(KERNEL_2_4) |
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/* wrap CACHE_FLUSH so we can pass it to smp_call_function */ |
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static void cache_flush(void *p) |
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{ |
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CACHE_FLUSH(); |
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} |
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#endif |
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/* |
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/* |
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* 2.4 kernels handle flushing in the change_page_attr() call, but kernels |
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* 2.4 kernels handle flushing in the change_page_attr() call, but kernels |
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* earlier than 2.4.27 don't flush on cpus that support Self Snoop, so we |
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* earlier than 2.4.27 don't flush on cpus that support Self Snoop, so we |
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* manually flush on these kernels (actually, we go ahead and flush on all |
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* manually flush on these kernels (actually, we go ahead and flush on all |
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* 2.4 kernels, as it's possible some others may be missing this fix and |
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* 2.4 kernels, as it's possible some others may be missing this fix and |
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* we'd prefer to be a little slower flushing caches than hanging the |
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* we'd prefer to be a little slower flushing caches than hanging the |
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* system. 2.6 kernels split the flushing out to a seperate call, |
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* system. |
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* global_flush_tlb(), so we rely on that. |
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* 2.6 kernels split the flushing out to a seperate call, |
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* global_flush_tlb(), so we rely on that. however, there are some 2.6 |
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* x86_64 kernels that do not properly flush. for now, we'll flush on all |
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* potential kernels, as it's slightly slower, but safer. |
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*/ |
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*/ |
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#if defined(KERNEL_2_4) || (defined(KERNEL_2_6) && defined(NVCPU_X86_64)) |
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#define NV_CPA_NEEDS_FLUSHING 1 |
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#endif |
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#if defined(NV_CPA_NEEDS_FLUSHING) |
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static void cache_flush(void *p) |
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{ |
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unsigned long reg0, reg1; |
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CACHE_FLUSH(); |
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// flush global TLBs |
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#if defined (NVCPU_X86) |
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asm volatile("movl %%cr4, %0; \n" |
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"andl $~0x80, %0; \n" |
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"movl %0, %%cr4; \n" |
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"movl %%cr3, %1; \n" |
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"movl %1, %%cr3; \n" |
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"orl $0x80, %0; \n" |
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"movl %0, %%cr4; \n" |
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: "=&r" (reg0), "=&r" (reg1) |
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: : "memory"); |
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#else |
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asm volatile("movq %%cr4, %0; \n" |
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"andq $~0x80, %0; \n" |
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"movq %0, %%cr4; \n" |
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"movq %%cr3, %1; \n" |
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"movq %1, %%cr3; \n" |
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"orq $0x80, %0; \n" |
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"movq %0, %%cr4; \n" |
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: "=&r" (reg0), "=&r" (reg1) |
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: : "memory"); |
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#endif |
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} |
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#endif |
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static void nv_flush_caches(void) |
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static void nv_flush_caches(void) |
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{ |
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{ |
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#if defined(KERNEL_2_4) |
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#if defined(NV_CPA_NEEDS_FLUSHING) |
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#ifdef CONFIG_SMP |
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#ifdef CONFIG_SMP |
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smp_call_function(cache_flush, NULL, 1, 1); |
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smp_call_function(cache_flush, NULL, 1, 1); |
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#endif |
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#endif |
