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Lines 205-210
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| 205 |
16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) |
205 |
16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1))) |
| 206 |
div++; |
206 |
div++; |
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208 |
/* |
| 209 |
* Prefer lower base clock (fact = 0) if even divisor. |
| 210 |
* |
| 211 |
* Note that this makes the receiver more tolerant to errors. |
| 212 |
*/ |
| 213 |
if (fact == 1 && div % 2 == 0) { |
| 214 |
div /= 2; |
| 215 |
fact = 0; |
| 216 |
} |
| 217 |
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| 208 |
return (0x100 - div) << 8 | fact << 2 | ps; |
221 |
return (0x100 - div) << 8 | fact << 2 | ps; |
| 209 |
} |
222 |
} |
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