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(-)a/hw/core/machine.c (+3 lines)
Lines 24-29 Link Here
24
#include "hw/pci/pci.h"
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#include "hw/pci/pci.h"
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#include "hw/mem/nvdimm.h"
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#include "hw/mem/nvdimm.h"
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GlobalProperty hw_compat_4_0[] = {};
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const size_t hw_compat_4_0_len = G_N_ELEMENTS(hw_compat_4_0);
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GlobalProperty hw_compat_3_1[] = {
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GlobalProperty hw_compat_3_1[] = {
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    { "pcie-root-port", "x-speed", "2_5" },
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    { "pcie-root-port", "x-speed", "2_5" },
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    { "pcie-root-port", "x-width", "1" },
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    { "pcie-root-port", "x-width", "1" },
(-)a/hw/i386/pc.c (+3 lines)
Lines 115-120 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; Link Here
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/* Physical Address of PVH entry point read from kernel ELF NOTE */
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/* Physical Address of PVH entry point read from kernel ELF NOTE */
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static size_t pvh_start_addr;
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static size_t pvh_start_addr;
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GlobalProperty pc_compat_4_0[] = {};
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const size_t pc_compat_4_0_len = G_N_ELEMENTS(pc_compat_4_0);
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GlobalProperty pc_compat_3_1[] = {
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GlobalProperty pc_compat_3_1[] = {
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    { "intel-iommu", "dma-drain", "off" },
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    { "intel-iommu", "dma-drain", "off" },
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    { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
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    { "Opteron_G3" "-" TYPE_X86_CPU, "rdtscp", "off" },
(-)a/hw/i386/pc_q35.c (-2 / +14 lines)
Lines 357-363 static void pc_q35_machine_options(MachineClass *m) Link Here
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    m->units_per_default_bus = 1;
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    m->units_per_default_bus = 1;
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    m->default_machine_opts = "firmware=bios-256k.bin";
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    m->default_machine_opts = "firmware=bios-256k.bin";
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    m->default_display = "std";
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    m->default_display = "std";
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    m->default_kernel_irqchip_split = true;
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    m->default_kernel_irqchip_split = false;
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    m->no_floppy = 1;
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    m->no_floppy = 1;
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    machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
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    machine_class_allow_dynamic_sysbus_dev(m, TYPE_AMD_IOMMU_DEVICE);
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    machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
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    machine_class_allow_dynamic_sysbus_dev(m, TYPE_INTEL_IOMMU_DEVICE);
Lines 365-376 static void pc_q35_machine_options(MachineClass *m) Link Here
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    m->max_cpus = 288;
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    m->max_cpus = 288;
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}
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}
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static void pc_q35_4_0_machine_options(MachineClass *m)
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static void pc_q35_4_0_1_machine_options(MachineClass *m)
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{
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{
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    pc_q35_machine_options(m);
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    pc_q35_machine_options(m);
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    m->alias = "q35";
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    m->alias = "q35";
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}
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}
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DEFINE_Q35_MACHINE(v4_0_1, "pc-q35-4.0.1", NULL,
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                   pc_q35_4_0_1_machine_options);
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static void pc_q35_4_0_machine_options(MachineClass *m)
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{
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    pc_q35_4_0_1_machine_options(m);
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    m->default_kernel_irqchip_split = true;
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    m->alias = NULL;
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    compat_props_add(m->compat_props, hw_compat_4_0, hw_compat_4_0_len);
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    compat_props_add(m->compat_props, pc_compat_4_0, pc_compat_4_0_len);
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}
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DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
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DEFINE_Q35_MACHINE(v4_0, "pc-q35-4.0", NULL,
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                   pc_q35_4_0_machine_options);
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                   pc_q35_4_0_machine_options);
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(-)a/include/hw/boards.h (+3 lines)
Lines 293-298 struct MachineState { Link Here
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    } \
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    } \
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    type_init(machine_initfn##_register_types)
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    type_init(machine_initfn##_register_types)
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extern GlobalProperty hw_compat_4_0[];
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extern const size_t hw_compat_4_0_len;
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extern GlobalProperty hw_compat_3_1[];
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extern GlobalProperty hw_compat_3_1[];
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extern const size_t hw_compat_3_1_len;
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extern const size_t hw_compat_3_1_len;
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(-)a/include/hw/i386/pc.h (+3 lines)
Lines 293-298 int e820_add_entry(uint64_t, uint64_t, uint32_t); Link Here
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int e820_get_num_entries(void);
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int e820_get_num_entries(void);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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extern GlobalProperty pc_compat_4_0[];
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extern const size_t pc_compat_4_0_len;
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extern GlobalProperty pc_compat_3_1[];
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extern GlobalProperty pc_compat_3_1[];
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extern const size_t pc_compat_3_1_len;
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extern const size_t pc_compat_3_1_len;

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