Attachment #544028 for bug #664054

View | Details | Raw Unified | Return to bug 664054
Collapse All | Expand All

Lines 805-811 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { Link Here

(-)a/target/i386/cpu.c (-2 / +2 lines)
805	NULL, NULL, NULL, NULL,	805	NULL, NULL, NULL, NULL,
806	NULL, NULL, NULL, NULL,	806	NULL, NULL, NULL, NULL,
807	NULL, NULL, "spec-ctrl", NULL,	807	NULL, NULL, "spec-ctrl", NULL,
808	NULL, NULL, NULL, NULL,	808	NULL, NULL, NULL, "ssbd",
809	},	809	},
810	.cpuid_eax = 7,	810	.cpuid_eax = 7,
811	.cpuid_needs_ecx = true, .cpuid_ecx = 0,	811	.cpuid_needs_ecx = true, .cpuid_ecx = 0,
Lines 836-842 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { Link Here
836	"ibpb", NULL, NULL, NULL,	836	"ibpb", NULL, NULL, NULL,
837	NULL, NULL, NULL, NULL,	837	NULL, NULL, NULL, NULL,
838	NULL, NULL, NULL, NULL,	838	NULL, NULL, NULL, NULL,
839	NULL, NULL, NULL, NULL,	839	NULL, "virt-ssbd", NULL, NULL,
840	NULL, NULL, NULL, NULL,	840	NULL, NULL, NULL, NULL,
841	},	841	},
842	.cpuid_eax = 0x80000008,	842	.cpuid_eax = 0x80000008,




#define MSR_IA32_FEATURE_CONTROL        0x0000003a
#define MSR_TSC_ADJUST                  0x0000003b
#define MSR_IA32_SPEC_CTRL              0x48
#define MSR_VIRT_SSBD                   0xc001011f
#define MSR_IA32_TSCDEADLINE            0x6e0

#define FEATURE_CONTROL_LOCKED                    (1<<0)

#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */

#define KVM_HINTS_DEDICATED (1U << 0)


    uint32_t pkru;

    uint64_t spec_ctrl;
    uint64_t virt_ssbd;

    /* End of state preserved by INIT (dummy marker).  */
    struct {} end_init_save;

Lines 93-98 static bool has_msr_hv_frequencies; Link Here

(-)a/target/i386/kvm.c (-2 / +14 lines)
93	static bool has_msr_hv_reenlightenment;	93	static bool has_msr_hv_reenlightenment;
94	static bool has_msr_xss;	94	static bool has_msr_xss;
95	static bool has_msr_spec_ctrl;	95	static bool has_msr_spec_ctrl;
		96	static bool has_msr_virt_ssbd;
96	static bool has_msr_smi_count;	97	static bool has_msr_smi_count;
97		98
98	static uint32_t has_architectural_pmu_version;	99	static uint32_t has_architectural_pmu_version;
Lines 1233-1238 static int kvm_get_supported_msrs(KVMState *s) Link Here
1233	case MSR_IA32_SPEC_CTRL:	1234	case MSR_IA32_SPEC_CTRL:
1234	has_msr_spec_ctrl = true;	1235	has_msr_spec_ctrl = true;
1235	break;	1236	break;
		1237	case MSR_VIRT_SSBD:
		1238	has_msr_virt_ssbd = true;
		1239	break;
1236	}	1240	}
1237	}	1241	}
1238	}	1242	}
Lines 1721-1726 static int kvm_put_msrs(X86CPU *cpu, int level) Link Here
1721	if (has_msr_spec_ctrl) {	1725	if (has_msr_spec_ctrl) {
1722	kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);	1726	kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1723	}	1727	}
		1728	if (has_msr_virt_ssbd) {
		1729	kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
		1730	}
		1731
1724	#ifdef TARGET_X86_64	1732	#ifdef TARGET_X86_64
1725	if (lm_capable_kernel) {	1733	if (lm_capable_kernel) {
1726	kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);	1734	kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
Lines 2100-2107 static int kvm_get_msrs(X86CPU *cpu) Link Here
2100	if (has_msr_spec_ctrl) {	2108	if (has_msr_spec_ctrl) {
2101	kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);	2109	kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2102	}	2110	}
2103		2111	if (has_msr_virt_ssbd) {
2104		2112	kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
		2113	}
2105	if (!env->tsc_valid) {	2114	if (!env->tsc_valid) {
2106	kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);	2115	kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2107	env->tsc_valid = !runstate_is_running();	2116	env->tsc_valid = !runstate_is_running();
Lines 2481-2486 static int kvm_get_msrs(X86CPU *cpu) Link Here
2481	case MSR_IA32_SPEC_CTRL:	2490	case MSR_IA32_SPEC_CTRL:
2482	env->spec_ctrl = msrs[i].data;	2491	env->spec_ctrl = msrs[i].data;
2483	break;	2492	break;
		2493	case MSR_VIRT_SSBD:
		2494	env->virt_ssbd = msrs[i].data;
		2495	break;
2484	case MSR_IA32_RTIT_CTL:	2496	case MSR_IA32_RTIT_CTL:
2485	env->msr_rtit_ctrl = msrs[i].data;	2497	env->msr_rtit_ctrl = msrs[i].data;
2486	break;	2498	break;




    }
};

static bool virt_ssbd_needed(void *opaque)
{
    X86CPU *cpu = opaque;
    CPUX86State *env = &cpu->env;

    return env->virt_ssbd != 0;
}

static const VMStateDescription vmstate_msr_virt_ssbd = {
    .name = "cpu/virt_ssbd",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = virt_ssbd_needed,
    .fields = (VMStateField[]){
        VMSTATE_UINT64(env.virt_ssbd, X86CPU),
        VMSTATE_END_OF_LIST()
    }
};

VMStateDescription vmstate_x86_cpu = {
    .name = "cpu",
    .version_id = 12,

        &vmstate_spec_ctrl,
        &vmstate_mcg_ext_ctl,
        &vmstate_msr_intel_pt,
        &vmstate_msr_virt_ssbd,
        NULL
    }
};

Return to bug 664054

Lines 351-356 typedef enum X86Seg { Link Here

(-)a/target/i386/cpu.h (+3 lines)
351	#define MSR_IA32_FEATURE_CONTROL 0x0000003a	351	#define MSR_IA32_FEATURE_CONTROL 0x0000003a
352	#define MSR_TSC_ADJUST 0x0000003b	352	#define MSR_TSC_ADJUST 0x0000003b
353	#define MSR_IA32_SPEC_CTRL 0x48	353	#define MSR_IA32_SPEC_CTRL 0x48
		354	#define MSR_VIRT_SSBD 0xc001011f
354	#define MSR_IA32_TSCDEADLINE 0x6e0	355	#define MSR_IA32_TSCDEADLINE 0x6e0
355		356
356	#define FEATURE_CONTROL_LOCKED (1<<0)	357	#define FEATURE_CONTROL_LOCKED (1<<0)
Lines 685-690 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; Link Here
685	#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */	686	#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
686	#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */	687	#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
687	#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */	688	#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */
		689	#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */
688		690
689	#define KVM_HINTS_DEDICATED (1U << 0)	691	#define KVM_HINTS_DEDICATED (1U << 0)
690		692
Lines 1209-1214 typedef struct CPUX86State { Link Here
1209	uint32_t pkru;	1211	uint32_t pkru;
1210		1212
1211	uint64_t spec_ctrl;	1213	uint64_t spec_ctrl;
		1214	uint64_t virt_ssbd;
1212		1215
1213	/* End of state preserved by INIT (dummy marker). */	1216	/* End of state preserved by INIT (dummy marker). */
1214	struct {} end_init_save;	1217	struct {} end_init_save;

Lines 916-921 static const VMStateDescription vmstate_msr_intel_pt = { Link Here

(-)a/target/i386/machine.c (+20 lines)
916	}	916	}
917	};	917	};
918		918
		919	static bool virt_ssbd_needed(void *opaque)
		920	{
		921	X86CPU *cpu = opaque;
		922	CPUX86State *env = &cpu->env;
		923
		924	return env->virt_ssbd != 0;
		925	}
		926
		927	static const VMStateDescription vmstate_msr_virt_ssbd = {
		928	.name = "cpu/virt_ssbd",
		929	.version_id = 1,
		930	.minimum_version_id = 1,
		931	.needed = virt_ssbd_needed,
		932	.fields = (VMStateField[]){
		933	VMSTATE_UINT64(env.virt_ssbd, X86CPU),
		934	VMSTATE_END_OF_LIST()
		935	}
		936	};
		937
919	VMStateDescription vmstate_x86_cpu = {	938	VMStateDescription vmstate_x86_cpu = {
920	.name = "cpu",	939	.name = "cpu",
921	.version_id = 12,	940	.version_id = 12,
Lines 1039-1044 VMStateDescription vmstate_x86_cpu = { Link Here
1039	&vmstate_spec_ctrl,	1058	&vmstate_spec_ctrl,
1040	&vmstate_mcg_ext_ctl,	1059	&vmstate_mcg_ext_ctl,
1041	&vmstate_msr_intel_pt,	1060	&vmstate_msr_intel_pt,
		1061	&vmstate_msr_virt_ssbd,
1042	NULL	1062	NULL
1043	}	1063	}
1044	};	1064	};