Attachment #515520 for bug #643432

View | Details | Raw Unified | Return to bug 643432
Collapse All | Expand All




    case 7:
        /* Structured Extended Feature Flags Enumeration Leaf */
        if (count == 0) {
            host_cpuid(index, 0, eax, ebx, ecx, edx);
            *eax = 0; /* Maximum ECX value for sub-leaves */
            *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
            *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
            if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
                *ecx |= CPUID_7_0_ECX_OSPKE;
            }
            *edx = env->features[FEAT_7_0_EDX] | *edx;
        } else {
            *eax = 0;
            *ebx = 0;

Lines 333-338 Link Here

(-)a/target/i386/cpu.h (+4 lines)
333	#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)	333	#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
334	#define MSR_IA32_FEATURE_CONTROL 0x0000003a	334	#define MSR_IA32_FEATURE_CONTROL 0x0000003a
335	#define MSR_TSC_ADJUST 0x0000003b	335	#define MSR_TSC_ADJUST 0x0000003b
		336	#define MSR_IA32_SPEC_CTRL 0x00000048
336	#define MSR_IA32_TSCDEADLINE 0x6e0	337	#define MSR_IA32_TSCDEADLINE 0x6e0
337		338
338	#define FEATURE_CONTROL_LOCKED (1<<0)	339	#define FEATURE_CONTROL_LOCKED (1<<0)
Lines 639-644 typedef uint32_t FeatureWordArray[FEATURE_WORDS]; Link Here
639		640
640	#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */	641	#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
641	#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */	642	#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
		643	#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
		644	#define CPUID_7_0_EDX_PRED_CMD (1U << 27)
642		645
643	#define CPUID_XSAVE_XSAVEOPT (1U << 0)	646	#define CPUID_XSAVE_XSAVEOPT (1U << 0)
644	#define CPUID_XSAVE_XSAVEC (1U << 1)	647	#define CPUID_XSAVE_XSAVEC (1U << 1)
Lines 1181-1186 typedef struct CPUX86State { Link Here
1181		1184
1182	uint64_t xss;	1185	uint64_t xss;
1183		1186
		1187	uint64_t spec_ctrl;
1184	TPRAccess tpr_access_type;	1188	TPRAccess tpr_access_type;
1185	} CPUX86State;	1189	} CPUX86State;
1186		1190

Lines 75-80 static bool has_msr_star; Link Here

(-)a/target/i386/kvm.c (-1 / +14 lines)
75	static bool has_msr_hsave_pa;	75	static bool has_msr_hsave_pa;
76	static bool has_msr_tsc_aux;	76	static bool has_msr_tsc_aux;
77	static bool has_msr_tsc_adjust;	77	static bool has_msr_tsc_adjust;
		78	static bool has_msr_spec_ctrl;
78	static bool has_msr_tsc_deadline;	79	static bool has_msr_tsc_deadline;
79	static bool has_msr_feature_control;	80	static bool has_msr_feature_control;
80	static bool has_msr_misc_enable;	81	static bool has_msr_misc_enable;
Lines 1096-1101 static int kvm_get_supported_msrs(KVMState *s) Link Here
1096	has_msr_tsc_adjust = true;	1097	has_msr_tsc_adjust = true;
1097	continue;	1098	continue;
1098	}	1099	}
		1100	if (kvm_msr_list->indices[i] == MSR_IA32_SPEC_CTRL) {
		1101	has_msr_spec_ctrl = true;
		1102	continue;
		1103	}
1099	if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {	1104	if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
1100	has_msr_tsc_deadline = true;	1105	has_msr_tsc_deadline = true;
1101	continue;	1106	continue;
Lines 1667-1672 static int kvm_put_msrs(X86CPU *cpu, int level) Link Here
1667	if (has_msr_xss) {	1672	if (has_msr_xss) {
1668	kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);	1673	kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1669	}	1674	}
		1675	if (has_msr_spec_ctrl) {
		1676	kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
		1677	}
1670	#ifdef TARGET_X86_64	1678	#ifdef TARGET_X86_64
1671	if (lm_capable_kernel) {	1679	if (lm_capable_kernel) {
1672	kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);	1680	kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
Lines 2081-2087 static int kvm_get_msrs(X86CPU *cpu) Link Here
2081	if (has_msr_xss) {	2089	if (has_msr_xss) {
2082	kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);	2090	kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2083	}	2091	}
2084		2092	if (has_msr_spec_ctrl) {
		2093	kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
		2094	}
2085		2095
2086	if (!env->tsc_valid) {	2096	if (!env->tsc_valid) {
2087	kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);	2097	kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
Lines 2303-2308 static int kvm_get_msrs(X86CPU *cpu) Link Here
2303	case MSR_IA32_XSS:	2313	case MSR_IA32_XSS:
2304	env->xss = msrs[i].data;	2314	env->xss = msrs[i].data;
2305	break;	2315	break;
		2316	case MSR_IA32_SPEC_CTRL:
		2317	env->spec_ctrl = msrs[i].data;
		2318	break;
2306	default:	2319	default:
2307	if (msrs[i].index >= MSR_MC0_CTL &&	2320	if (msrs[i].index >= MSR_MC0_CTL &&
2308	msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {	2321	msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {




    }
};

static bool spec_ctrl_needed(void *opaque)
{
    X86CPU *cpu = opaque;
    CPUX86State *env = &cpu->env;

    return env->spec_ctrl != 0;
}

static const VMStateDescription vmstate_spec_ctrl = {
    .name = "cpu/spec_ctrl",
    .version_id = 1,
    .minimum_version_id = 1,
    .needed = spec_ctrl_needed,
    .fields = (VMStateField[]) {
        VMSTATE_UINT64(env.spec_ctrl, X86CPU),
        VMSTATE_END_OF_LIST()
    }
};

#ifdef TARGET_X86_64
static bool pkru_needed(void *opaque)
{

        &vmstate_msr_hyperv_stimer,
        &vmstate_avx512,
        &vmstate_xss,
        &vmstate_spec_ctrl,
        &vmstate_tsc_khz,
#ifdef TARGET_X86_64
        &vmstate_pkru,

Return to bug 643432

Lines 2823-2835 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, Link Here

(-)a/target/i386/cpu.c (-1 / +2 lines)
2823	case 7:	2823	case 7:
2824	/* Structured Extended Feature Flags Enumeration Leaf */	2824	/* Structured Extended Feature Flags Enumeration Leaf */
2825	if (count == 0) {	2825	if (count == 0) {
		2826	host_cpuid(index, 0, eax, ebx, ecx, edx);
2826	eax = 0; / Maximum ECX value for sub-leaves */	2827	eax = 0; / Maximum ECX value for sub-leaves */
2827	ebx = env->features[FEAT_7_0_EBX]; / Feature flags */	2828	ebx = env->features[FEAT_7_0_EBX]; / Feature flags */
2828	ecx = env->features[FEAT_7_0_ECX]; / Feature flags */	2829	ecx = env->features[FEAT_7_0_ECX]; / Feature flags */
2829	if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {	2830	if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2830	*ecx \|= CPUID_7_0_ECX_OSPKE;	2831	*ecx \|= CPUID_7_0_ECX_OSPKE;
2831	}	2832	}
2832	edx = env->features[FEAT_7_0_EDX]; / Feature flags */	2833	edx = env->features[FEAT_7_0_EDX] \| edx;
2833	} else {	2834	} else {
2834	*eax = 0;	2835	*eax = 0;
2835	*ebx = 0;	2836	*ebx = 0;

Lines 868-873 static const VMStateDescription vmstate_xss = { Link Here

(-)a/target/i386/machine.c (+20 lines)
868	}	868	}
869	};	869	};
870		870
		871	static bool spec_ctrl_needed(void *opaque)
		872	{
		873	X86CPU *cpu = opaque;
		874	CPUX86State *env = &cpu->env;
		875
		876	return env->spec_ctrl != 0;
		877	}
		878
		879	static const VMStateDescription vmstate_spec_ctrl = {
		880	.name = "cpu/spec_ctrl",
		881	.version_id = 1,
		882	.minimum_version_id = 1,
		883	.needed = spec_ctrl_needed,
		884	.fields = (VMStateField[]) {
		885	VMSTATE_UINT64(env.spec_ctrl, X86CPU),
		886	VMSTATE_END_OF_LIST()
		887	}
		888	};
		889
871	#ifdef TARGET_X86_64	890	#ifdef TARGET_X86_64
872	static bool pkru_needed(void *opaque)	891	static bool pkru_needed(void *opaque)
873	{	892	{
Lines 1049-1054 VMStateDescription vmstate_x86_cpu = { Link Here
1049	&vmstate_msr_hyperv_stimer,	1068	&vmstate_msr_hyperv_stimer,
1050	&vmstate_avx512,	1069	&vmstate_avx512,
1051	&vmstate_xss,	1070	&vmstate_xss,
		1071	&vmstate_spec_ctrl,
1052	&vmstate_tsc_khz,	1072	&vmstate_tsc_khz,
1053	#ifdef TARGET_X86_64	1073	#ifdef TARGET_X86_64
1054	&vmstate_pkru,	1074	&vmstate_pkru,