--- bitcoin-0.13.1-cxx11/src/test/test_bitcoin.cpp
+++ bitcoin-0.13.1-uclibc/src/test/test_bitcoin.cpp
@@ -158,3 +158,82 @@ bool ShutdownRequested()
 {
   return false;
 }
+
+int main(int argc, char** argv)
+{
+	new TestChain100Setup();
+	return 0;
+}
+
+
+#ifdef __UCLIBC__
+#if defined __i386__ || defined __amd64__
+#include <fenv.h>
+#include <x86intrin.h>
+
+#define	_SSE_MASK_SHIFT 7
+
+static inline unsigned short get_x87_sw(void)
+{
+	unsigned short sw;
+	__asm__("fnstsw %0" : "=a"(sw));
+	return sw;
+}
+
+int feclearexcept(int mask)
+{
+	unsigned short sw = get_x87_sw();
+	if (sw & mask & FE_ALL_EXCEPT) {
+        	__asm__("fnclex");
+	}
+	unsigned int mxcsr = _mm_getcsr();
+	mxcsr |= sw & FE_ALL_EXCEPT;
+	if (mxcsr & mask & FE_ALL_EXCEPT) {
+		_mm_setcsr(mxcsr & ~(mask & FE_ALL_EXCEPT));
+	}
+	return 0;
+}
+
+int feenableexcept(int mask)
+{
+	unsigned int mxcsr, omask;
+	unsigned short control;
+
+	mask &= FE_ALL_EXCEPT;
+
+	__asm__ volatile ("fnstcw %0" : "=m" (control));
+	__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr));
+
+	omask = ~(control | (mxcsr >> _SSE_MASK_SHIFT)) & FE_ALL_EXCEPT;
+	control &= ~mask;
+	__asm__ volatile ("fldcw %0" : : "m" (control));
+
+	mxcsr &= ~(mask << _SSE_MASK_SHIFT);
+	__asm__ volatile ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (omask);
+}
+
+int fedisableexcept(int mask)
+{
+	unsigned int mxcsr, omask;
+	unsigned short control;
+
+	mask &= FE_ALL_EXCEPT;
+
+	__asm__ volatile ("fnstcw %0" : "=m" (control));
+	__asm__ volatile ("stmxcsr %0" : "=m" (mxcsr));
+
+	omask = ~(control | (mxcsr >> _SSE_MASK_SHIFT)) & FE_ALL_EXCEPT;
+	control |= mask;
+	__asm__ volatile ("fldcw %0" : : "m" (control));
+
+	mxcsr |= mask << _SSE_MASK_SHIFT;
+	__asm__ volatile ("ldmxcsr %0" : : "m" (mxcsr));
+
+	return (omask);
+}
+#else
+#error Only IA32 and AMD64 architectures are supported for fe*except
+#endif
+#endif
Binary files bitcoin-0.13.1-cxx11/src/test/test_test_bitcoin-test_bitcoin.o and bitcoin-0.13.1-uclibc/src/test/test_test_bitcoin-test_bitcoin.o differ