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Lines 25-30
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| 25 |
UNSPEC_FILD_ATOMIC |
25 |
UNSPEC_FILD_ATOMIC |
| 26 |
UNSPEC_FIST_ATOMIC |
26 |
UNSPEC_FIST_ATOMIC |
| 27 |
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27 |
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28 |
UNSPEC_LDX_ATOMIC |
| 29 |
UNSPEC_STX_ATOMIC |
| 30 |
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| 28 |
;; __atomic support |
31 |
;; __atomic support |
| 29 |
UNSPEC_LDA |
32 |
UNSPEC_LDA |
| 30 |
UNSPEC_STA |
33 |
UNSPEC_STA |
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Lines 199-207
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| 199 |
} |
202 |
} |
| 200 |
else |
203 |
else |
| 201 |
{ |
204 |
{ |
| 202 |
adjust_reg_mode (tmp, DImode); |
205 |
emit_insn (gen_loaddi_via_sse (tmp, src)); |
| 203 |
emit_move_insn (tmp, src); |
206 |
emit_insn (gen_storedi_via_sse (mem, tmp)); |
| 204 |
emit_move_insn (mem, tmp); |
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| 205 |
} |
207 |
} |
| 206 |
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208 |
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| 207 |
if (mem != dst) |
209 |
if (mem != dst) |
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Lines 226-235
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| 226 |
"operands[5] = gen_lowpart (DFmode, operands[1]);") |
228 |
"operands[5] = gen_lowpart (DFmode, operands[1]);") |
| 227 |
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229 |
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| 228 |
(define_peephole2 |
230 |
(define_peephole2 |
| 229 |
[(set (match_operand:DI 0 "sse_reg_operand") |
231 |
[(set (match_operand:DF 0 "sse_reg_operand") |
| 230 |
(match_operand:DI 1 "memory_operand")) |
232 |
(unspec:DF [(match_operand:DI 1 "memory_operand")] |
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233 |
UNSPEC_LDX_ATOMIC)) |
| 231 |
(set (match_operand:DI 2 "memory_operand") |
234 |
(set (match_operand:DI 2 "memory_operand") |
| 232 |
(match_dup 0)) |
235 |
(unspec:DI [(match_dup 0)] |
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236 |
UNSPEC_STX_ATOMIC)) |
| 233 |
(set (match_operand:DF 3 "fp_register_operand") |
237 |
(set (match_operand:DF 3 "fp_register_operand") |
| 234 |
(match_operand:DF 4 "memory_operand"))] |
238 |
(match_operand:DF 4 "memory_operand"))] |
| 235 |
"!TARGET_64BIT |
239 |
"!TARGET_64BIT |
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Lines 301-307
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| 301 |
rtx dst = operands[0], src = operands[1]; |
305 |
rtx dst = operands[0], src = operands[1]; |
| 302 |
rtx mem = operands[2], tmp = operands[3]; |
306 |
rtx mem = operands[2], tmp = operands[3]; |
| 303 |
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307 |
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| 304 |
if (!SSE_REG_P (src)) |
308 |
if (SSE_REG_P (src)) |
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309 |
emit_move_insn (dst, src); |
| 310 |
else |
| 305 |
{ |
311 |
{ |
| 306 |
if (REG_P (src)) |
312 |
if (REG_P (src)) |
| 307 |
{ |
313 |
{ |
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Lines 313-328
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| 313 |
{ |
319 |
{ |
| 314 |
emit_insn (gen_loaddi_via_fpu (tmp, src)); |
320 |
emit_insn (gen_loaddi_via_fpu (tmp, src)); |
| 315 |
emit_insn (gen_storedi_via_fpu (dst, tmp)); |
321 |
emit_insn (gen_storedi_via_fpu (dst, tmp)); |
| 316 |
DONE; |
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| 317 |
} |
322 |
} |
| 318 |
else |
323 |
else |
| 319 |
{ |
324 |
{ |
| 320 |
adjust_reg_mode (tmp, DImode); |
325 |
emit_insn (gen_loaddi_via_sse (tmp, src)); |
| 321 |
emit_move_insn (tmp, src); |
326 |
emit_insn (gen_storedi_via_sse (dst, tmp)); |
| 322 |
src = tmp; |
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| 323 |
} |
327 |
} |
| 324 |
} |
328 |
} |
| 325 |
emit_move_insn (dst, src); |
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| 326 |
DONE; |
329 |
DONE; |
| 327 |
}) |
330 |
}) |
| 328 |
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331 |
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Lines 344-353
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| 344 |
(define_peephole2 |
347 |
(define_peephole2 |
| 345 |
[(set (match_operand:DF 0 "memory_operand") |
348 |
[(set (match_operand:DF 0 "memory_operand") |
| 346 |
(match_operand:DF 1 "fp_register_operand")) |
349 |
(match_operand:DF 1 "fp_register_operand")) |
| 347 |
(set (match_operand:DI 2 "sse_reg_operand") |
350 |
(set (match_operand:DF 2 "sse_reg_operand") |
| 348 |
(match_operand:DI 3 "memory_operand")) |
351 |
(unspec:DF [(match_operand:DI 3 "memory_operand")] |
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352 |
UNSPEC_LDX_ATOMIC)) |
| 349 |
(set (match_operand:DI 4 "memory_operand") |
353 |
(set (match_operand:DI 4 "memory_operand") |
| 350 |
(match_dup 2))] |
354 |
(unspec:DI [(match_dup 2)] |
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355 |
UNSPEC_STX_ATOMIC))] |
| 351 |
"!TARGET_64BIT |
356 |
"!TARGET_64BIT |
| 352 |
&& peep2_reg_dead_p (3, operands[2]) |
357 |
&& peep2_reg_dead_p (3, operands[2]) |
| 353 |
&& rtx_equal_p (operands[0], adjust_address_nv (operands[3], DFmode, 0))" |
358 |
&& rtx_equal_p (operands[0], adjust_address_nv (operands[3], DFmode, 0))" |
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Lines 382-387
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| 382 |
[(set_attr "type" "fmov") |
387 |
[(set_attr "type" "fmov") |
| 383 |
(set_attr "mode" "DI")]) |
388 |
(set_attr "mode" "DI")]) |
| 384 |
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389 |
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390 |
(define_insn "loaddi_via_sse" |
| 391 |
[(set (match_operand:DF 0 "register_operand" "=x") |
| 392 |
(unspec:DF [(match_operand:DI 1 "memory_operand" "m")] |
| 393 |
UNSPEC_LDX_ATOMIC))] |
| 394 |
"TARGET_SSE" |
| 395 |
{ |
| 396 |
if (TARGET_SSE2) |
| 397 |
return "%vmovq\t{%1, %0|%0, %1}"; |
| 398 |
return "movlps\t{%1, %0|%0, %1}"; |
| 399 |
} |
| 400 |
[(set_attr "type" "ssemov") |
| 401 |
(set_attr "mode" "DI")]) |
| 402 |
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| 403 |
(define_insn "storedi_via_sse" |
| 404 |
[(set (match_operand:DI 0 "memory_operand" "=m") |
| 405 |
(unspec:DI [(match_operand:DF 1 "register_operand" "x")] |
| 406 |
UNSPEC_STX_ATOMIC))] |
| 407 |
"TARGET_SSE" |
| 408 |
{ |
| 409 |
if (TARGET_SSE2) |
| 410 |
return "%vmovq\t{%1, %0|%0, %1}"; |
| 411 |
return "movlps\t{%1, %0|%0, %1}"; |
| 412 |
} |
| 413 |
[(set_attr "type" "ssemov") |
| 414 |
(set_attr "mode" "DI")]) |
| 415 |
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| 385 |
(define_expand "atomic_compare_and_swap<mode>" |
416 |
(define_expand "atomic_compare_and_swap<mode>" |
| 386 |
[(match_operand:QI 0 "register_operand") ;; bool success output |
417 |
[(match_operand:QI 0 "register_operand") ;; bool success output |
| 387 |
(match_operand:SWI124 1 "register_operand") ;; oldval output |
418 |
(match_operand:SWI124 1 "register_operand") ;; oldval output |
