|
Line
Link Here
|
| 0 |
-- b/lib/Target/AMDGPU/SIInstructions.td |
0 |
++ a/lib/Target/AMDGPU/SIInstructions.td |
|
Lines 2029-2035
Link Here
|
| 2029 |
let hasSideEffects = 1; |
2029 |
let hasSideEffects = 1; |
| 2030 |
let SALU = 1; |
2030 |
let SALU = 1; |
| 2031 |
let hasNoSchedulingInfo = 1; |
2031 |
let hasNoSchedulingInfo = 1; |
| 2032 |
let DisableWQM = 1; |
|
|
| 2033 |
} |
2032 |
} |
| 2034 |
|
2033 |
|
| 2035 |
let Uses = [EXEC], Defs = [EXEC, VCC, M0], |
2034 |
let Uses = [EXEC], Defs = [EXEC, VCC, M0], |
| 2036 |
-- b/lib/Target/AMDGPU/SIWholeQuadMode.cpp |
2035 |
++ a/lib/Target/AMDGPU/SIWholeQuadMode.cpp |
|
Lines 219-224
Link Here
|
| 219 |
markInstruction(MI, Flags, Worklist); |
219 |
markInstruction(MI, Flags, Worklist); |
| 220 |
GlobalFlags |= Flags; |
220 |
GlobalFlags |= Flags; |
| 221 |
} |
221 |
} |
|
|
222 |
|
| 223 |
if (WQMOutputs && MBB.succ_empty()) { |
| 224 |
// This is a prolog shader. Make sure we go back to exact mode at the end. |
| 225 |
Blocks[&MBB].OutNeeds = StateExact; |
| 226 |
Worklist.push_back(&MBB); |
| 227 |
GlobalFlags |= StateExact; |
| 228 |
} |
| 222 |
} |
229 |
} |
| 223 |
|
230 |
|
| 224 |
return GlobalFlags; |
231 |
return GlobalFlags; |
| 225 |
-- b/test/CodeGen/AMDGPU/wqm.ll |
232 |
++ a/test/CodeGen/AMDGPU/wqm.ll |
|
Lines 17-34
Link Here
|
| 17 |
;CHECK-LABEL: {{^}}test2: |
17 |
;CHECK-LABEL: {{^}}test2: |
| 18 |
;CHECK-NEXT: ; %main_body |
18 |
;CHECK-NEXT: ; %main_body |
| 19 |
;CHECK-NEXT: s_wqm_b64 exec, exec |
19 |
;CHECK-NEXT: s_wqm_b64 exec, exec |
|
|
20 |
;CHECK: image_sample |
| 20 |
;CHECK-NOT: exec |
21 |
;CHECK-NOT: exec |
| 21 |
define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) { |
22 |
;CHECK: _load_dword v0, |
|
|
23 |
define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) { |
| 22 |
main_body: |
24 |
main_body: |
| 23 |
%c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
25 |
%c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
| 24 |
%c.2 = bitcast <4 x float> %c.1 to <4 x i32> |
26 |
%c.2 = bitcast <4 x float> %c.1 to <4 x i32> |
| 25 |
%c.3 = extractelement <4 x i32> %c.2, i32 0 |
27 |
%c.3 = extractelement <4 x i32> %c.2, i32 0 |
| 26 |
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3 |
28 |
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3 |
| 27 |
%data = load float, float addrspace(1)* %gep |
29 |
%data = load float, float addrspace(1)* %gep |
| 28 |
|
30 |
ret float %data |
| 29 |
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %data, float undef, float undef, float undef) |
|
|
| 30 |
|
| 31 |
ret void |
| 32 |
} |
31 |
} |
| 33 |
|
32 |
|
| 34 |
; ... but disabled for stores (and, in this simple case, not re-enabled). |
33 |
; ... but disabled for stores (and, in this simple case, not re-enabled). |
|
Lines 415-460
Link Here
|
| 415 |
ret void |
414 |
ret void |
| 416 |
} |
415 |
} |
| 417 |
|
416 |
|
| 418 |
; Must return to exact at the end of a non-void returning shader, |
|
|
| 419 |
; otherwise the EXEC mask exported by the epilog will be wrong. This is true |
| 420 |
; even if the shader has no kills, because a kill could have happened in a |
| 421 |
; previous shader fragment. |
| 422 |
; |
| 423 |
; CHECK-LABEL: {{^}}test_nonvoid_return: |
| 424 |
; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec |
| 425 |
; CHECK: s_wqm_b64 exec, exec |
| 426 |
; |
| 427 |
; CHECK: s_and_b64 exec, exec, [[LIVE]] |
| 428 |
; CHECK-NOT: exec |
| 429 |
define amdgpu_ps <4 x float> @test_nonvoid_return() nounwind { |
| 430 |
%tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
| 431 |
%tex.i = bitcast <4 x float> %tex to <4 x i32> |
| 432 |
%dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
| 433 |
ret <4 x float> %dtex |
| 434 |
} |
| 435 |
|
| 436 |
; CHECK-LABEL: {{^}}test_nonvoid_return_unreachable: |
| 437 |
; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec |
| 438 |
; CHECK: s_wqm_b64 exec, exec |
| 439 |
; |
| 440 |
; CHECK: s_and_b64 exec, exec, [[LIVE]] |
| 441 |
; CHECK-NOT: exec |
| 442 |
define amdgpu_ps <4 x float> @test_nonvoid_return_unreachable(i32 inreg %c) nounwind { |
| 443 |
entry: |
| 444 |
%tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
| 445 |
%tex.i = bitcast <4 x float> %tex to <4 x i32> |
| 446 |
%dtex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tex.i, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) |
| 447 |
|
| 448 |
%cc = icmp sgt i32 %c, 0 |
| 449 |
br i1 %cc, label %if, label %else |
| 450 |
|
| 451 |
if: |
| 452 |
store volatile <4 x float> %dtex, <4 x float>* undef |
| 453 |
unreachable |
| 454 |
|
| 455 |
else: |
| 456 |
ret <4 x float> %dtex |
| 457 |
} |
| 458 |
|
417 |
|
| 459 |
declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 |
418 |
declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 |
| 460 |
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1 |
419 |
declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #1 |
