Lines 49-55
Link Here
|
49 |
#endif /* CONFIG_PPC_OF */ |
49 |
#endif /* CONFIG_PPC_OF */ |
50 |
|
50 |
|
51 |
#define DRV_NAME "sata_svw" |
51 |
#define DRV_NAME "sata_svw" |
52 |
#define DRV_VERSION "1.04" |
52 |
#define DRV_VERSION "1.05" |
53 |
|
53 |
|
54 |
/* Taskfile registers offsets */ |
54 |
/* Taskfile registers offsets */ |
55 |
#define K2_SATA_TF_CMD_OFFSET 0x00 |
55 |
#define K2_SATA_TF_CMD_OFFSET 0x00 |
Lines 75-84
Link Here
|
75 |
#define K2_SATA_SICR1_OFFSET 0x80 |
75 |
#define K2_SATA_SICR1_OFFSET 0x80 |
76 |
#define K2_SATA_SICR2_OFFSET 0x84 |
76 |
#define K2_SATA_SICR2_OFFSET 0x84 |
77 |
#define K2_SATA_SIM_OFFSET 0x88 |
77 |
#define K2_SATA_SIM_OFFSET 0x88 |
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|
78 |
#define K2_SATA_MDIO_ACCESS 0x8c |
78 |
|
79 |
|
79 |
/* Port stride */ |
80 |
/* Port stride */ |
80 |
#define K2_SATA_PORT_OFFSET 0x100 |
81 |
#define K2_SATA_PORT_OFFSET 0x100 |
81 |
|
82 |
|
|
|
83 |
/* Private structure */ |
84 |
struct k2_sata_priv |
85 |
{ |
86 |
#ifdef CONFIG_PPC_OF |
87 |
struct device_node *of_node; |
88 |
#endif |
89 |
int need_mdio_phy_reset; |
90 |
}; |
82 |
|
91 |
|
83 |
static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
92 |
static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg) |
84 |
{ |
93 |
{ |
Lines 96-101
static void k2_sata_scr_write (struct at
Link Here
|
96 |
writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
105 |
writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4)); |
97 |
} |
106 |
} |
98 |
|
107 |
|
|
|
108 |
static u16 k2_sata_mdio_read(struct ata_host_set *host_set, int reg) |
109 |
{ |
110 |
u16 val; |
111 |
int timeout; |
112 |
|
113 |
writel((reg & 0x1f) | 0x4000, |
114 |
host_set->mmio_base + K2_SATA_MDIO_ACCESS); |
115 |
for(timeout = 10000; timeout > 0; timeout++) { |
116 |
val = readl(host_set->mmio_base + K2_SATA_MDIO_ACCESS); |
117 |
if (val & 0x8000) |
118 |
break; |
119 |
udelay(100); |
120 |
} |
121 |
if (timeout <= 0) { |
122 |
printk(KERN_WARNING "sata_svw: timeout reading MDIO reg %d\n", reg); |
123 |
return 0xffff; |
124 |
} |
125 |
return val >> 16; |
126 |
} |
127 |
|
128 |
static void k2_sata_mdio_write(struct ata_host_set *host_set, int reg, u16 val) |
129 |
{ |
130 |
int timeout; |
131 |
|
132 |
writel((reg & 0x1f) | (((u32)val) << 16) | 0x2000, |
133 |
host_set->mmio_base + K2_SATA_MDIO_ACCESS); |
134 |
for(timeout = 10000; timeout > 0; timeout++) { |
135 |
val = readl(host_set->mmio_base + K2_SATA_MDIO_ACCESS); |
136 |
if (val & 0x8000) |
137 |
break; |
138 |
udelay(100); |
139 |
} |
140 |
if (timeout <= 0) |
141 |
printk(KERN_WARNING "sata_svw: timeout writing MDIO reg %d\n", reg); |
142 |
} |
99 |
|
143 |
|
100 |
static void k2_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf) |
144 |
static void k2_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf) |
101 |
{ |
145 |
{ |
Lines 220-225
static u8 k2_stat_check_status(struct at
Link Here
|
220 |
return readl((void *) ap->ioaddr.status_addr); |
264 |
return readl((void *) ap->ioaddr.status_addr); |
221 |
} |
265 |
} |
222 |
|
266 |
|
|
|
267 |
static void k2_sata_mdio_phy_reset(struct ata_host_set *host_set) |
268 |
{ |
269 |
u16 reg; |
270 |
|
271 |
reg = k2_sata_mdio_read(host_set, 4); |
272 |
k2_sata_mdio_write(host_set, 4, reg | 0x0008); |
273 |
udelay(200); |
274 |
k2_sata_mdio_write(host_set, 4, reg); |
275 |
udelay(250); |
276 |
} |
277 |
|
278 |
static void k2_sata_host_start(struct ata_host_set *host_set) |
279 |
{ |
280 |
struct k2_sata_priv *pp; |
281 |
|
282 |
pp = host_set->private_data; |
283 |
|
284 |
/* Some cell revs need a HW reset of the PHY layer at this point, and |
285 |
* on wakeup from power management |
286 |
*/ |
287 |
if (pp->need_mdio_phy_reset) |
288 |
k2_sata_mdio_phy_reset(host_set); |
289 |
} |
290 |
|
291 |
|
223 |
#ifdef CONFIG_PPC_OF |
292 |
#ifdef CONFIG_PPC_OF |
224 |
/* |
293 |
/* |
225 |
* k2_sata_proc_info |
294 |
* k2_sata_proc_info |
Lines 237-242
static int k2_sata_proc_info(struct Scsi
Link Here
|
237 |
{ |
306 |
{ |
238 |
struct ata_port *ap; |
307 |
struct ata_port *ap; |
239 |
struct device_node *np; |
308 |
struct device_node *np; |
|
|
309 |
struct k2_sata_priv *pp; |
240 |
int len, index; |
310 |
int len, index; |
241 |
|
311 |
|
242 |
/* Find the ata_port */ |
312 |
/* Find the ata_port */ |
Lines 245-251
static int k2_sata_proc_info(struct Scsi
Link Here
|
245 |
return 0; |
315 |
return 0; |
246 |
|
316 |
|
247 |
/* Find the OF node for the PCI device proper */ |
317 |
/* Find the OF node for the PCI device proper */ |
248 |
np = pci_device_to_OF_node(ap->host_set->pdev); |
318 |
pp = ap->host_set->private_data; |
|
|
319 |
np = pp->of_node; |
249 |
if (np == NULL) |
320 |
if (np == NULL) |
250 |
return 0; |
321 |
return 0; |
251 |
|
322 |
|
Lines 310-315
static struct ata_port_operations k2_sat
Link Here
|
310 |
.scr_write = k2_sata_scr_write, |
381 |
.scr_write = k2_sata_scr_write, |
311 |
.port_start = ata_port_start, |
382 |
.port_start = ata_port_start, |
312 |
.port_stop = ata_port_stop, |
383 |
.port_stop = ata_port_stop, |
|
|
384 |
.host_start = k2_sata_host_start, |
313 |
}; |
385 |
}; |
314 |
|
386 |
|
315 |
static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base) |
387 |
static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base) |
Lines 338-343
static int k2_sata_init_one (struct pci_
Link Here
|
338 |
struct ata_probe_ent *probe_ent = NULL; |
410 |
struct ata_probe_ent *probe_ent = NULL; |
339 |
unsigned long base; |
411 |
unsigned long base; |
340 |
void *mmio_base; |
412 |
void *mmio_base; |
|
|
413 |
struct k2_sata_priv *pp = NULL; |
341 |
int rc; |
414 |
int rc; |
342 |
|
415 |
|
343 |
if (!printed_version++) |
416 |
if (!printed_version++) |
Lines 376-384
static int k2_sata_init_one (struct pci_
Link Here
|
376 |
} |
449 |
} |
377 |
|
450 |
|
378 |
memset(probe_ent, 0, sizeof(*probe_ent)); |
451 |
memset(probe_ent, 0, sizeof(*probe_ent)); |
|
|
452 |
|
453 |
pp = (struct k2_sata_priv *)kmalloc(sizeof(struct k2_sata_priv), GFP_KERNEL); |
454 |
if (pp == NULL) { |
455 |
rc = -ENOMEM; |
456 |
goto err_out_free_ent; |
457 |
} |
458 |
memset(pp, 0, sizeof(struct k2_sata_priv)); |
459 |
|
379 |
probe_ent->pdev = pdev; |
460 |
probe_ent->pdev = pdev; |
380 |
INIT_LIST_HEAD(&probe_ent->node); |
461 |
INIT_LIST_HEAD(&probe_ent->node); |
381 |
|
462 |
|
|
|
463 |
probe_ent->private_data = pdev; |
464 |
|
465 |
#ifdef CONFIG_PPC_OF |
466 |
/* Find the OF node for the PCI device proper */ |
467 |
pp->of_node = pci_device_to_OF_node(pdev); |
468 |
|
469 |
/* Check for revision 1 */ |
470 |
if (pp->of_node) { |
471 |
u32 *rev; |
472 |
rev = (u32 *)get_property(pp->of_node, "cell-revision", NULL); |
473 |
if (rev && (*rev) > 0) |
474 |
pp->need_mdio_phy_reset = 1; |
475 |
} |
476 |
#endif /* CONFIG_PPC_OF */ |
382 |
mmio_base = ioremap(pci_resource_start(pdev, 5), |
477 |
mmio_base = ioremap(pci_resource_start(pdev, 5), |
383 |
pci_resource_len(pdev, 5)); |
478 |
pci_resource_len(pdev, 5)); |
384 |
if (mmio_base == NULL) { |
479 |
if (mmio_base == NULL) { |
Lines 404-409
static int k2_sata_init_one (struct pci_
Link Here
|
404 |
probe_ent->port_ops = &k2_sata_ops; |
499 |
probe_ent->port_ops = &k2_sata_ops; |
405 |
probe_ent->n_ports = 4; |
500 |
probe_ent->n_ports = 4; |
406 |
probe_ent->irq = pdev->irq; |
501 |
probe_ent->irq = pdev->irq; |
|
|
502 |
/* JMA: hack to fix IRQ on Imac G5 */ |
503 |
if (probe_ent->irq == 0) |
504 |
probe_ent->irq = 0xA; |
407 |
probe_ent->irq_flags = SA_SHIRQ; |
505 |
probe_ent->irq_flags = SA_SHIRQ; |
408 |
probe_ent->mmio_base = mmio_base; |
506 |
probe_ent->mmio_base = mmio_base; |
409 |
|
507 |
|
Lines 429-434
static int k2_sata_init_one (struct pci_
Link Here
|
429 |
return 0; |
527 |
return 0; |
430 |
|
528 |
|
431 |
err_out_free_ent: |
529 |
err_out_free_ent: |
|
|
530 |
if (pp) |
531 |
kfree(pp); |
532 |
if (probe_ent) |
432 |
kfree(probe_ent); |
533 |
kfree(probe_ent); |
433 |
err_out_regions: |
534 |
err_out_regions: |
434 |
pci_release_regions(pdev); |
535 |
pci_release_regions(pdev); |