|
Lines 156-162
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|
| 156 |
OPTION_NORADEONXINERAMA, |
156 |
OPTION_NORADEONXINERAMA, |
| 157 |
OPTION_CRT2ISSCRN0, |
157 |
OPTION_CRT2ISSCRN0, |
| 158 |
OPTION_DISP_PRIORITY, |
158 |
OPTION_DISP_PRIORITY, |
| 159 |
OPTION_PANEL_SIZE |
159 |
OPTION_PANEL_SIZE, |
|
|
160 |
OPTION_FWPLL |
| 160 |
} RADEONOpts; |
161 |
} RADEONOpts; |
| 161 |
|
162 |
|
| 162 |
const OptionInfoRec RADEONOptions[] = { |
163 |
const OptionInfoRec RADEONOptions[] = { |
|
Lines 197-202
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|
| 197 |
{ OPTION_CRT2ISSCRN0, "MergedXineramaCRT2IsScreen0", OPTV_BOOLEAN, {0}, FALSE }, |
198 |
{ OPTION_CRT2ISSCRN0, "MergedXineramaCRT2IsScreen0", OPTV_BOOLEAN, {0}, FALSE }, |
| 198 |
{ OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, |
199 |
{ OPTION_DISP_PRIORITY, "DisplayPriority", OPTV_ANYSTR, {0}, FALSE }, |
| 199 |
{ OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, |
200 |
{ OPTION_PANEL_SIZE, "PanelSize", OPTV_ANYSTR, {0}, FALSE }, |
|
|
201 |
{ OPTION_FWPLL, "UseFWPLL", OPTV_BOOLEAN, {0}, FALSE }, |
| 200 |
{ -1, NULL, OPTV_NONE, {0}, FALSE } |
202 |
{ -1, NULL, OPTV_NONE, {0}, FALSE } |
| 201 |
}; |
203 |
}; |
| 202 |
|
204 |
|
|
Lines 1892-1897
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|
| 1892 |
pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); |
1894 |
pll->xclk = RADEON_BIOS16(pll_info_block + 0x08); |
| 1893 |
} |
1895 |
} |
| 1894 |
|
1896 |
|
|
|
1897 |
if (xf86ReturnOptValBool(info->Options, OPTION_FWPLL, FALSE)) |
| 1898 |
pll->reference_div = INPLL(pScrn, RADEON_PPLL_REF_DIV); |
| 1899 |
|
| 1900 |
|
| 1895 |
return TRUE; |
1901 |
return TRUE; |
| 1896 |
} |
1902 |
} |
| 1897 |
|
1903 |
|
|
Lines 6551-6560
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|
| 6551 |
} |
6557 |
} |
| 6552 |
|
6558 |
|
| 6553 |
/* Define PLL registers for requested video mode */ |
6559 |
/* Define PLL registers for requested video mode */ |
| 6554 |
static void RADEONInitPLLRegisters(RADEONSavePtr save, RADEONPLLPtr pll, |
6560 |
static void RADEONInitPLLRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save, RADEONPLLPtr pll, |
| 6555 |
double dot_clock) |
6561 |
double dot_clock) |
| 6556 |
{ |
6562 |
{ |
| 6557 |
unsigned long freq = dot_clock * 100; |
6563 |
unsigned long freq = dot_clock * 100; |
|
|
6564 |
RADEONInfoPtr info = RADEONPTR(pScrn); |
| 6558 |
|
6565 |
|
| 6559 |
struct { |
6566 |
struct { |
| 6560 |
int divider; |
6567 |
int divider; |
|
Lines 6598-6604
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|
| 6598 |
save->post_div = post_div->divider; |
6605 |
save->post_div = post_div->divider; |
| 6599 |
|
6606 |
|
| 6600 |
save->ppll_ref_div = pll->reference_div; |
6607 |
save->ppll_ref_div = pll->reference_div; |
| 6601 |
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); |
6608 |
|
|
|
6609 |
if (xf86ReturnOptValBool(info->Options, OPTION_FWPLL, FALSE)) |
| 6610 |
save->ppll_div_3 = INPLL(pScrn, RADEON_PPLL_DIV_3); |
| 6611 |
else |
| 6612 |
save->ppll_div_3 = (save->feedback_div | (post_div->bitvalue << 16)); |
| 6613 |
|
| 6602 |
save->htotal_cntl = 0; |
6614 |
save->htotal_cntl = 0; |
| 6603 |
} |
6615 |
} |
| 6604 |
|
6616 |
|
|
Lines 6733-6739
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|
| 6733 |
return FALSE; |
6745 |
return FALSE; |
| 6734 |
dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0; |
6746 |
dot_clock = (((RADEONMergedDisplayModePtr)mode->Private)->CRT1)->Clock / 1000.0; |
| 6735 |
if (dot_clock) { |
6747 |
if (dot_clock) { |
| 6736 |
RADEONInitPLLRegisters(save, &info->pll, dot_clock); |
6748 |
RADEONInitPLLRegisters(pScrn, save, &info->pll, dot_clock); |
| 6737 |
} else { |
6749 |
} else { |
| 6738 |
save->ppll_ref_div = info->SavedReg.ppll_ref_div; |
6750 |
save->ppll_ref_div = info->SavedReg.ppll_ref_div; |
| 6739 |
save->ppll_div_3 = info->SavedReg.ppll_div_3; |
6751 |
save->ppll_div_3 = info->SavedReg.ppll_div_3; |
|
Lines 6754-6760
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|
| 6754 |
save->htotal_cntl = 0; |
6766 |
save->htotal_cntl = 0; |
| 6755 |
} |
6767 |
} |
| 6756 |
else |
6768 |
else |
| 6757 |
RADEONInitPLLRegisters(save, &info->pll, dot_clock); |
6769 |
RADEONInitPLLRegisters(pScrn, save, &info->pll, dot_clock); |
| 6758 |
} else { |
6770 |
} else { |
| 6759 |
save->ppll_ref_div = info->SavedReg.ppll_ref_div; |
6771 |
save->ppll_ref_div = info->SavedReg.ppll_ref_div; |
| 6760 |
save->ppll_div_3 = info->SavedReg.ppll_div_3; |
6772 |
save->ppll_div_3 = info->SavedReg.ppll_div_3; |
