Attachment #397058 for bug #539950

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2015-02-20  Uros Bizjak  <ubizjak@gmail.com>

	Backport from mainline
	2013-09-08  Richard Sandiford  <rdsandiford@googlemail.com>

	* ira.c (update_equiv_regs): Only call set_paradoxical_subreg
	for non-debug insns.
	* lra.c (new_insn_reg): Take the containing insn as a parameter.
	Only modify lra_reg_info[].biggest_mode if it's non-debug insn.
	(collect_non_operand_hard_regs, add_regs_to_insn_regno_info): Update
	accordingly.

2015-02-17  Ilya Tocar  <ilya.tocar@intel.com>

	Backported from mainline

	Backport from mainline
	2015-01-31  Uros Bizjak  <ubizjak@gmail.com>

	PR target/64882
	* config/i386/predicates.md (address_no_seg_operand): Reject
	non-CONST_INT_P operands in invalid mode.


2014-12-10  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	Backport from mainline
	2014-09-02  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE):  New
	built-in definition.

	(vec_mul): Likewise.

	Backport from mainline
	2014-08-28  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.h (vec_xl): New #define.
	(vec_xst): Likewise.

	(vsx_xxspltd_<mode>): New insn.

	Backport from mainline
	2014-08-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.h (vec_cpsgn): New #define.
	(vec_mergee): Likewise.

	vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz.

	Backport from mainline
	2014-07-20  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

	* config/rs6000/altivec.md (unspec enum):  Fix typo in UNSPEC_VSLDOI.
	(altivec_vsldoi_<mode>): Likewise.

	for immediate.

	2014-11-19  Felix Yang  <felix.yang@huawei.com>
		    Shanyao Chen  <chenshanyao@huawei.com>

	PR target/59593
	* config/arm/arm.md (define_attr "arch"): Add v6t2.

	Backport from mainline

	2014-06-20  Julian Brown  <julian@codesourcery.com>
		    Chung-Lin Tang  <cltang@codesourcery.com>

	* config/arm/arm.c (arm_output_mi_thunk): Fix offset for
	TARGET_THUMB1_ONLY. Add comments.

Lines 2944-2954 update_equiv_regs (void) Link Here

(-)a/gcc/ira.c (-5 / +2 lines)
2944	prevent access beyond allocated memory for paradoxical memory subreg. */	2944	prevent access beyond allocated memory for paradoxical memory subreg. */
2945	FOR_EACH_BB (bb)	2945	FOR_EACH_BB (bb)
2946	FOR_BB_INSNS (bb, insn)	2946	FOR_BB_INSNS (bb, insn)
2947	{	2947	if (NONDEBUG_INSN_P (insn))
2948	if (! INSN_P (insn))	2948	for_each_rtx (&insn, set_paradoxical_subreg, (void *) pdx_subregs);
2949	continue;
2950	for_each_rtx (&insn, set_paradoxical_subreg, (void *)pdx_subregs);
2951	}
2952		2949
2953	/* Scan the insns and find which registers have equivalences. Do this	2950	/* Scan the insns and find which registers have equivalences. Do this
2954	in a separate scan of the insns because (due to -fcse-follow-jumps)	2951	in a separate scan of the insns because (due to -fcse-follow-jumps)




    = create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg), 100);
}

/* Create LRA insn related info about a reference to REGNO in INSN with
   TYPE (in/out/inout), biggest reference mode MODE, flag that it is
   reference through subreg (SUBREG_P), flag that is early clobbered
   in the insn (EARLY_CLOBBER), and reference to the next insn reg
   info (NEXT).	 */
static struct lra_insn_reg *
new_insn_reg (rtx insn, int regno, enum op_type type, enum machine_mode mode,
	      bool subreg_p, bool early_clobber, struct lra_insn_reg *next)
{
  struct lra_insn_reg *ir;

  ir = (struct lra_insn_reg *) pool_alloc (insn_reg_pool);
  ir->type = type;
  ir->biggest_mode = mode;
  if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode)
      && NONDEBUG_INSN_P (insn))
    lra_reg_info[regno].biggest_mode = mode;
  ir->subreg_p = subreg_p;
  ir->early_clobber = early_clobber;

		     && ! (FIRST_STACK_REG <= regno
			   && regno <= LAST_STACK_REG));
#endif
		list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
				     early_clobber, list);
	      }
	  }

      expand_reg_info ();
      if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid))
	{
	  data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
				     early_clobber, data->regs);
	  return;
	}

		if (curr->subreg_p != subreg_p || curr->biggest_mode != mode)
		  /* The info can not be integrated into the found
		     structure.  */
		  data->regs = new_insn_reg (data->insn, regno, type, mode,
					     subreg_p, early_clobber,
					     data->regs);
		else
		  {
		    if (curr->type != type)




2015-02-20  Uros Bizjak  <ubizjak@gmail.com>

	Backport from mainline
	2013-09-08  Richard Sandiford  <rdsandiford@googlemail.com>

	* g++.dg/debug/ra1.C: New test.

2015-02-17  Sandra Loosemore  <sandra@codesourcery.com>

	Backported from mainline

	Backport from mainline
	2015-01-31  Uros Bizjak  <ubizjak@gmail.com>

	PR target/64882
	* gcc.dg/torture/pr64882.c: New test.

2015-02-01  Jakub Jelinek  <jakub@redhat.com>




/* { dg-options "-fcompare-debug" } */

enum signop { SIGNED, UNSIGNED };
enum tree_code { FOO, BAR };
enum tree_code_class { tcc_type, tcc_other };
extern enum tree_code_class tree_code_type[];

struct tree_base {
  enum tree_code code : 16;
  unsigned unsigned_flag : 1;
};

struct tree_def {
  tree_base base;
  struct {
    int precision;
  } type_common;
};

typedef tree_def *tree;

struct storage_ref
{
  storage_ref (const long *, unsigned int, unsigned int);

  const long *val;
  unsigned int len;
  unsigned int precision;
};

inline storage_ref::storage_ref (const long *val_in,
				 unsigned int len_in,
				 unsigned int precision_in)
  : val (val_in), len (len_in), precision (precision_in)
{
}

struct hwi_with_prec
{
  long val;
  unsigned int precision;
  signop sgn;
};

inline storage_ref
decompose (long *scratch, unsigned int precision,
	   const hwi_with_prec &x)
{
  scratch[0] = x.val;
  if (x.sgn == SIGNED || x.val >= 0 || precision <= sizeof (long) * 8)
    return storage_ref (scratch, 1, precision);
  scratch[1] = 0;
  return storage_ref (scratch, 2, precision);
}

extern void tree_class_check_failed (int) __attribute__ ((__noreturn__));

inline tree
tree_class_check (tree t, const enum tree_code_class cls, int x)
{
  if (tree_code_type[t->base.code] != cls)
    tree_class_check_failed (x);
  return t;
}

tree wide_int_to_tree (tree, const storage_ref &);

tree
build_int_cstu (tree type, unsigned long val)
{
  hwi_with_prec x;
  x.val = val;
  x.precision = tree_class_check (type, tcc_type, 1)->type_common.precision;
  x.sgn = (signop) tree_class_check (type, tcc_type, 2)->base.unsigned_flag;
  long scratch[2];
  return wide_int_to_tree (type, decompose (scratch, x.precision, x));
}

Return to bug 539950

Lines 446-458 init_insn_regs (void) Link Here

(-)a/gcc/lra.c (-8 / +10 lines)
446	= create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg), 100);	446	= create_alloc_pool ("insn regs", sizeof (struct lra_insn_reg), 100);
447	}	447	}
448		448
449	/* Create LRA insn related info about referenced REGNO with TYPE	449	/* Create LRA insn related info about a reference to REGNO in INSN with
450	(in/out/inout), biggest reference mode MODE, flag that it is	450	TYPE (in/out/inout), biggest reference mode MODE, flag that it is
451	reference through subreg (SUBREG_P), flag that is early clobbered	451	reference through subreg (SUBREG_P), flag that is early clobbered
452	in the insn (EARLY_CLOBBER), and reference to the next insn reg	452	in the insn (EARLY_CLOBBER), and reference to the next insn reg
453	info (NEXT). */	453	info (NEXT). */
454	static struct lra_insn_reg *	454	static struct lra_insn_reg *
455	new_insn_reg (int regno, enum op_type type, enum machine_mode mode,	455	new_insn_reg (rtx insn, int regno, enum op_type type, enum machine_mode mode,
456	bool subreg_p, bool early_clobber, struct lra_insn_reg *next)	456	bool subreg_p, bool early_clobber, struct lra_insn_reg *next)
457	{	457	{
458	struct lra_insn_reg *ir;	458	struct lra_insn_reg *ir;
Lines 460-466 new_insn_reg (int regno, enum op_type type, enum machine_mode mode, Link Here
460	ir = (struct lra_insn_reg *) pool_alloc (insn_reg_pool);	460	ir = (struct lra_insn_reg *) pool_alloc (insn_reg_pool);
461	ir->type = type;	461	ir->type = type;
462	ir->biggest_mode = mode;	462	ir->biggest_mode = mode;
463	if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode))	463	if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (lra_reg_info[regno].biggest_mode)
		464	&& NONDEBUG_INSN_P (insn))
464	lra_reg_info[regno].biggest_mode = mode;	465	lra_reg_info[regno].biggest_mode = mode;
465	ir->subreg_p = subreg_p;	466	ir->subreg_p = subreg_p;
466	ir->early_clobber = early_clobber;	467	ir->early_clobber = early_clobber;
Lines 942-948 collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, Link Here
942	&& ! (FIRST_STACK_REG <= regno	943	&& ! (FIRST_STACK_REG <= regno
943	&& regno <= LAST_STACK_REG));	944	&& regno <= LAST_STACK_REG));
944	#endif	945	#endif
945	list = new_insn_reg (regno, type, mode, subreg_p,	946	list = new_insn_reg (data->insn, regno, type, mode, subreg_p,
946	early_clobber, list);	947	early_clobber, list);
947	}	948	}
948	}	949	}
Lines 1540-1546 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, Link Here
1540	expand_reg_info ();	1541	expand_reg_info ();
1541	if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid))	1542	if (bitmap_set_bit (&lra_reg_info[regno].insn_bitmap, uid))
1542	{	1543	{
1543	data->regs = new_insn_reg (regno, type, mode, subreg_p,	1544	data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p,
1544	early_clobber, data->regs);	1545	early_clobber, data->regs);
1545	return;	1546	return;
1546	}	1547	}
Lines 1552-1559 add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, Link Here
1552	if (curr->subreg_p != subreg_p \|\| curr->biggest_mode != mode)	1553	if (curr->subreg_p != subreg_p \|\| curr->biggest_mode != mode)
1553	/* The info can not be integrated into the found	1554	/* The info can not be integrated into the found
1554	structure. */	1555	structure. */
1555	data->regs = new_insn_reg (regno, type, mode, subreg_p,	1556	data->regs = new_insn_reg (data->insn, regno, type, mode,
1556	early_clobber, data->regs);	1557	subreg_p, early_clobber,
		1558	data->regs);
1557	else	1559	else
1558	{	1560	{
1559	if (curr->type != type)	1561	if (curr->type != type)

Lines 1-3 Link Here

(-)a/gcc/ChangeLog (-7 / +19 lines)
		1	2015-02-20 Uros Bizjak <ubizjak@gmail.com>
		2
		3	Backport from mainline
		4	2013-09-08 Richard Sandiford <rdsandiford@googlemail.com>
		5
		6	* ira.c (update_equiv_regs): Only call set_paradoxical_subreg
		7	for non-debug insns.
		8	* lra.c (new_insn_reg): Take the containing insn as a parameter.
		9	Only modify lra_reg_info[].biggest_mode if it's non-debug insn.
		10	(collect_non_operand_hard_regs, add_regs_to_insn_regno_info): Update
		11	accordingly.
		12
1	2015-02-17 Ilya Tocar <ilya.tocar@intel.com>	13	2015-02-17 Ilya Tocar <ilya.tocar@intel.com>
2		14
3	Backported from mainline	15	Backported from mainline
Lines 35-41 Link Here
35	Backport from mainline	47	Backport from mainline
36	2015-01-31 Uros Bizjak <ubizjak@gmail.com>	48	2015-01-31 Uros Bizjak <ubizjak@gmail.com>
37		49
38	PR target/64882	50	PR target/64882
39	* config/i386/predicates.md (address_no_seg_operand): Reject	51	* config/i386/predicates.md (address_no_seg_operand): Reject
40	non-CONST_INT_P operands in invalid mode.	52	non-CONST_INT_P operands in invalid mode.
41		53
Lines 218-224 Link Here
218	2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>	230	2014-12-10 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
219		231
220	Backport from mainline	232	Backport from mainline
221	2014-09-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>	233	2014-09-02 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
222		234
223	* config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE): New	235	* config/rs6000/rs6000-builtin.def (XVCVSXDDP_SCALE): New
224	built-in definition.	236	built-in definition.
Lines 253-259 Link Here
253	(vec_mul): Likewise.	265	(vec_mul): Likewise.
254		266
255	Backport from mainline	267	Backport from mainline
256	2014-08-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com>	268	2014-08-28 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
257		269
258	* config/rs6000/altivec.h (vec_xl): New #define.	270	* config/rs6000/altivec.h (vec_xl): New #define.
259	(vec_xst): Likewise.	271	(vec_xst): Likewise.
Lines 276-282 Link Here
276	(vsx_xxspltd_<mode>): New insn.	288	(vsx_xxspltd_<mode>): New insn.
277		289
278	Backport from mainline	290	Backport from mainline
279	2014-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>	291	2014-08-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
280		292
281	* config/rs6000/altivec.h (vec_cpsgn): New #define.	293	* config/rs6000/altivec.h (vec_cpsgn): New #define.
282	(vec_mergee): Likewise.	294	(vec_mergee): Likewise.
Lines 294-300 Link Here
294	vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz.	306	vec_any_ne, vec_mergee, vec_mergeo, vec_packsu, and vec_cntlz.
295		307
296	Backport from mainline	308	Backport from mainline
297	2014-07-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>	309	2014-07-20 Bill Schmidt <wschmidt@linux.vnet.ibm.com>
298		310
299	* config/rs6000/altivec.md (unspec enum): Fix typo in UNSPEC_VSLDOI.	311	* config/rs6000/altivec.md (unspec enum): Fix typo in UNSPEC_VSLDOI.
300	(altivec_vsldoi_<mode>): Likewise.	312	(altivec_vsldoi_<mode>): Likewise.
Lines 378-384 Link Here
378	for immediate.	390	for immediate.
379		391
380	2014-11-19 Felix Yang <felix.yang@huawei.com>	392	2014-11-19 Felix Yang <felix.yang@huawei.com>
381	Shanyao Chen <chenshanyao@huawei.com>	393	Shanyao Chen <chenshanyao@huawei.com>
382		394
383	PR target/59593	395	PR target/59593
384	* config/arm/arm.md (define_attr "arch"): Add v6t2.	396	* config/arm/arm.md (define_attr "arch"): Add v6t2.
Lines 1286-1292 Link Here
1286	Backport from mainline	1298	Backport from mainline
1287		1299
1288	2014-06-20 Julian Brown <julian@codesourcery.com>	1300	2014-06-20 Julian Brown <julian@codesourcery.com>
1289	Chung-Lin Tang <cltang@codesourcery.com>	1301	Chung-Lin Tang <cltang@codesourcery.com>
1290		1302
1291	* config/arm/arm.c (arm_output_mi_thunk): Fix offset for	1303	* config/arm/arm.c (arm_output_mi_thunk): Fix offset for
1292	TARGET_THUMB1_ONLY. Add comments.	1304	TARGET_THUMB1_ONLY. Add comments.

Lines 1-3 Link Here

(-)a/gcc/testsuite/ChangeLog (-1 / +8 lines)
		1	2015-02-20 Uros Bizjak <ubizjak@gmail.com>
		2
		3	Backport from mainline
		4	2013-09-08 Richard Sandiford <rdsandiford@googlemail.com>
		5
		6	* g++.dg/debug/ra1.C: New test.
		7
1	2015-02-17 Sandra Loosemore <sandra@codesourcery.com>	8	2015-02-17 Sandra Loosemore <sandra@codesourcery.com>
2		9
3	Backported from mainline	10	Backported from mainline
Lines 43-49 Link Here
43	Backport from mainline	50	Backport from mainline
44	2015-01-31 Uros Bizjak <ubizjak@gmail.com>	51	2015-01-31 Uros Bizjak <ubizjak@gmail.com>
45		52
46	PR target/64882	53	PR target/64882
47	* gcc.dg/torture/pr64882.c: New test.	54	* gcc.dg/torture/pr64882.c: New test.
48		55
49	2015-02-01 Jakub Jelinek <jakub@redhat.com>	56	2015-02-01 Jakub Jelinek <jakub@redhat.com>

Line 0 Link Here

(-)a/gcc/testsuite/g++.dg/debug/ra1.C (-1 / +77 lines)
0	-	1	/* { dg-options "-fcompare-debug" } */
		2
		3	enum signop { SIGNED, UNSIGNED };
		4	enum tree_code { FOO, BAR };
		5	enum tree_code_class { tcc_type, tcc_other };
		6	extern enum tree_code_class tree_code_type[];
		7
		8	struct tree_base {
		9	enum tree_code code : 16;
		10	unsigned unsigned_flag : 1;
		11	};
		12
		13	struct tree_def {
		14	tree_base base;
		15	struct {
		16	int precision;
		17	} type_common;
		18	};
		19
		20	typedef tree_def *tree;
		21
		22	struct storage_ref
		23	{
		24	storage_ref (const long *, unsigned int, unsigned int);
		25
		26	const long *val;
		27	unsigned int len;
		28	unsigned int precision;
		29	};
		30
		31	inline storage_ref::storage_ref (const long *val_in,
		32	unsigned int len_in,
		33	unsigned int precision_in)
		34	: val (val_in), len (len_in), precision (precision_in)
		35	{
		36	}
		37
		38	struct hwi_with_prec
		39	{
		40	long val;
		41	unsigned int precision;
		42	signop sgn;
		43	};
		44
		45	inline storage_ref
		46	decompose (long *scratch, unsigned int precision,
		47	const hwi_with_prec &x)
		48	{
		49	scratch[0] = x.val;
		50	if (x.sgn == SIGNED \|\| x.val >= 0 \|\| precision <= sizeof (long) * 8)
		51	return storage_ref (scratch, 1, precision);
		52	scratch[1] = 0;
		53	return storage_ref (scratch, 2, precision);
		54	}
		55
		56	extern void tree_class_check_failed (int) __attribute__ ((__noreturn__));
		57
		58	inline tree
		59	tree_class_check (tree t, const enum tree_code_class cls, int x)
		60	{
		61	if (tree_code_type[t->base.code] != cls)
		62	tree_class_check_failed (x);
		63	return t;
		64	}
		65
66	tree wide_int_to_tree (tree, const storage_ref &);
67
68	tree
69	build_int_cstu (tree type, unsigned long val)
70	{
71	hwi_with_prec x;
72	x.val = val;
73	x.precision = tree_class_check (type, tcc_type, 1)->type_common.precision;
74	x.sgn = (signop) tree_class_check (type, tcc_type, 2)->base.unsigned_flag;
75	long scratch[2];
76	return wide_int_to_tree (type, decompose (scratch, x.precision, x));
77	}