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Lines 12867-12873
mips_process_sync_loop (rtx insn, rtx *o
Link Here
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| 12867 |
This will sometimes be a delayed branch; see the write code below |
12867 |
This will sometimes be a delayed branch; see the write code below |
| 12868 |
for details. */ |
12868 |
for details. */ |
| 12869 |
mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); |
12869 |
mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); |
| 12870 |
mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); |
12870 |
|
|
|
12871 |
/* When using branch likely (-mfix-r10000), the delay slot instruction |
| 12872 |
will be annulled on false. The normal delay slot instructions |
| 12873 |
calculate the overall result of the atomic operation and must not |
| 12874 |
be annulled. To ensure this behaviour unconditionally use a NOP |
| 12875 |
in the delay slot for the branch likely case. */ |
| 12876 |
|
| 12877 |
mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at, NULL); |
| 12871 |
|
12878 |
|
| 12872 |
/* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ |
12879 |
/* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ |
| 12873 |
if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) |
12880 |
if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) |
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Lines 12875-12881
mips_process_sync_loop (rtx insn, rtx *o
Link Here
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| 12875 |
mips_multi_copy_insn (tmp3_insn); |
12882 |
mips_multi_copy_insn (tmp3_insn); |
| 12876 |
mips_multi_set_operand (mips_multi_last_index (), 0, newval); |
12883 |
mips_multi_set_operand (mips_multi_last_index (), 0, newval); |
| 12877 |
} |
12884 |
} |
| 12878 |
else if (!(required_oldval && cmp)) |
12885 |
else if (!(required_oldval && cmp) && !mips_branch_likely) |
| 12879 |
mips_multi_add_insn ("nop", NULL); |
12886 |
mips_multi_add_insn ("nop", NULL); |
| 12880 |
|
12887 |
|
| 12881 |
/* CMP = 1 -- either standalone or in a delay slot. */ |
12888 |
/* CMP = 1 -- either standalone or in a delay slot. */ |
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Lines 12899-12910
mips_process_sync_loop (rtx insn, rtx *o
Link Here
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| 12899 |
const char * |
12906 |
const char * |
| 12900 |
mips_output_sync_loop (rtx insn, rtx *operands) |
12907 |
mips_output_sync_loop (rtx insn, rtx *operands) |
| 12901 |
{ |
12908 |
{ |
| 12902 |
mips_process_sync_loop (insn, operands); |
|
|
| 12903 |
|
| 12904 |
/* Use branch-likely instructions to work around the LL/SC R10000 |
12909 |
/* Use branch-likely instructions to work around the LL/SC R10000 |
| 12905 |
errata. */ |
12910 |
errata. */ |
| 12906 |
mips_branch_likely = TARGET_FIX_R10000; |
12911 |
mips_branch_likely = TARGET_FIX_R10000; |
| 12907 |
|
12912 |
|
|
|
12913 |
mips_process_sync_loop (insn, operands); |
| 12914 |
|
| 12908 |
mips_push_asm_switch (&mips_noreorder); |
12915 |
mips_push_asm_switch (&mips_noreorder); |
| 12909 |
mips_push_asm_switch (&mips_nomacro); |
12916 |
mips_push_asm_switch (&mips_nomacro); |
| 12910 |
mips_push_asm_switch (&mips_noat); |
12917 |
mips_push_asm_switch (&mips_noat); |
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Lines 12926-12931
mips_output_sync_loop (rtx insn, rtx *op
Link Here
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| 12926 |
unsigned int |
12933 |
unsigned int |
| 12927 |
mips_sync_loop_insns (rtx insn, rtx *operands) |
12934 |
mips_sync_loop_insns (rtx insn, rtx *operands) |
| 12928 |
{ |
12935 |
{ |
|
|
12936 |
/* Use branch-likely instructions to work around the LL/SC R10000 |
| 12937 |
errata. */ |
| 12938 |
mips_branch_likely = TARGET_FIX_R10000; |
| 12929 |
mips_process_sync_loop (insn, operands); |
12939 |
mips_process_sync_loop (insn, operands); |
| 12930 |
return mips_multi_num_insns; |
12940 |
return mips_multi_num_insns; |
| 12931 |
} |
12941 |
} |
