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Lines 12469-12475
mips_process_sync_loop (rtx insn, rtx *o
Link Here
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| 12469 |
This will sometimes be a delayed branch; see the write code below |
12469 |
This will sometimes be a delayed branch; see the write code below |
| 12470 |
for details. */ |
12470 |
for details. */ |
| 12471 |
mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); |
12471 |
mips_multi_add_insn (is_64bit_p ? "scd\t%0,%1" : "sc\t%0,%1", at, mem, NULL); |
| 12472 |
mips_multi_add_insn ("beq%?\t%0,%.,1b", at, NULL); |
12472 |
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|
|
12473 |
/* When using branch likely (-mfix-r10000), the delay slot instruction |
| 12474 |
will be annulled on false. The normal delay slot instructions |
| 12475 |
calculate the overall result of the atomic operation and must not |
| 12476 |
be annulled. To ensure this behaviour unconditionally use a NOP |
| 12477 |
in the delay slot for the branch likely case. */ |
| 12478 |
|
| 12479 |
mips_multi_add_insn ("beq%?\t%0,%.,1b%~", at, NULL); |
| 12473 |
|
12480 |
|
| 12474 |
/* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ |
12481 |
/* if (INSN1 != MOVE && INSN1 != LI) NEWVAL = $TMP3 [delay slot]. */ |
| 12475 |
if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) |
12482 |
if (insn1 != SYNC_INSN1_MOVE && insn1 != SYNC_INSN1_LI && tmp3 != newval) |
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Lines 12477-12483
mips_process_sync_loop (rtx insn, rtx *o
Link Here
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| 12477 |
mips_multi_copy_insn (tmp3_insn); |
12484 |
mips_multi_copy_insn (tmp3_insn); |
| 12478 |
mips_multi_set_operand (mips_multi_last_index (), 0, newval); |
12485 |
mips_multi_set_operand (mips_multi_last_index (), 0, newval); |
| 12479 |
} |
12486 |
} |
| 12480 |
else if (!(required_oldval && cmp)) |
12487 |
else if (!(required_oldval && cmp) && !mips_branch_likely) |
| 12481 |
mips_multi_add_insn ("nop", NULL); |
12488 |
mips_multi_add_insn ("nop", NULL); |
| 12482 |
|
12489 |
|
| 12483 |
/* CMP = 1 -- either standalone or in a delay slot. */ |
12490 |
/* CMP = 1 -- either standalone or in a delay slot. */ |
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Lines 12501-12512
mips_process_sync_loop (rtx insn, rtx *o
Link Here
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| 12501 |
const char * |
12508 |
const char * |
| 12502 |
mips_output_sync_loop (rtx insn, rtx *operands) |
12509 |
mips_output_sync_loop (rtx insn, rtx *operands) |
| 12503 |
{ |
12510 |
{ |
| 12504 |
mips_process_sync_loop (insn, operands); |
|
|
| 12505 |
|
| 12506 |
/* Use branch-likely instructions to work around the LL/SC R10000 |
12511 |
/* Use branch-likely instructions to work around the LL/SC R10000 |
| 12507 |
errata. */ |
12512 |
errata. */ |
| 12508 |
mips_branch_likely = TARGET_FIX_R10000; |
12513 |
mips_branch_likely = TARGET_FIX_R10000; |
| 12509 |
|
12514 |
|
|
|
12515 |
mips_process_sync_loop (insn, operands); |
| 12516 |
|
| 12510 |
mips_push_asm_switch (&mips_noreorder); |
12517 |
mips_push_asm_switch (&mips_noreorder); |
| 12511 |
mips_push_asm_switch (&mips_nomacro); |
12518 |
mips_push_asm_switch (&mips_nomacro); |
| 12512 |
mips_push_asm_switch (&mips_noat); |
12519 |
mips_push_asm_switch (&mips_noat); |
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Lines 12528-12533
mips_output_sync_loop (rtx insn, rtx *op
Link Here
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| 12528 |
unsigned int |
12535 |
unsigned int |
| 12529 |
mips_sync_loop_insns (rtx insn, rtx *operands) |
12536 |
mips_sync_loop_insns (rtx insn, rtx *operands) |
| 12530 |
{ |
12537 |
{ |
|
|
12538 |
/* Use branch-likely instructions to work around the LL/SC R10000 |
| 12539 |
errata. */ |
| 12540 |
mips_branch_likely = TARGET_FIX_R10000; |
| 12531 |
mips_process_sync_loop (insn, operands); |
12541 |
mips_process_sync_loop (insn, operands); |
| 12532 |
return mips_multi_num_insns; |
12542 |
return mips_multi_num_insns; |
| 12533 |
} |
12543 |
} |
