Attachment #390840 for bug #531528






static void
get_common_indeces (unsigned int *family, unsigned int *model, unsigned int *stepping)
{
  __cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
	   __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,

  unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
  *family = (eax >> 8) & 0x0f;
  *model = (eax >> 4) & 0x0f;
  *stepping = eax & 0x0f;
}



  unsigned int edx;
  unsigned int family = 0;
  unsigned int model = 0;
  unsigned int stepping = 0;
  enum cpu_features_kind kind;

  __cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);

    {
      kind = arch_kind_intel;

      get_common_indeces (&family, &model, &stepping);

      unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
      unsigned int extended_family = (eax >> 20) & 0xff;

    {
      kind = arch_kind_amd;

      get_common_indeces (&family, &model, &stepping);

      ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;


	}
    }

  /* Disable Intel TSX (HLE and RTM) due to erratum HSD136/HSW136
     on Haswell processors, to work around outdated microcode that
     doesn't disable the broken feature by default */
  if (kind == arch_kind_intel && family == 6 &&
      ((model == 63 && stepping <= 2) || (model == 60 && stepping <= 3) ||
       (model == 69 && stepping <= 1) || (model == 70 && stepping <= 1)))
    __cpu_features.cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM | bit_HLE);

  __cpu_features.family = family;
  __cpu_features.model = model;
  atomic_write_barrier ();

Lines 41-46 Link Here

(-)a/sysdeps/x86_64/multiarch/init-arch.h (+1 lines)
41		41
42	/* COMMON_CPUID_INDEX_7. */	42	/* COMMON_CPUID_INDEX_7. */
43	#define bit_RTM (1 << 11)	43	#define bit_RTM (1 << 11)
		44	#define bit_HLE (1 << 4)
44	#define bit_AVX2 (1 << 5)	45	#define bit_AVX2 (1 << 5)
45		46
46	/* XCR0 Feature flags. */	47	/* XCR0 Feature flags. */

Return to bug 531528

Lines 26-32 Link Here

(-)a/sysdeps/x86_64/multiarch/init-arch.c (-3 / +13 lines)
26		26
27		27
28	static void	28	static void
29	get_common_indeces (unsigned int family, unsigned int model)	29	get_common_indeces (unsigned int family, unsigned int model, unsigned int *stepping)
30	{	30	{
31	__cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,	31	__cpuid (1, __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax,
32	__cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,	32	__cpu_features.cpuid[COMMON_CPUID_INDEX_1].ebx,
Lines 36-41 Link Here
36	unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;	36	unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
37	*family = (eax >> 8) & 0x0f;	37	*family = (eax >> 8) & 0x0f;
38	*model = (eax >> 4) & 0x0f;	38	*model = (eax >> 4) & 0x0f;
		39	*stepping = eax & 0x0f;
39	}	40	}
40		41
41		42
Lines 47-52 Link Here
47	unsigned int edx;	48	unsigned int edx;
48	unsigned int family = 0;	49	unsigned int family = 0;
49	unsigned int model = 0;	50	unsigned int model = 0;
		51	unsigned int stepping = 0;
50	enum cpu_features_kind kind;	52	enum cpu_features_kind kind;
51		53
52	__cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);	54	__cpuid (0, __cpu_features.max_cpuid, ebx, ecx, edx);
Lines 56-62 Link Here
56	{	58	{
57	kind = arch_kind_intel;	59	kind = arch_kind_intel;
58		60
59	get_common_indeces (&family, &model);	61	get_common_indeces (&family, &model, &stepping);
60		62
61	unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;	63	unsigned int eax = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].eax;
62	unsigned int extended_family = (eax >> 20) & 0xff;	64	unsigned int extended_family = (eax >> 20) & 0xff;
Lines 131-137 Link Here
131	{	133	{
132	kind = arch_kind_amd;	134	kind = arch_kind_amd;
133		135
134	get_common_indeces (&family, &model);	136	get_common_indeces (&family, &model, &stepping);
135		137
136	ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;	138	ecx = __cpu_features.cpuid[COMMON_CPUID_INDEX_1].ecx;
137		139
Lines 179-184 Link Here
179	}	181	}
180	}	182	}
181		183
		184	/* Disable Intel TSX (HLE and RTM) due to erratum HSD136/HSW136
		185	on Haswell processors, to work around outdated microcode that
		186	doesn't disable the broken feature by default */
		187	if (kind == arch_kind_intel && family == 6 &&
		188	((model == 63 && stepping <= 2) \|\| (model == 60 && stepping <= 3) \|\|
		189	(model == 69 && stepping <= 1) \|\| (model == 70 && stepping <= 1)))
		190	__cpu_features.cpuid[COMMON_CPUID_INDEX_7].ebx &= ~(bit_RTM \| bit_HLE);
		191
182	__cpu_features.family = family;	192	__cpu_features.family = family;
183	__cpu_features.model = model;	193	__cpu_features.model = model;
184	atomic_write_barrier ();	194	atomic_write_barrier ();