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Lines 57-62
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| 57 |
ich5_pata = 0, |
57 |
ich5_pata = 0, |
| 58 |
ich5_sata = 1, |
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ich5_sata = 1, |
| 59 |
piix4_pata = 2, |
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piix4_pata = 2, |
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60 |
ich6_sata = 3, |
| 60 |
}; |
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}; |
| 61 |
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62 |
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| 62 |
static int piix_init_one (struct pci_dev *pdev, |
63 |
static int piix_init_one (struct pci_dev *pdev, |
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Lines 91-100
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| 91 |
* and enhanced mode, with queueing and other fancy stuff. |
92 |
* and enhanced mode, with queueing and other fancy stuff. |
| 92 |
* This is distinguished by PCI class code. |
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* This is distinguished by PCI class code. |
| 93 |
*/ |
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*/ |
| 94 |
{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, |
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{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
| 95 |
PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata }, |
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{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
| 96 |
{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, |
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| 97 |
PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich5_sata }, |
| 98 |
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97 |
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| 99 |
{ } /* terminate list */ |
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{ } /* terminate list */ |
| 100 |
}; |
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}; |
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Lines 138-147
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| 138 |
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137 |
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| 139 |
.bmdma_setup = ata_bmdma_setup_pio, |
138 |
.bmdma_setup = ata_bmdma_setup_pio, |
| 140 |
.bmdma_start = ata_bmdma_start_pio, |
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.bmdma_start = ata_bmdma_start_pio, |
| 141 |
.fill_sg = ata_fill_sg, |
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.qc_prep = ata_qc_prep, |
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.qc_issue = ata_qc_issue_prot, |
| 142 |
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| 142 |
.eng_timeout = ata_eng_timeout, |
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.eng_timeout = ata_eng_timeout, |
| 143 |
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| 144 |
.irq_handler = ata_interrupt, |
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.irq_handler = ata_interrupt, |
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.irq_clear = ata_bmdma_irq_clear, |
| 145 |
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| 146 |
.port_start = ata_port_start, |
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.port_start = ata_port_start, |
| 147 |
.port_stop = ata_port_stop, |
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.port_stop = ata_port_stop, |
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Lines 161-170
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| 161 |
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163 |
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| 162 |
.bmdma_setup = ata_bmdma_setup_pio, |
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.bmdma_setup = ata_bmdma_setup_pio, |
| 163 |
.bmdma_start = ata_bmdma_start_pio, |
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.bmdma_start = ata_bmdma_start_pio, |
| 164 |
.fill_sg = ata_fill_sg, |
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.qc_prep = ata_qc_prep, |
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.qc_issue = ata_qc_issue_prot, |
| 168 |
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| 165 |
.eng_timeout = ata_eng_timeout, |
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.eng_timeout = ata_eng_timeout, |
| 166 |
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| 167 |
.irq_handler = ata_interrupt, |
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.irq_handler = ata_interrupt, |
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.irq_clear = ata_bmdma_irq_clear, |
| 168 |
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| 169 |
.port_start = ata_port_start, |
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.port_start = ata_port_start, |
| 170 |
.port_stop = ata_port_stop, |
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.port_stop = ata_port_stop, |
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Lines 199-204
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| 199 |
.udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */ |
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.udma_mask = ATA_UDMA_MASK_40C, /* FIXME: cbl det */ |
| 200 |
.port_ops = &piix_pata_ops, |
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.port_ops = &piix_pata_ops, |
| 201 |
}, |
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}, |
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| 208 |
/* ich6_sata */ |
| 209 |
{ |
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.sht = &piix_sht, |
| 211 |
.host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST | |
| 212 |
PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR | |
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ATA_FLAG_SLAVE_POSS, |
| 214 |
.pio_mask = 0x03, /* pio3-4 */ |
| 215 |
.udma_mask = 0x7f, /* udma0-6 ; FIXME */ |
| 216 |
.port_ops = &piix_sata_ops, |
| 217 |
}, |
| 202 |
}; |
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}; |
| 203 |
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219 |
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| 204 |
static struct pci_bits piix_enable_bits[] = { |
220 |
static struct pci_bits piix_enable_bits[] = { |
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Lines 327-339
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| 327 |
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343 |
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| 328 |
static void piix_sata_phy_reset(struct ata_port *ap) |
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static void piix_sata_phy_reset(struct ata_port *ap) |
| 329 |
{ |
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{ |
| 330 |
if (!pci_test_config_bits(ap->host_set->pdev, |
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| 331 |
&piix_enable_bits[ap->port_no])) { |
| 332 |
ata_port_disable(ap); |
| 333 |
printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id); |
| 334 |
return; |
| 335 |
} |
| 336 |
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| 337 |
if (!piix_sata_probe(ap)) { |
346 |
if (!piix_sata_probe(ap)) { |
| 338 |
ata_port_disable(ap); |
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ata_port_disable(ap); |
| 339 |
printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id); |
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printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id); |