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Gentoo's Bugzilla – Attachment 353476 Details for
Bug 451032
Example files for Emacs test plans
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Example file for app-emacs/vhdl-mode
example.vhdl (text/plain), 1.16 KB, created by
Ulrich Müller
on 2013-07-16 20:42:25 UTC
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Description:
Example file for app-emacs/vhdl-mode
Filename:
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Creator:
Ulrich Müller
Created:
2013-07-16 20:42:25 UTC
Size:
1.16 KB
patch
obsolete
>-- The following example is an up-counter with asynchronous reset, >-- parallel load and configurable width. It demonstrates the use >-- of the 'unsigned' type, type conversions between 'unsigned' and >-- 'std_logic_vector' and VHDL generics. The generics are very >-- close to arguments or templates in other traditional programming >-- languages like C++. > >library IEEE; >use IEEE.std_logic_1164.all; >use IEEE.numeric_std.all; -- for the unsigned type > >entity COUNTER is > generic ( > WIDTH : in natural := 32); > port ( > RST : in std_logic; > CLK : in std_logic; > LOAD : in std_logic; > DATA : in std_logic_vector(WIDTH-1 downto 0); > Q : out std_logic_vector(WIDTH-1 downto 0)); >end entity COUNTER; > >architecture RTL of COUNTER is > signal CNT : unsigned(WIDTH-1 downto 0); >begin > process(RST, CLK) is > begin > if RST = '1' then > CNT <= (others => '0'); > elsif rising_edge(CLK) then > if LOAD = '1' then > CNT <= unsigned(DATA); -- type is converted to unsigned > else > CNT <= CNT + 1; > end if; > end if; > end process; > > Q <= std_logic_vector(CNT); -- type is converted back to std_logic_vector >end architecture RTL;
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