Lines 479-523
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479 |
#define __NR_pciconfig_iobase 200 |
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#define __NR_pciconfig_iobase 200 |
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#endif |
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#endif |
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|
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#endif |
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static Bool |
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|
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hwEnableIO(void) |
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Bool |
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xf86EnableIO(void) |
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{ |
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{ |
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#if defined(__powerpc__) |
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int fd; |
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int fd; |
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unsigned int ioBase_phys; |
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unsigned int ioBase_phys = syscall(__NR_pciconfig_iobase, 2, 0, 0); |
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#endif |
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|
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if (ExtendedEnabled) |
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return TRUE; |
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#if defined(__powerpc__) |
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ioBase_phys = syscall(__NR_pciconfig_iobase, 2, 0, 0); |
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|
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fd = open("/dev/mem", O_RDWR); |
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fd = open("/dev/mem", O_RDWR); |
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if (ioBase == NULL) { |
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if (ioBase == NULL) { |
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ioBase = (volatile unsigned char *) mmap(0, 0x20000, |
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ioBase = (volatile unsigned char *) mmap(0, 0x20000, |
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PROT_READ | PROT_WRITE, |
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PROT_READ | PROT_WRITE, |
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MAP_SHARED, fd, ioBase_phys); |
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MAP_SHARED, fd, ioBase_phys); |
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/* Should this be fatal or just a warning? */ |
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#if 0 |
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if (ioBase == MAP_FAILED) { |
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xf86Msg(X_WARNING, |
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"xf86EnableIOPorts: Failed to map iobase (%s)\n", |
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strerror(errno)); |
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return FALSE; |
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} |
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#endif |
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} |
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} |
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close(fd); |
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close(fd); |
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#elif !defined(__mc68000__) && !defined(__sparc__) && !defined(__mips__) && !defined(__sh__) && !defined(__hppa__) && !defined(__s390__) && !defined(__arm__) && !defined(__m32r__) && !defined(__nds32__) |
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return ioBase != MAP_FAILED; |
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} |
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|
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static void |
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hwDisableIO(void) |
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{ |
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munmap(ioBase, 0x20000); |
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ioBase = NULL; |
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} |
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|
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#elif defined(__i386__) || defined(__x86_64__) || defined(__ia64__) || \ |
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defined(__alpha__) |
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|
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static Bool |
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hwEnableIO(void) |
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{ |
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if (ioperm(0, 1024, 1) || iopl(3)) { |
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if (ioperm(0, 1024, 1) || iopl(3)) { |
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if (errno == ENODEV) |
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ErrorF("xf86EnableIOPorts: failed to set IOPL for I/O (%s)\n", |
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ErrorF("xf86EnableIOPorts: no I/O ports found\n"); |
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strerror(errno)); |
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else |
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|
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FatalError("xf86EnableIOPorts: failed to set IOPL" |
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" for I/O (%s)\n", strerror(errno)); |
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return FALSE; |
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return FALSE; |
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} |
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} |
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#if !defined(__alpha__) |
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#if !defined(__alpha__) |
Lines 526-552
Link Here
|
526 |
ioperm(0x40, 4, 0); /* trap access to the timer chip */ |
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ioperm(0x40, 4, 0); /* trap access to the timer chip */ |
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ioperm(0x60, 4, 0); /* trap access to the keyboard controller */ |
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ioperm(0x60, 4, 0); /* trap access to the keyboard controller */ |
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#endif |
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#endif |
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#endif |
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ExtendedEnabled = TRUE; |
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|
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return TRUE; |
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return TRUE; |
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} |
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} |
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static void |
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hwDisableIO(void) |
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{ |
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iopl(0); |
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ioperm(0, 1024, 0); |
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} |
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|
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#else /* non-IO architectures */ |
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|
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#define hwEnableIO() TRUE |
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#define hwDisableIO() do {} while (0) |
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|
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#endif |
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|
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Bool |
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xf86EnableIO(void) |
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{ |
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if (ExtendedEnabled) |
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return TRUE; |
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|
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ExtendedEnabled = hwEnableIO(); |
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|
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return ExtendedEnabled; |
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} |
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|
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void |
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void |
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xf86DisableIO(void) |
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xf86DisableIO(void) |
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{ |
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{ |
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if (!ExtendedEnabled) |
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if (!ExtendedEnabled) |
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return; |
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return; |
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#if defined(__powerpc__) |
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munmap(ioBase, 0x20000); |
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ioBase = NULL; |
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#elif !defined(__mc68000__) && !defined(__sparc__) && !defined(__mips__) && !defined(__sh__) && !defined(__hppa__) && !defined(__arm__) && !defined(__s390__) && !defined(__m32r__) && !defined(__nds32__) |
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iopl(0); |
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ioperm(0, 1024, 0); |
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#endif |
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ExtendedEnabled = FALSE; |
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|
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|
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return; |
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hwDisableIO(); |
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|
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ExtendedEnabled = FALSE; |
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} |
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} |
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|
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#if defined (__alpha__) |
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#if defined (__alpha__) |