Attachment #337724 for bug #452482

Lines 1023-1028 ARCH_LIST=' Link Here

(-)a/configure (-2 / +10 lines)
1023	x86	1023	x86
1024	x86_32	1024	x86_32
1025	x86_64	1025	x86_64
		1026	x86_64_x32
		1027	x86_64_x64
1026	'	1028	'
1027		1029
1028	ARCH_EXT_LIST='	1030	ARCH_EXT_LIST='
Lines 2398-2406 case "$arch" in Link Here
2398	x86)	2400	x86)
2399	subarch="x86_32"	2401	subarch="x86_32"
2400	check_cc <<EOF && subarch="x86_64"	2402	check_cc <<EOF && subarch="x86_64"
2401	int test[(int)sizeof(char*) - 7];	2403	#ifndef __x86_64__
		2404	int test[-1];
		2405	#endif
2402	EOF	2406	EOF
2403	if test "$subarch" = "x86_64"; then	2407	if test "$subarch" = "x86_64"; then
		2408	check_cc <<EOF && subarch="x86_64 x86_64_x64" \|\| subarch="x86_64 x86_64_x32"
		2409	int test[(int)sizeof(char*) - 7];
		2410	EOF
2404	spic=$shared	2411	spic=$shared
2405	fi	2412	fi
2406	;;	2413	;;
Lines 2770-2776 EOF Link Here
2770		2777
2771	if ! disabled_any asm mmx yasm; then	2778	if ! disabled_any asm mmx yasm; then
2772	if check_cmd $yasmexe --version; then	2779	if check_cmd $yasmexe --version; then
2773	enabled x86_64 && yasm_extra="-m amd64"	2780	enabled x86_64_x64 && yasm_extra="-m amd64"
		2781	enabled x86_64_x32 && yasm_extra="-m x32"
2774	yasm_debug="-g dwarf2"	2782	yasm_debug="-g dwarf2"
2775	elif check_cmd nasm -v; then	2783	elif check_cmd nasm -v; then
2776	yasmexe=nasm	2784	yasmexe=nasm




%else
%define w_reg r6
cglobal emu_edge_core, 2, 7, 0
    mov        r4p, r4m         ; end_y
    mov        r5p, r5m         ; block_h
%endif

    ; start with vertical extend (top/bottom) and body pixel copy
    mov preg(w_reg), r7m
    sub preg(w_reg), r6m        ; w = start_x - end_x
    sub         r5, r4
%ifdef ARCH_X86_64
    sub         r4, r3

.v_extend_end:

    ; horizontal extend (left/right)
    mov preg(w_reg), r6m        ; start_x
    sub         r0, w_reg
%ifdef ARCH_X86_64
    mov         r3, r0          ; backup of buf+block_h*linesize

    mov         r0, r0m
    mov         r5, r5m
%endif
    mov preg(w_reg), r7m        ; end_x
    mov        r1p, r8m         ; block_w
    mov         r4, r1
    sub         r1, w_reg
    jz .h_extend_end            ; if (end_x == block_w) goto h_extend_end

    READ_NUM_BYTES  top,    %%n              ; read bytes
.emuedge_extend_top_ %+ %%n %+ _loop:        ; do {
    WRITE_NUM_BYTES top,    %%n              ;   write bytes
    add           r0p , r2p                  ;   dst += linesize
%ifdef ARCH_X86_64
    dec            r3d
%else ; ARCH_X86_32

.emuedge_copy_body_ %+ %%n %+ _loop:         ; do {
    READ_NUM_BYTES  body,   %%n              ;   read bytes
    WRITE_NUM_BYTES body,   %%n              ;   write bytes
    add           r0p , r2p                  ;   dst += linesize
    add           r1p , r2p                  ;   src += linesize
    dec            r4d
    jnz .emuedge_copy_body_ %+ %%n %+ _loop  ; } while (--end_y)

    ; copy bottom pixels
    test           r5 , r5                   ; if (!block_h)
    jz .emuedge_v_extend_end_ %+ %%n         ;   goto end
    sub           r1p , r2p                  ; src -= linesize
    READ_NUM_BYTES  bottom, %%n              ; read bytes
.emuedge_extend_bottom_ %+ %%n %+ _loop:     ; do {
    WRITE_NUM_BYTES bottom, %%n              ;   write bytes
    add           r0p , r2p                  ;   dst += linesize
    dec            r5d
    jnz .emuedge_extend_bottom_ %+ %%n %+ _loop ; } while (--block_h)


%rep 11
ALIGN 64
.emuedge_extend_left_ %+ %%n:          ; do {
    sub        r0p, r2p                ;   dst -= linesize
    READ_V_PIXEL  %%n, [r0+r1]         ;   read pixels
    WRITE_V_PIXEL %%n, r0              ;   write pixels
    dec         r5

ALIGN 64
.emuedge_extend_right_ %+ %%n:          ; do {
%ifdef ARCH_X86_64
    sub       r3p, r2p                  ;   dst -= linesize
    READ_V_PIXEL  %%n, [r3+w_reg-1]     ;   read pixels
    WRITE_V_PIXEL %%n, r3+r4-%%n        ;   write pixels
    dec       r11


%macro V_COPY_ROW 2
%ifidn %1, bottom
    sub        r1p, linesize
%endif
.%1_copy_loop:
    xor    cnt_reg, cnt_reg

%else ; sse
    V_COPY_NPX %1, xmm0, movups, 16, 0xFFFFFFF0
%ifdef ARCH_X86_64
%define linesize r2p
    V_COPY_NPX %1, rax , mov,     8
%else ; ARCH_X86_32
%define linesize r2m

    V_COPY_NPX %1, vall, mov,     1
    mov      w_reg, cnt_reg
%ifidn %1, body
    add        r1p, linesize
%endif
    add        r0p, linesize
    dec         %2
    jnz .%1_copy_loop
%endmacro

.slow_left_extend_loop:
; r0=buf+block_h*linesize,r2=linesize,r6(64)/r3(32)=val,r5=block_h,r4=cntr,r10/r6=start_x
    mov         r4, 8
    sub        r0p, linesize
    READ_V_PIXEL 8, [r0+w_reg]
.left_extend_8px_loop:
    movq [r0+r4-8], mm0

%define bh_reg r5
%endif
    lea         r1, [r4-8]
    sub preg(buf_reg), linesize
    READ_V_PIXEL 8, [buf_reg+w_reg-1]
.right_extend_8px_loop:
    movq [buf_reg+r1], mm0





%include "x86inc.asm"

%ifdef ARCH_X86_64
%define pointer resq
%else
%define pointer resd
%endif

struc FFTContext
    .nbits:    resd 1
    .reverse:  resd 1
    .revtab:   resp 1
    .tmpbuf:   resp 1
    .mdctsize: resd 1
    .mdctbits: resd 1
    .tcos:     resp 1
    .tsin:     resp 1
endstruc

SECTION_RODATA

%assign i i<<1
%endrep

%ifdef ARCH_X86_64
    %define pointer dq
%else
    %define pointer dd
%endif

%macro IF0 1+
%endmacro
%macro IF1 1+


%macro FFT_DISPATCH 2; clobbers 5 GPRs, 8 XMMs
    lea r2, [dispatch_tab%1]
    mov r2p, [r2 + (%2q-2)*ptrsize]
%ifdef PIC
    lea r3, [$$]
    add r2, r3

%undef n

align 8
dispatch_tab%3%2: dp list_of_fft

section .text


    mov   r3d, [r0+FFTContext.mdctsize]
    add   r2, r3
    shr   r3, 1
    mov   preg(rtcos), [r0+FFTContext.tcos]
    mov   preg(rtsin), [r0+FFTContext.tsin]
    add   rtcos, r3
    add   rtsin, r3
%ifndef ARCH_X86_64

    push  rtsin
%endif
    shr   r3, 1
    mov   preg(rrevtab), [r0+FFTContext.revtab]
    add   rrevtab, r3
%ifndef ARCH_X86_64
    push  rrevtab




%macro FLOAT_TO_INT16_INTERLEAVE2 1
cglobal float_to_int16_interleave2_%1, 3,4,2, dst, src0, src1, len
    lea      lenq, [4*r2q]
    mov     src1p, [src0q+ptrsize]
    mov     src0p, [src0q]
    add      dstq, lenq
    add     src0q, lenq
    add     src1q, lenq

%else
    %define lend dword r2m
%endif
    mov src1p, [srcq+1*ptrsize]
    mov src2p, [srcq+2*ptrsize]
    mov src3p, [srcq+3*ptrsize]
    mov src4p, [srcq+4*ptrsize]
    mov src5p, [srcq+5*ptrsize]
    mov srcp,  [srcq]
    sub src1q, srcq
    sub src2q, srcq
    sub src3q, srcq

%else
    %define lend dword r2m
%endif
    mov    src1p, [srcq+1*ptrsize]
    mov    src2p, [srcq+2*ptrsize]
    mov    src3p, [srcq+3*ptrsize]
    mov    src4p, [srcq+4*ptrsize]
    mov    src5p, [srcq+5*ptrsize]
    mov     srcp, [srcq]
    sub    src1q, srcq
    sub    src2q, srcq
    sub    src3q, srcq


%macro FLOAT_INTERLEAVE2 2
cglobal float_interleave2_%1, 3,4,%2, dst, src, len, src1
    mov     src1p, [srcq+ptrsize]
    mov      srcp, [srcq        ]
    sub     src1q, srcq
.loop
    MOVPS      m0, [srcq             ]




    mov          r5, 32
    add          r2, 384
%ifdef ARCH_X86_64
    add         r10, ptrsize
%else
    add        r0mp, ptrsize
%endif
    call         h264_idct_add8_mmx_plane
    RET

    jz .try_dc
%ifdef ARCH_X86_64
    mov         r0d, dword [r1+r5*4]
    add         r0p, [r10]
%else
    mov          r0, r1m ; XXX r1m here is actually r0m of the calling func
    mov          r0, [r0]

    mov          r5, 32
    add          r2, 384
%ifdef ARCH_X86_64
    add         r10, ptrsize
%else
    add        r0mp, ptrsize
%endif
    call h264_idct_add8_mmx2_plane
    RET

    jz .try%1dc
%ifdef ARCH_X86_64
    mov        r0d, dword [r1+(%1&1)*8+64*(1+(%1>>1))]
    add        r0p, [r10]
%else
    mov         r0, r0m
    mov         r0, [r0]

    jz .cycle%1end
%ifdef ARCH_X86_64
    mov        r0d, dword [r1+(%1&1)*8+64*(1+(%1>>1))]
    add        r0p, [r10]
%else
    mov         r0, r0m
    mov         r0, [r0]

    add8_sse2_cycle 0, 0x34
    add8_sse2_cycle 1, 0x3c
%ifdef ARCH_X86_64
    add         r10, ptrsize
%else
    add        r0mp, ptrsize
%endif
    add8_sse2_cycle 2, 0x5c
    add8_sse2_cycle 3, 0x64




    mov r10, r0
%endif
    add      r2, 1024
    mov     r0p, [r0]
    ADD16_OP_INTRA %1, 16, 4+ 6*8
    ADD16_OP_INTRA %1, 18, 4+ 7*8
    add      r2, 1024-128*2
%ifdef ARCH_X86_64
    mov     r0p, [r10+ptrsize]
%else
    mov      r0, r0m
    mov      r0, [r0+ptrsize]
%endif
    ADD16_OP_INTRA %1, 32, 4+11*8
    ADD16_OP_INTRA %1, 34, 4+12*8

Lines 156-163 static void mlp_filter_channel_x86(int32_t state, const int32_t coeff, Link Here

(-)a/libavcodec/x86/mlpdsp.c (-2 / +2 lines)
156	/* 2*/"+r"(sample_buffer),	156	/* 2*/"+r"(sample_buffer),
157	#if ARCH_X86_64	157	#if ARCH_X86_64
158	/* 3*/"+r"(blocksize)	158	/* 3*/"+r"(blocksize)
159	: /* 4/"r"((x86_reg)mask), / 5*/"r"(firjump),	159	: /* 4/"r"((x86_native_reg)mask), / 5*/"r"((x86_native_reg)(uintptr_t)firjump),
160	/* 6/"r"(iirjump) , / 7*/"c"(filter_shift)	160	/* 6/"r"((x86_native_reg)(uintptr_t)iirjump), / 7*/"c"(filter_shift)
161	, /* 8*/"r"((int64_t)coeff[0])	161	, /* 8*/"r"((int64_t)coeff[0])
162	, /* 9*/"r"((int64_t)coeff[1])	162	, /* 9*/"r"((int64_t)coeff[1])
163	, /10/"r"((int64_t)coeff[2])	163	, /10/"r"((int64_t)coeff[2])

Lines 28-36 Link Here

(-)a/libavutil/x86/cpu.c (-2 / +2 lines)
28	/* ebx saving is necessary for PIC. gcc seems unable to see it alone */	28	/* ebx saving is necessary for PIC. gcc seems unable to see it alone */
29	#define cpuid(index,eax,ebx,ecx,edx)\	29	#define cpuid(index,eax,ebx,ecx,edx)\
30	__asm__ volatile\	30	__asm__ volatile\
31	("mov %%"REG_b", %%"REG_S"\n\t"\	31	("mov %%"REG_rb", %%"REG_rS"\n\t"\
32	"cpuid\n\t"\	32	"cpuid\n\t"\
33	"xchg %%"REG_b", %%"REG_S\	33	"xchg %%"REG_rb", %%"REG_rS\
34	: "=a" (eax), "=S" (ebx),\	34	: "=a" (eax), "=S" (ebx),\
35	"=c" (ecx), "=d" (edx)\	35	"=c" (ecx), "=d" (edx)\
36	: "0" (index));	36	: "0" (index));

Lines 120-131 Link Here

(-)a/libavutil/x86/x86inc.asm (-1 / +33 lines)
120		120
121	; registers:	121	; registers:
122	; rN and rNq are the native-size register holding function argument N	122	; rN and rNq are the native-size register holding function argument N
123	; rNd, rNw, rNb are dword, word, and byte size	123	; rNp, rNd, rNw, rNb are pointer, dword, word, and byte size
124	; rNm is the original location of arg N (a register or on the stack), dword	124	; rNm is the original location of arg N (a register or on the stack), dword
125	; rNmp is native size	125	; rNmp is native size
126		126
127	%macro DECLARE_REG 6	127	%macro DECLARE_REG 6
128	%define r%1q %2	128	%define r%1q %2
		129	%ifdef ARCH_X86_64_X64
		130	%define r%1p %2
		131	%else
		132	%define r%1p %3
		133	%endif
129	%define r%1d %3	134	%define r%1d %3
130	%define r%1w %4	135	%define r%1w %4
131	%define r%1b %5	136	%define r%1b %5
Lines 143-148 Link Here
143	%macro DECLARE_REG_SIZE 2	148	%macro DECLARE_REG_SIZE 2
144	%define r%1q r%1	149	%define r%1q r%1
145	%define e%1q r%1	150	%define e%1q r%1
		151	%ifdef ARCH_X86_64_X64
		152	%define r%1p r%1
		153	%else
		154	%define r%1p e%1
		155	%endif
		156	%define e%1p e%1
146	%define r%1d e%1	157	%define r%1d e%1
147	%define e%1d e%1	158	%define e%1d e%1
148	%define r%1w %1	159	%define r%1w %1
Lines 176-181 DECLARE_REG_SIZE bp, bpl Link Here
176	%macro DECLARE_REG_TMP_SIZE 0-*	187	%macro DECLARE_REG_TMP_SIZE 0-*
177	%rep %0	188	%rep %0
178	%define t%1q t%1 %+ q	189	%define t%1q t%1 %+ q
		190	%ifdef ARCH_X86_64_X64
		191	%define t%1p t%1
		192	%else
		193	%define t%1p t%1 %+ d
		194	%endif
179	%define t%1d t%1 %+ d	195	%define t%1d t%1 %+ d
180	%define t%1w t%1 %+ w	196	%define t%1w t%1 %+ w
181	%define t%1b t%1 %+ b	197	%define t%1b t%1 %+ b
Lines 191-196 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9 Link Here
191	%define gprsize 4	207	%define gprsize 4
192	%endif	208	%endif
193		209
		210	%ifdef ARCH_X86_64_X64
		211	%define ptrsize 8
		212	%define pword qword
		213	%define dp dq
		214	%define resp resq
		215	%define preg(x) x
		216	%else
		217	%define ptrsize 4
		218	%define pword dword
		219	%define dp dd
		220	%define resp resd
		221	%define preg(x) x %+ d
		222	%endif
		223
194	%macro PUSH 1	224	%macro PUSH 1
195	push %1	225	push %1
196	%assign stack_offset stack_offset+gprsize	226	%assign stack_offset stack_offset+gprsize
Lines 238-243 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9 Link Here
238	%assign %%i 0	268	%assign %%i 0
239	%rep n_arg_names	269	%rep n_arg_names
240	CAT_UNDEF arg_name %+ %%i, q	270	CAT_UNDEF arg_name %+ %%i, q
		271	CAT_UNDEF arg_name %+ %%i, p
241	CAT_UNDEF arg_name %+ %%i, d	272	CAT_UNDEF arg_name %+ %%i, d
242	CAT_UNDEF arg_name %+ %%i, w	273	CAT_UNDEF arg_name %+ %%i, w
243	CAT_UNDEF arg_name %+ %%i, b	274	CAT_UNDEF arg_name %+ %%i, b
Lines 250-255 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9 Link Here
250	%assign %%i 0	281	%assign %%i 0
251	%rep %0	282	%rep %0
252	%xdefine %1q r %+ %%i %+ q	283	%xdefine %1q r %+ %%i %+ q
		284	%xdefine %1p r %+ %%i %+ p
253	%xdefine %1d r %+ %%i %+ d	285	%xdefine %1d r %+ %%i %+ d
254	%xdefine %1w r %+ %%i %+ w	286	%xdefine %1w r %+ %%i %+ w
255	%xdefine %1b r %+ %%i %+ b	287	%xdefine %1b r %+ %%i %+ b




#include <stdint.h>
#include "config.h"

#if ARCH_X86_64_X64
#    define OPSIZE "q"
#    define REG_a "rax"
#    define REG_b "rbx"

#    define REG_d "rdx"
#    define REG_D "rdi"
#    define REG_S "rsi"
#    define REG_8 "r8"
#    define PTR_SIZE "8"
typedef int64_t x86_reg;


#    define REGc    rcx
#    define REGd    rdx
#    define REGSP   rsp
#    define REG8    r8

#elif ARCH_X86_32 || ARCH_X86_64_X32

#    define OPSIZE "l"
#    define REG_a "eax"

#    define REG_d "edx"
#    define REG_D "edi"
#    define REG_S "esi"
#    define REG_8 "r8d"
#    define PTR_SIZE "4"
typedef int32_t x86_reg;


#    define REGc    ecx
#    define REGd    edx
#    define REGSP   esp
#    define REG8    r8d
#else
typedef int x86_reg;
#endif

#if ARCH_X86_64
#    define REG_rb "rbx"
#    define REG_rS "rsi"
#    define REG_rBP "rbp"
typedef int64_t x86_native_reg;
#elif ARCH_X86_32
#    define REG_rb "ebx"
#    define REG_rS "esi"
#    define REG_rBP "ebp"
typedef int32_t x86_native_reg;
#endif

#define HAVE_7REGS (ARCH_X86_64 || (HAVE_EBX_AVAILABLE && HAVE_EBP_AVAILABLE))
#define HAVE_6REGS (ARCH_X86_64 || (HAVE_EBX_AVAILABLE || HAVE_EBP_AVAILABLE))





    movsx     cntr_reg,  r1m
.filterloop_ %+ %%i:
    ; input pixels
    mov            r6p, [r2+ptrsize*cntr_reg-2*ptrsize]
%if %1 == 16
    mova            m3, [r6+r5*4]
    mova            m5, [r6+r5*4+mmsize]
%else ; %1 == 8/9/10
    mova            m3, [r6+r5*2]
%endif ; %1 == 8/9/10/16
    mov            r6p, [r2+ptrsize*cntr_reg-ptrsize]
%if %1 == 16
    mova            m4, [r6+r5*4]
    mova            m6, [r6+r5*4+mmsize]




        const int16_t *abuf0 = abuf[0], *abuf1 = abuf[1];
#if ARCH_X86_64
        __asm__ volatile(
            YSCALEYUV2RGB(%%REG8, %5)
            YSCALEYUV2RGB_YA(%%REG8, %5, %6, %7)
            "psraw                  $3, %%mm1       \n\t" /* abuf0[eax] - abuf1[eax] >>7*/
            "psraw                  $3, %%mm7       \n\t" /* abuf0[eax] - abuf1[eax] >>7*/
            "packuswb            %%mm7, %%mm1       \n\t"
            WRITEBGR32(%4, 8280(%5), %%REG8, %%mm2, %%mm4, %%mm5, %%mm1, %%mm0, %%mm7, %%mm3, %%mm6)
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "r" (dest),
               "a" (&c->redDither),
               "r" (abuf0), "r" (abuf1)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB(%%REGBP, %5)
            "push                   %0              \n\t"
            "push                   %1              \n\t"

            "pop                    %1              \n\t"
            "pop                    %0              \n\t"
            WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm1, %%mm0, %%mm7, %%mm3, %%mm6)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB(%%REGBP, %5)
            "pcmpeqd %%mm7, %%mm7                   \n\t"
            WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

    __asm__ volatile(
        "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
        "mov        %4, %%"REG_b"               \n\t"
        "push %%"REG_rBP"                       \n\t"
        YSCALEYUV2RGB(%%REGBP, %5)
        "pxor    %%mm7, %%mm7                   \n\t"
        WRITEBGR24(%%REGb, 8280(%5), %%REGBP)
        "pop %%"REG_rBP"                        \n\t"
        "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
        :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
           "a" (&c->redDither)

    __asm__ volatile(
        "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
        "mov        %4, %%"REG_b"               \n\t"
        "push %%"REG_rBP"                       \n\t"
        YSCALEYUV2RGB(%%REGBP, %5)
        "pxor    %%mm7, %%mm7                   \n\t"
        /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */

        "paddusb "RED_DITHER"(%5), %%mm5      \n\t"
#endif
        WRITERGB15(%%REGb, 8280(%5), %%REGBP)
        "pop %%"REG_rBP"                        \n\t"
        "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
        :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
           "a" (&c->redDither)

    __asm__ volatile(
        "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
        "mov        %4, %%"REG_b"               \n\t"
        "push %%"REG_rBP"                       \n\t"
        YSCALEYUV2RGB(%%REGBP, %5)
        "pxor    %%mm7, %%mm7                   \n\t"
        /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */

        "paddusb "RED_DITHER"(%5), %%mm5      \n\t"
#endif
        WRITERGB16(%%REGb, 8280(%5), %%REGBP)
        "pop %%"REG_rBP"                        \n\t"
        "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
        :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
           "a" (&c->redDither)

    __asm__ volatile(
        "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
        "mov %4, %%"REG_b"                        \n\t"
        "push %%"REG_rBP"                       \n\t"
        YSCALEYUV2PACKED(%%REGBP, %5)
        WRITEYUY2(%%REGb, 8280(%5), %%REGBP)
        "pop %%"REG_rBP"                        \n\t"
        "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
        :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
           "a" (&c->redDither)

            __asm__ volatile(
                "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
                "mov        %4, %%"REG_b"               \n\t"
                "push %%"REG_rBP"                       \n\t"
                YSCALEYUV2RGB1(%%REGBP, %5)
                YSCALEYUV2RGB1_ALPHA(%%REGBP)
                WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
                "pop %%"REG_rBP"                        \n\t"
                "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
                :: "c" (buf0), "d" (abuf0), "S" (ubuf0), "D" (ubuf1), "m" (dest),
                   "a" (&c->redDither)

            __asm__ volatile(
                "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
                "mov        %4, %%"REG_b"               \n\t"
                "push %%"REG_rBP"                       \n\t"
                YSCALEYUV2RGB1(%%REGBP, %5)
                "pcmpeqd %%mm7, %%mm7                   \n\t"
                WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
                "pop %%"REG_rBP"                        \n\t"
                "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
                :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
                   "a" (&c->redDither)

            __asm__ volatile(
                "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
                "mov        %4, %%"REG_b"               \n\t"
                "push %%"REG_rBP"                       \n\t"
                YSCALEYUV2RGB1b(%%REGBP, %5)
                YSCALEYUV2RGB1_ALPHA(%%REGBP)
                WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
                "pop %%"REG_rBP"                        \n\t"
                "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
                :: "c" (buf0), "d" (abuf0), "S" (ubuf0), "D" (ubuf1), "m" (dest),
                   "a" (&c->redDither)

            __asm__ volatile(
                "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
                "mov        %4, %%"REG_b"               \n\t"
                "push %%"REG_rBP"                       \n\t"
                YSCALEYUV2RGB1b(%%REGBP, %5)
                "pcmpeqd %%mm7, %%mm7                   \n\t"
                WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
                "pop %%"REG_rBP"                        \n\t"
                "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
                :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
                   "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB1(%%REGBP, %5)
            "pxor    %%mm7, %%mm7                   \n\t"
            WRITEBGR24(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB1b(%%REGBP, %5)
            "pxor    %%mm7, %%mm7                   \n\t"
            WRITEBGR24(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB1(%%REGBP, %5)
            "pxor    %%mm7, %%mm7                   \n\t"
            /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */

            "paddusb "RED_DITHER"(%5), %%mm5      \n\t"
#endif
            WRITERGB15(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB1b(%%REGBP, %5)
            "pxor    %%mm7, %%mm7                   \n\t"
            /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */

            "paddusb "RED_DITHER"(%5), %%mm5      \n\t"
#endif
            WRITERGB15(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB1(%%REGBP, %5)
            "pxor    %%mm7, %%mm7                   \n\t"
            /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */

            "paddusb "RED_DITHER"(%5), %%mm5      \n\t"
#endif
            WRITERGB16(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2RGB1b(%%REGBP, %5)
            "pxor    %%mm7, %%mm7                   \n\t"
            /* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */

            "paddusb "RED_DITHER"(%5), %%mm5      \n\t"
#endif
            WRITERGB16(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2PACKED1(%%REGBP, %5)
            WRITEYUY2(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

        __asm__ volatile(
            "mov %%"REG_b", "ESP_OFFSET"(%5)        \n\t"
            "mov        %4, %%"REG_b"               \n\t"
            "push %%"REG_rBP"                       \n\t"
            YSCALEYUV2PACKED1b(%%REGBP, %5)
            WRITEYUY2(%%REGb, 8280(%5), %%REGBP)
            "pop %%"REG_rBP"                        \n\t"
            "mov "ESP_OFFSET"(%5), %%"REG_b"        \n\t"
            :: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
               "a" (&c->redDither)

{
    int32_t *filterPos = c->hLumFilterPos;
    int16_t *filter    = c->hLumFilter;
    x86_native_reg mmx2FilterCode = (uintptr_t)c->lumMmx2FilterCode;
    int i;
#if defined(PIC)
    uint64_t ebxsave;
- 

Return to bug 452482

Lines 505-517 cglobal emu_edge_core, 6, 7, 1 Link Here

(-)a/libavcodec/x86/dsputil_yasm.asm (-20 / +20 lines)
505	%else	505	%else
506	%define w_reg r6	506	%define w_reg r6
507	cglobal emu_edge_core, 2, 7, 0	507	cglobal emu_edge_core, 2, 7, 0
508	mov r4, r4m ; end_y	508	mov r4p, r4m ; end_y
509	mov r5, r5m ; block_h	509	mov r5p, r5m ; block_h
510	%endif	510	%endif
511		511
512	; start with vertical extend (top/bottom) and body pixel copy	512	; start with vertical extend (top/bottom) and body pixel copy
513	mov w_reg, r7m	513	mov preg(w_reg), r7m
514	sub w_reg, r6m ; w = start_x - end_x	514	sub preg(w_reg), r6m ; w = start_x - end_x
515	sub r5, r4	515	sub r5, r4
516	%ifdef ARCH_X86_64	516	%ifdef ARCH_X86_64
517	sub r4, r3	517	sub r4, r3
Lines 534-540 cglobal emu_edge_core, 2, 7, 0 Link Here
534	.v_extend_end:	534	.v_extend_end:
535		535
536	; horizontal extend (left/right)	536	; horizontal extend (left/right)
537	mov w_reg, r6m ; start_x	537	mov preg(w_reg), r6m ; start_x
538	sub r0, w_reg	538	sub r0, w_reg
539	%ifdef ARCH_X86_64	539	%ifdef ARCH_X86_64
540	mov r3, r0 ; backup of buf+block_h*linesize	540	mov r3, r0 ; backup of buf+block_h*linesize
Lines 568-575 cglobal emu_edge_core, 2, 7, 0 Link Here
568	mov r0, r0m	568	mov r0, r0m
569	mov r5, r5m	569	mov r5, r5m
570	%endif	570	%endif
571	mov w_reg, r7m ; end_x	571	mov preg(w_reg), r7m ; end_x
572	mov r1, r8m ; block_w	572	mov r1p, r8m ; block_w
573	mov r4, r1	573	mov r4, r1
574	sub r1, w_reg	574	sub r1, w_reg
575	jz .h_extend_end ; if (end_x == block_w) goto h_extend_end	575	jz .h_extend_end ; if (end_x == block_w) goto h_extend_end
Lines 750-756 ALIGN 128 Link Here
750	READ_NUM_BYTES top, %%n ; read bytes	750	READ_NUM_BYTES top, %%n ; read bytes
751	.emuedge_extend_top_ %+ %%n %+ _loop: ; do {	751	.emuedge_extend_top_ %+ %%n %+ _loop: ; do {
752	WRITE_NUM_BYTES top, %%n ; write bytes	752	WRITE_NUM_BYTES top, %%n ; write bytes
753	add r0 , r2 ; dst += linesize	753	add r0p , r2p ; dst += linesize
754	%ifdef ARCH_X86_64	754	%ifdef ARCH_X86_64
755	dec r3d	755	dec r3d
756	%else ; ARCH_X86_32	756	%else ; ARCH_X86_32
Lines 762-780 ALIGN 128 Link Here
762	.emuedge_copy_body_ %+ %%n %+ _loop: ; do {	762	.emuedge_copy_body_ %+ %%n %+ _loop: ; do {
763	READ_NUM_BYTES body, %%n ; read bytes	763	READ_NUM_BYTES body, %%n ; read bytes
764	WRITE_NUM_BYTES body, %%n ; write bytes	764	WRITE_NUM_BYTES body, %%n ; write bytes
765	add r0 , r2 ; dst += linesize	765	add r0p , r2p ; dst += linesize
766	add r1 , r2 ; src += linesize	766	add r1p , r2p ; src += linesize
767	dec r4d	767	dec r4d
768	jnz .emuedge_copy_body_ %+ %%n %+ _loop ; } while (--end_y)	768	jnz .emuedge_copy_body_ %+ %%n %+ _loop ; } while (--end_y)
769		769
770	; copy bottom pixels	770	; copy bottom pixels
771	test r5 , r5 ; if (!block_h)	771	test r5 , r5 ; if (!block_h)
772	jz .emuedge_v_extend_end_ %+ %%n ; goto end	772	jz .emuedge_v_extend_end_ %+ %%n ; goto end
773	sub r1 , r2 ; src -= linesize	773	sub r1p , r2p ; src -= linesize
774	READ_NUM_BYTES bottom, %%n ; read bytes	774	READ_NUM_BYTES bottom, %%n ; read bytes
775	.emuedge_extend_bottom_ %+ %%n %+ _loop: ; do {	775	.emuedge_extend_bottom_ %+ %%n %+ _loop: ; do {
776	WRITE_NUM_BYTES bottom, %%n ; write bytes	776	WRITE_NUM_BYTES bottom, %%n ; write bytes
777	add r0 , r2 ; dst += linesize	777	add r0p , r2p ; dst += linesize
778	dec r5d	778	dec r5d
779	jnz .emuedge_extend_bottom_ %+ %%n %+ _loop ; } while (--block_h)	779	jnz .emuedge_extend_bottom_ %+ %%n %+ _loop ; } while (--block_h)
780		780
Lines 836-842 ALIGN 128 Link Here
836	%rep 11	836	%rep 11
837	ALIGN 64	837	ALIGN 64
838	.emuedge_extend_left_ %+ %%n: ; do {	838	.emuedge_extend_left_ %+ %%n: ; do {
839	sub r0, r2 ; dst -= linesize	839	sub r0p, r2p ; dst -= linesize
840	READ_V_PIXEL %%n, [r0+r1] ; read pixels	840	READ_V_PIXEL %%n, [r0+r1] ; read pixels
841	WRITE_V_PIXEL %%n, r0 ; write pixels	841	WRITE_V_PIXEL %%n, r0 ; write pixels
842	dec r5	842	dec r5
Lines 857-863 ALIGN 64 Link Here
857	ALIGN 64	857	ALIGN 64
858	.emuedge_extend_right_ %+ %%n: ; do {	858	.emuedge_extend_right_ %+ %%n: ; do {
859	%ifdef ARCH_X86_64	859	%ifdef ARCH_X86_64
860	sub r3, r2 ; dst -= linesize	860	sub r3p, r2p ; dst -= linesize
861	READ_V_PIXEL %%n, [r3+w_reg-1] ; read pixels	861	READ_V_PIXEL %%n, [r3+w_reg-1] ; read pixels
862	WRITE_V_PIXEL %%n, r3+r4-%%n ; write pixels	862	WRITE_V_PIXEL %%n, r3+r4-%%n ; write pixels
863	dec r11	863	dec r11
Lines 907-913 ALIGN 64 Link Here
907		907
908	%macro V_COPY_ROW 2	908	%macro V_COPY_ROW 2
909	%ifidn %1, bottom	909	%ifidn %1, bottom
910	sub r1, linesize	910	sub r1p, linesize
911	%endif	911	%endif
912	.%1_copy_loop:	912	.%1_copy_loop:
913	xor cnt_reg, cnt_reg	913	xor cnt_reg, cnt_reg
Lines 917-923 ALIGN 64 Link Here
917	%else ; sse	917	%else ; sse
918	V_COPY_NPX %1, xmm0, movups, 16, 0xFFFFFFF0	918	V_COPY_NPX %1, xmm0, movups, 16, 0xFFFFFFF0
919	%ifdef ARCH_X86_64	919	%ifdef ARCH_X86_64
920	%define linesize r2	920	%define linesize r2p
921	V_COPY_NPX %1, rax , mov, 8	921	V_COPY_NPX %1, rax , mov, 8
922	%else ; ARCH_X86_32	922	%else ; ARCH_X86_32
923	%define linesize r2m	923	%define linesize r2m
Lines 929-937 ALIGN 64 Link Here
929	V_COPY_NPX %1, vall, mov, 1	929	V_COPY_NPX %1, vall, mov, 1
930	mov w_reg, cnt_reg	930	mov w_reg, cnt_reg
931	%ifidn %1, body	931	%ifidn %1, body
932	add r1, linesize	932	add r1p, linesize
933	%endif	933	%endif
934	add r0, linesize	934	add r0p, linesize
935	dec %2	935	dec %2
936	jnz .%1_copy_loop	936	jnz .%1_copy_loop
937	%endmacro	937	%endmacro
Lines 978-984 ALIGN 64 Link Here
978	.slow_left_extend_loop:	978	.slow_left_extend_loop:
979	; r0=buf+block_h*linesize,r2=linesize,r6(64)/r3(32)=val,r5=block_h,r4=cntr,r10/r6=start_x	979	; r0=buf+block_h*linesize,r2=linesize,r6(64)/r3(32)=val,r5=block_h,r4=cntr,r10/r6=start_x
980	mov r4, 8	980	mov r4, 8
981	sub r0, linesize	981	sub r0p, linesize
982	READ_V_PIXEL 8, [r0+w_reg]	982	READ_V_PIXEL 8, [r0+w_reg]
983	.left_extend_8px_loop:	983	.left_extend_8px_loop:
984	movq [r0+r4-8], mm0	984	movq [r0+r4-8], mm0
Lines 1014-1020 ALIGN 64 Link Here
1014	%define bh_reg r5	1014	%define bh_reg r5
1015	%endif	1015	%endif
1016	lea r1, [r4-8]	1016	lea r1, [r4-8]
1017	sub buf_reg, linesize	1017	sub preg(buf_reg), linesize
1018	READ_V_PIXEL 8, [buf_reg+w_reg-1]	1018	READ_V_PIXEL 8, [buf_reg+w_reg-1]
1019	.right_extend_8px_loop:	1019	.right_extend_8px_loop:
1020	movq [buf_reg+r1], mm0	1020	movq [buf_reg+r1], mm0

Lines 624-632 cglobal h264_idct_add8_8_mmx, 5, 7, 0 Link Here

(-)a/libavcodec/x86/h264_idct.asm (-9 / +9 lines)
624	mov r5, 32	624	mov r5, 32
625	add r2, 384	625	add r2, 384
626	%ifdef ARCH_X86_64	626	%ifdef ARCH_X86_64
627	add r10, gprsize	627	add r10, ptrsize
628	%else	628	%else
629	add r0mp, gprsize	629	add r0mp, ptrsize
630	%endif	630	%endif
631	call h264_idct_add8_mmx_plane	631	call h264_idct_add8_mmx_plane
632	RET	632	RET
Lines 639-645 h264_idct_add8_mmx2_plane Link Here
639	jz .try_dc	639	jz .try_dc
640	%ifdef ARCH_X86_64	640	%ifdef ARCH_X86_64
641	mov r0d, dword [r1+r5*4]	641	mov r0d, dword [r1+r5*4]
642	add r0, [r10]	642	add r0p, [r10]
643	%else	643	%else
644	mov r0, r1m ; XXX r1m here is actually r0m of the calling func	644	mov r0, r1m ; XXX r1m here is actually r0m of the calling func
645	mov r0, [r0]	645	mov r0, [r0]
Lines 687-695 cglobal h264_idct_add8_8_mmx2, 5, 7, 0 Link Here
687	mov r5, 32	687	mov r5, 32
688	add r2, 384	688	add r2, 384
689	%ifdef ARCH_X86_64	689	%ifdef ARCH_X86_64
690	add r10, gprsize	690	add r10, ptrsize
691	%else	691	%else
692	add r0mp, gprsize	692	add r0mp, ptrsize
693	%endif	693	%endif
694	call h264_idct_add8_mmx2_plane	694	call h264_idct_add8_mmx2_plane
695	RET	695	RET
Lines 819-825 cglobal h264_idct_add16intra_8_sse2, 5, 7, 8 Link Here
819	jz .try%1dc	819	jz .try%1dc
820	%ifdef ARCH_X86_64	820	%ifdef ARCH_X86_64
821	mov r0d, dword [r1+(%1&1)8+64(1+(%1>>1))]	821	mov r0d, dword [r1+(%1&1)8+64(1+(%1>>1))]
822	add r0, [r10]	822	add r0p, [r10]
823	%else	823	%else
824	mov r0, r0m	824	mov r0, r0m
825	mov r0, [r0]	825	mov r0, [r0]
Lines 833-839 cglobal h264_idct_add16intra_8_sse2, 5, 7, 8 Link Here
833	jz .cycle%1end	833	jz .cycle%1end
834	%ifdef ARCH_X86_64	834	%ifdef ARCH_X86_64
835	mov r0d, dword [r1+(%1&1)8+64(1+(%1>>1))]	835	mov r0d, dword [r1+(%1&1)8+64(1+(%1>>1))]
836	add r0, [r10]	836	add r0p, [r10]
837	%else	837	%else
838	mov r0, r0m	838	mov r0, r0m
839	mov r0, [r0]	839	mov r0, [r0]
Lines 858-866 cglobal h264_idct_add8_8_sse2, 5, 7, 8 Link Here
858	add8_sse2_cycle 0, 0x34	858	add8_sse2_cycle 0, 0x34
859	add8_sse2_cycle 1, 0x3c	859	add8_sse2_cycle 1, 0x3c
860	%ifdef ARCH_X86_64	860	%ifdef ARCH_X86_64
861	add r10, gprsize	861	add r10, ptrsize
862	%else	862	%else
863	add r0mp, gprsize	863	add r0mp, ptrsize
864	%endif	864	%endif
865	add8_sse2_cycle 2, 0x5c	865	add8_sse2_cycle 2, 0x5c
866	add8_sse2_cycle 3, 0x64	866	add8_sse2_cycle 3, 0x64

Lines 320-334 cglobal h264_idct_add8_10_%1,5,7 Link Here

(-)a/libavcodec/x86/h264_idct_10bit.asm (-3 / +3 lines)
320	mov r10, r0	320	mov r10, r0
321	%endif	321	%endif
322	add r2, 1024	322	add r2, 1024
323	mov r0, [r0]	323	mov r0p, [r0]
324	ADD16_OP_INTRA %1, 16, 4+ 6*8	324	ADD16_OP_INTRA %1, 16, 4+ 6*8
325	ADD16_OP_INTRA %1, 18, 4+ 7*8	325	ADD16_OP_INTRA %1, 18, 4+ 7*8
326	add r2, 1024-128*2	326	add r2, 1024-128*2
327	%ifdef ARCH_X86_64	327	%ifdef ARCH_X86_64
328	mov r0, [r10+gprsize]	328	mov r0p, [r10+ptrsize]
329	%else	329	%else
330	mov r0, r0m	330	mov r0, r0m
331	mov r0, [r0+gprsize]	331	mov r0, [r0+ptrsize]
332	%endif	332	%endif
333	ADD16_OP_INTRA %1, 32, 4+11*8	333	ADD16_OP_INTRA %1, 32, 4+11*8
334	ADD16_OP_INTRA %1, 34, 4+12*8	334	ADD16_OP_INTRA %1, 34, 4+12*8

Lines 30-50 Link Here

(-)a/libavcodec/x86/fft_mmx.asm (-21 / +9 lines)
30		30
31	%include "x86inc.asm"	31	%include "x86inc.asm"
32		32
33	%ifdef ARCH_X86_64
34	%define pointer resq
35	%else
36	%define pointer resd
37	%endif
38
39	struc FFTContext	33	struc FFTContext
40	.nbits: resd 1	34	.nbits: resd 1
41	.reverse: resd 1	35	.reverse: resd 1
42	.revtab: pointer 1	36	.revtab: resp 1
43	.tmpbuf: pointer 1	37	.tmpbuf: resp 1
44	.mdctsize: resd 1	38	.mdctsize: resd 1
45	.mdctbits: resd 1	39	.mdctbits: resd 1
46	.tcos: pointer 1	40	.tcos: resp 1
47	.tsin: pointer 1	41	.tsin: resp 1
48	endstruc	42	endstruc
49		43
50	SECTION_RODATA	44	SECTION_RODATA
Lines 73-84 cextern cos_ %+ i Link Here
73	%assign i i<<1	67	%assign i i<<1
74	%endrep	68	%endrep
75		69
76	%ifdef ARCH_X86_64
77	%define pointer dq
78	%else
79	%define pointer dd
80	%endif
81
82	%macro IF0 1+	70	%macro IF0 1+
83	%endmacro	71	%endmacro
84	%macro IF1 1+	72	%macro IF1 1+
Lines 584-590 DECL_PASS pass_interleave_3dn, PASS_BIG 0 Link Here
584		572
585	%macro FFT_DISPATCH 2; clobbers 5 GPRs, 8 XMMs	573	%macro FFT_DISPATCH 2; clobbers 5 GPRs, 8 XMMs
586	lea r2, [dispatch_tab%1]	574	lea r2, [dispatch_tab%1]
587	mov r2, [r2 + (%2q-2)*gprsize]	575	mov r2p, [r2 + (%2q-2)*ptrsize]
588	%ifdef PIC	576	%ifdef PIC
589	lea r3, [$$]	577	lea r3, [$$]
590	add r2, r3	578	add r2, r3
Lines 624-630 fft %+ n %+ %3%2: Link Here
624	%undef n	612	%undef n
625		613
626	align 8	614	align 8
627	dispatch_tab%3%2: pointer list_of_fft	615	dispatch_tab%3%2: dp list_of_fft
628		616
629	section .text	617	section .text
630		618
Lines 765-772 cglobal imdct_half%1, 3,7,8; FFTContext s, FFTSample output, const FFTSample * Link Here
765	mov r3d, [r0+FFTContext.mdctsize]	753	mov r3d, [r0+FFTContext.mdctsize]
766	add r2, r3	754	add r2, r3
767	shr r3, 1	755	shr r3, 1
768	mov rtcos, [r0+FFTContext.tcos]	756	mov preg(rtcos), [r0+FFTContext.tcos]
769	mov rtsin, [r0+FFTContext.tsin]	757	mov preg(rtsin), [r0+FFTContext.tsin]
770	add rtcos, r3	758	add rtcos, r3
771	add rtsin, r3	759	add rtsin, r3
772	%ifndef ARCH_X86_64	760	%ifndef ARCH_X86_64
Lines 774-780 cglobal imdct_half%1, 3,7,8; FFTContext s, FFTSample output, const FFTSample * Link Here
774	push rtsin	762	push rtsin
775	%endif	763	%endif
776	shr r3, 1	764	shr r3, 1
777	mov rrevtab, [r0+FFTContext.revtab]	765	mov preg(rrevtab), [r0+FFTContext.revtab]
778	add rrevtab, r3	766	add rrevtab, r3
779	%ifndef ARCH_X86_64	767	%ifndef ARCH_X86_64
780	push rrevtab	768	push rrevtab

Lines 122-129 FLOAT_TO_INT16 3dnow, 0 Link Here

(-)a/libavcodec/x86/fmtconvert.asm (-16 / +16 lines)
122	%macro FLOAT_TO_INT16_INTERLEAVE2 1	122	%macro FLOAT_TO_INT16_INTERLEAVE2 1
123	cglobal float_to_int16_interleave2_%1, 3,4,2, dst, src0, src1, len	123	cglobal float_to_int16_interleave2_%1, 3,4,2, dst, src0, src1, len
124	lea lenq, [4*r2q]	124	lea lenq, [4*r2q]
125	mov src1q, [src0q+gprsize]	125	mov src1p, [src0q+ptrsize]
126	mov src0q, [src0q]	126	mov src0p, [src0q]
127	add dstq, lenq	127	add dstq, lenq
128	add src0q, lenq	128	add src0q, lenq
129	add src1q, lenq	129	add src1q, lenq
Lines 186-197 cglobal float_to_int16_interleave6_%1, 2,7,0, dst, src, src1, src2, src3, src4, Link Here
186	%else	186	%else
187	%define lend dword r2m	187	%define lend dword r2m
188	%endif	188	%endif
189	mov src1q, [srcq+1*gprsize]	189	mov src1p, [srcq+1*ptrsize]
190	mov src2q, [srcq+2*gprsize]	190	mov src2p, [srcq+2*ptrsize]
191	mov src3q, [srcq+3*gprsize]	191	mov src3p, [srcq+3*ptrsize]
192	mov src4q, [srcq+4*gprsize]	192	mov src4p, [srcq+4*ptrsize]
193	mov src5q, [srcq+5*gprsize]	193	mov src5p, [srcq+5*ptrsize]
194	mov srcq, [srcq]	194	mov srcp, [srcq]
195	sub src1q, srcq	195	sub src1q, srcq
196	sub src2q, srcq	196	sub src2q, srcq
197	sub src3q, srcq	197	sub src3q, srcq
Lines 247-258 cglobal float_interleave6_%1, 2,7,%2, dst, src, src1, src2, src3, src4, src5 Link Here
247	%else	247	%else
248	%define lend dword r2m	248	%define lend dword r2m
249	%endif	249	%endif
250	mov src1q, [srcq+1*gprsize]	250	mov src1p, [srcq+1*ptrsize]
251	mov src2q, [srcq+2*gprsize]	251	mov src2p, [srcq+2*ptrsize]
252	mov src3q, [srcq+3*gprsize]	252	mov src3p, [srcq+3*ptrsize]
253	mov src4q, [srcq+4*gprsize]	253	mov src4p, [srcq+4*ptrsize]
254	mov src5q, [srcq+5*gprsize]	254	mov src5p, [srcq+5*ptrsize]
255	mov srcq, [srcq]	255	mov srcp, [srcq]
256	sub src1q, srcq	256	sub src1q, srcq
257	sub src2q, srcq	257	sub src2q, srcq
258	sub src3q, srcq	258	sub src3q, srcq
Lines 325-332 FLOAT_INTERLEAVE6 sse, 7 Link Here
325		325
326	%macro FLOAT_INTERLEAVE2 2	326	%macro FLOAT_INTERLEAVE2 2
327	cglobal float_interleave2_%1, 3,4,%2, dst, src, len, src1	327	cglobal float_interleave2_%1, 3,4,%2, dst, src, len, src1
328	mov src1q, [srcq+gprsize]	328	mov src1p, [srcq+ptrsize]
329	mov srcq, [srcq ]	329	mov srcp, [srcq ]
330	sub src1q, srcq	330	sub src1q, srcq
331	.loop	331	.loop
332	MOVPS m0, [srcq ]	332	MOVPS m0, [srcq ]

Lines 24-30 Link Here

(-)a/libavutil/x86_cpu.h (-2 / +18 lines)
24	#include <stdint.h>	24	#include <stdint.h>
25	#include "config.h"	25	#include "config.h"
26		26
27	#if ARCH_X86_64	27	#if ARCH_X86_64_X64
28	# define OPSIZE "q"	28	# define OPSIZE "q"
29	# define REG_a "rax"	29	# define REG_a "rax"
30	# define REG_b "rbx"	30	# define REG_b "rbx"
Lines 32-37 Link Here
32	# define REG_d "rdx"	32	# define REG_d "rdx"
33	# define REG_D "rdi"	33	# define REG_D "rdi"
34	# define REG_S "rsi"	34	# define REG_S "rsi"
		35	# define REG_8 "r8"
35	# define PTR_SIZE "8"	36	# define PTR_SIZE "8"
36	typedef int64_t x86_reg;	37	typedef int64_t x86_reg;
37		38
Lines 43-50 typedef int64_t x86_reg; Link Here
43	# define REGc rcx	44	# define REGc rcx
44	# define REGd rdx	45	# define REGd rdx
45	# define REGSP rsp	46	# define REGSP rsp
		47	# define REG8 r8
46		48
47	#elif ARCH_X86_32	49	#elif ARCH_X86_32 \|\| ARCH_X86_64_X32
48		50
49	# define OPSIZE "l"	51	# define OPSIZE "l"
50	# define REG_a "eax"	52	# define REG_a "eax"
Lines 53-58 typedef int64_t x86_reg; Link Here
53	# define REG_d "edx"	55	# define REG_d "edx"
54	# define REG_D "edi"	56	# define REG_D "edi"
55	# define REG_S "esi"	57	# define REG_S "esi"
		58	# define REG_8 "r8d"
56	# define PTR_SIZE "4"	59	# define PTR_SIZE "4"
57	typedef int32_t x86_reg;	60	typedef int32_t x86_reg;
58		61
Lines 64-73 typedef int32_t x86_reg; Link Here
64	# define REGc ecx	67	# define REGc ecx
65	# define REGd edx	68	# define REGd edx
66	# define REGSP esp	69	# define REGSP esp
		70	# define REG8 r8d
67	#else	71	#else
68	typedef int x86_reg;	72	typedef int x86_reg;
69	#endif	73	#endif
70		74
		75	#if ARCH_X86_64
		76	# define REG_rb "rbx"
		77	# define REG_rS "rsi"
		78	# define REG_rBP "rbp"
		79	typedef int64_t x86_native_reg;
		80	#elif ARCH_X86_32
		81	# define REG_rb "ebx"
		82	# define REG_rS "esi"
		83	# define REG_rBP "ebp"
		84	typedef int32_t x86_native_reg;
		85	#endif
		86
71	#define HAVE_7REGS (ARCH_X86_64 \|\| (HAVE_EBX_AVAILABLE && HAVE_EBP_AVAILABLE))	87	#define HAVE_7REGS (ARCH_X86_64 \|\| (HAVE_EBX_AVAILABLE && HAVE_EBP_AVAILABLE))
72	#define HAVE_6REGS (ARCH_X86_64 \|\| (HAVE_EBX_AVAILABLE \|\| HAVE_EBP_AVAILABLE))	88	#define HAVE_6REGS (ARCH_X86_64 \|\| (HAVE_EBX_AVAILABLE \|\| HAVE_EBP_AVAILABLE))
73		89

Lines 149-162 cglobal yuv2planeX_%1, %3, 7, %2 Link Here

(-)a/libswscale/x86/output.asm (-2 / +2 lines)
149	movsx cntr_reg, r1m	149	movsx cntr_reg, r1m
150	.filterloop_ %+ %%i:	150	.filterloop_ %+ %%i:
151	; input pixels	151	; input pixels
152	mov r6, [r2+gprsizecntr_reg-2gprsize]	152	mov r6p, [r2+ptrsizecntr_reg-2ptrsize]
153	%if %1 == 16	153	%if %1 == 16
154	mova m3, [r6+r5*4]	154	mova m3, [r6+r5*4]
155	mova m5, [r6+r5*4+mmsize]	155	mova m5, [r6+r5*4+mmsize]
156	%else ; %1 == 8/9/10	156	%else ; %1 == 8/9/10
157	mova m3, [r6+r5*2]	157	mova m3, [r6+r5*2]
158	%endif ; %1 == 8/9/10/16	158	%endif ; %1 == 8/9/10/16
159	mov r6, [r2+gprsize*cntr_reg-gprsize]	159	mov r6p, [r2+ptrsize*cntr_reg-ptrsize]
160	%if %1 == 16	160	%if %1 == 16
161	mova m4, [r6+r5*4]	161	mova m4, [r6+r5*4]
162	mova m6, [r6+r5*4+mmsize]	162	mova m6, [r6+r5*4+mmsize]

Lines 774-785 static void RENAME(yuv2rgb32_2)(SwsContext c, const int16_t buf[2], Link Here

(-)a/libswscale/x86/swscale_template.c (-41 / +40 lines)
774	const int16_t abuf0 = abuf[0], abuf1 = abuf[1];	774	const int16_t abuf0 = abuf[0], abuf1 = abuf[1];
775	#if ARCH_X86_64	775	#if ARCH_X86_64
776	__asm__ volatile(	776	__asm__ volatile(
777	YSCALEYUV2RGB(%%r8, %5)	777	YSCALEYUV2RGB(%%REG8, %5)
778	YSCALEYUV2RGB_YA(%%r8, %5, %6, %7)	778	YSCALEYUV2RGB_YA(%%REG8, %5, %6, %7)
779	"psraw $3, %%mm1 \n\t" /* abuf0[eax] - abuf1[eax] >>7*/	779	"psraw $3, %%mm1 \n\t" /* abuf0[eax] - abuf1[eax] >>7*/
780	"psraw $3, %%mm7 \n\t" /* abuf0[eax] - abuf1[eax] >>7*/	780	"psraw $3, %%mm7 \n\t" /* abuf0[eax] - abuf1[eax] >>7*/
781	"packuswb %%mm7, %%mm1 \n\t"	781	"packuswb %%mm7, %%mm1 \n\t"
782	WRITEBGR32(%4, 8280(%5), %%r8, %%mm2, %%mm4, %%mm5, %%mm1, %%mm0, %%mm7, %%mm3, %%mm6)	782	WRITEBGR32(%4, 8280(%5), %%REG8, %%mm2, %%mm4, %%mm5, %%mm1, %%mm0, %%mm7, %%mm3, %%mm6)
783	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "r" (dest),	783	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "r" (dest),
784	"a" (&c->redDither),	784	"a" (&c->redDither),
785	"r" (abuf0), "r" (abuf1)	785	"r" (abuf0), "r" (abuf1)
Lines 791-797 static void RENAME(yuv2rgb32_2)(SwsContext c, const int16_t buf[2], Link Here
791	__asm__ volatile(	791	__asm__ volatile(
792	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	792	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
793	"mov %4, %%"REG_b" \n\t"	793	"mov %4, %%"REG_b" \n\t"
794	"push %%"REG_BP" \n\t"	794	"push %%"REG_rBP" \n\t"
795	YSCALEYUV2RGB(%%REGBP, %5)	795	YSCALEYUV2RGB(%%REGBP, %5)
796	"push %0 \n\t"	796	"push %0 \n\t"
797	"push %1 \n\t"	797	"push %1 \n\t"
Lines 804-810 static void RENAME(yuv2rgb32_2)(SwsContext c, const int16_t buf[2], Link Here
804	"pop %1 \n\t"	804	"pop %1 \n\t"
805	"pop %0 \n\t"	805	"pop %0 \n\t"
806	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm1, %%mm0, %%mm7, %%mm3, %%mm6)	806	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm1, %%mm0, %%mm7, %%mm3, %%mm6)
807	"pop %%"REG_BP" \n\t"	807	"pop %%"REG_rBP" \n\t"
808	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	808	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
809	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	809	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
810	"a" (&c->redDither)	810	"a" (&c->redDither)
Lines 814-824 static void RENAME(yuv2rgb32_2)(SwsContext c, const int16_t buf[2], Link Here
814	__asm__ volatile(	814	__asm__ volatile(
815	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	815	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
816	"mov %4, %%"REG_b" \n\t"	816	"mov %4, %%"REG_b" \n\t"
817	"push %%"REG_BP" \n\t"	817	"push %%"REG_rBP" \n\t"
818	YSCALEYUV2RGB(%%REGBP, %5)	818	YSCALEYUV2RGB(%%REGBP, %5)
819	"pcmpeqd %%mm7, %%mm7 \n\t"	819	"pcmpeqd %%mm7, %%mm7 \n\t"
820	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)	820	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
821	"pop %%"REG_BP" \n\t"	821	"pop %%"REG_rBP" \n\t"
822	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	822	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
823	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	823	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
824	"a" (&c->redDither)	824	"a" (&c->redDither)
Lines 838-848 static void RENAME(yuv2bgr24_2)(SwsContext c, const int16_t buf[2], Link Here
838	__asm__ volatile(	838	__asm__ volatile(
839	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	839	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
840	"mov %4, %%"REG_b" \n\t"	840	"mov %4, %%"REG_b" \n\t"
841	"push %%"REG_BP" \n\t"	841	"push %%"REG_rBP" \n\t"
842	YSCALEYUV2RGB(%%REGBP, %5)	842	YSCALEYUV2RGB(%%REGBP, %5)
843	"pxor %%mm7, %%mm7 \n\t"	843	"pxor %%mm7, %%mm7 \n\t"
844	WRITEBGR24(%%REGb, 8280(%5), %%REGBP)	844	WRITEBGR24(%%REGb, 8280(%5), %%REGBP)
845	"pop %%"REG_BP" \n\t"	845	"pop %%"REG_rBP" \n\t"
846	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	846	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
847	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	847	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
848	"a" (&c->redDither)	848	"a" (&c->redDither)
Lines 861-867 static void RENAME(yuv2rgb555_2)(SwsContext c, const int16_t buf[2], Link Here
861	__asm__ volatile(	861	__asm__ volatile(
862	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	862	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
863	"mov %4, %%"REG_b" \n\t"	863	"mov %4, %%"REG_b" \n\t"
864	"push %%"REG_BP" \n\t"	864	"push %%"REG_rBP" \n\t"
865	YSCALEYUV2RGB(%%REGBP, %5)	865	YSCALEYUV2RGB(%%REGBP, %5)
866	"pxor %%mm7, %%mm7 \n\t"	866	"pxor %%mm7, %%mm7 \n\t"
867	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */	867	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */
Lines 871-877 static void RENAME(yuv2rgb555_2)(SwsContext c, const int16_t buf[2], Link Here
871	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"	871	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"
872	#endif	872	#endif
873	WRITERGB15(%%REGb, 8280(%5), %%REGBP)	873	WRITERGB15(%%REGb, 8280(%5), %%REGBP)
874	"pop %%"REG_BP" \n\t"	874	"pop %%"REG_rBP" \n\t"
875	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	875	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
876	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	876	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
877	"a" (&c->redDither)	877	"a" (&c->redDither)
Lines 890-896 static void RENAME(yuv2rgb565_2)(SwsContext c, const int16_t buf[2], Link Here
890	__asm__ volatile(	890	__asm__ volatile(
891	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	891	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
892	"mov %4, %%"REG_b" \n\t"	892	"mov %4, %%"REG_b" \n\t"
893	"push %%"REG_BP" \n\t"	893	"push %%"REG_rBP" \n\t"
894	YSCALEYUV2RGB(%%REGBP, %5)	894	YSCALEYUV2RGB(%%REGBP, %5)
895	"pxor %%mm7, %%mm7 \n\t"	895	"pxor %%mm7, %%mm7 \n\t"
896	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */	896	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */
Lines 900-906 static void RENAME(yuv2rgb565_2)(SwsContext c, const int16_t buf[2], Link Here
900	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"	900	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"
901	#endif	901	#endif
902	WRITERGB16(%%REGb, 8280(%5), %%REGBP)	902	WRITERGB16(%%REGb, 8280(%5), %%REGBP)
903	"pop %%"REG_BP" \n\t"	903	"pop %%"REG_rBP" \n\t"
904	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	904	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
905	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	905	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
906	"a" (&c->redDither)	906	"a" (&c->redDither)
Lines 959-968 static void RENAME(yuv2yuyv422_2)(SwsContext c, const int16_t buf[2], Link Here
959	__asm__ volatile(	959	__asm__ volatile(
960	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	960	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
961	"mov %4, %%"REG_b" \n\t"	961	"mov %4, %%"REG_b" \n\t"
962	"push %%"REG_BP" \n\t"	962	"push %%"REG_rBP" \n\t"
963	YSCALEYUV2PACKED(%%REGBP, %5)	963	YSCALEYUV2PACKED(%%REGBP, %5)
964	WRITEYUY2(%%REGb, 8280(%5), %%REGBP)	964	WRITEYUY2(%%REGb, 8280(%5), %%REGBP)
965	"pop %%"REG_BP" \n\t"	965	"pop %%"REG_rBP" \n\t"
966	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	966	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
967	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	967	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
968	"a" (&c->redDither)	968	"a" (&c->redDither)
Lines 1100-1110 static void RENAME(yuv2rgb32_1)(SwsContext c, const int16_t buf0, Link Here
1100	__asm__ volatile(	1100	__asm__ volatile(
1101	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1101	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1102	"mov %4, %%"REG_b" \n\t"	1102	"mov %4, %%"REG_b" \n\t"
1103	"push %%"REG_BP" \n\t"	1103	"push %%"REG_rBP" \n\t"
1104	YSCALEYUV2RGB1(%%REGBP, %5)	1104	YSCALEYUV2RGB1(%%REGBP, %5)
1105	YSCALEYUV2RGB1_ALPHA(%%REGBP)	1105	YSCALEYUV2RGB1_ALPHA(%%REGBP)
1106	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)	1106	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
1107	"pop %%"REG_BP" \n\t"	1107	"pop %%"REG_rBP" \n\t"
1108	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1108	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1109	:: "c" (buf0), "d" (abuf0), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1109	:: "c" (buf0), "d" (abuf0), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1110	"a" (&c->redDither)	1110	"a" (&c->redDither)
Lines 1113-1123 static void RENAME(yuv2rgb32_1)(SwsContext c, const int16_t buf0, Link Here
1113	__asm__ volatile(	1113	__asm__ volatile(
1114	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1114	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1115	"mov %4, %%"REG_b" \n\t"	1115	"mov %4, %%"REG_b" \n\t"
1116	"push %%"REG_BP" \n\t"	1116	"push %%"REG_rBP" \n\t"
1117	YSCALEYUV2RGB1(%%REGBP, %5)	1117	YSCALEYUV2RGB1(%%REGBP, %5)
1118	"pcmpeqd %%mm7, %%mm7 \n\t"	1118	"pcmpeqd %%mm7, %%mm7 \n\t"
1119	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)	1119	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
1120	"pop %%"REG_BP" \n\t"	1120	"pop %%"REG_rBP" \n\t"
1121	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1121	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1122	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1122	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1123	"a" (&c->redDither)	1123	"a" (&c->redDither)
Lines 1128-1138 static void RENAME(yuv2rgb32_1)(SwsContext c, const int16_t buf0, Link Here
1128	__asm__ volatile(	1128	__asm__ volatile(
1129	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1129	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1130	"mov %4, %%"REG_b" \n\t"	1130	"mov %4, %%"REG_b" \n\t"
1131	"push %%"REG_BP" \n\t"	1131	"push %%"REG_rBP" \n\t"
1132	YSCALEYUV2RGB1b(%%REGBP, %5)	1132	YSCALEYUV2RGB1b(%%REGBP, %5)
1133	YSCALEYUV2RGB1_ALPHA(%%REGBP)	1133	YSCALEYUV2RGB1_ALPHA(%%REGBP)
1134	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)	1134	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
1135	"pop %%"REG_BP" \n\t"	1135	"pop %%"REG_rBP" \n\t"
1136	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1136	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1137	:: "c" (buf0), "d" (abuf0), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1137	:: "c" (buf0), "d" (abuf0), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1138	"a" (&c->redDither)	1138	"a" (&c->redDither)
Lines 1141-1151 static void RENAME(yuv2rgb32_1)(SwsContext c, const int16_t buf0, Link Here
1141	__asm__ volatile(	1141	__asm__ volatile(
1142	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1142	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1143	"mov %4, %%"REG_b" \n\t"	1143	"mov %4, %%"REG_b" \n\t"
1144	"push %%"REG_BP" \n\t"	1144	"push %%"REG_rBP" \n\t"
1145	YSCALEYUV2RGB1b(%%REGBP, %5)	1145	YSCALEYUV2RGB1b(%%REGBP, %5)
1146	"pcmpeqd %%mm7, %%mm7 \n\t"	1146	"pcmpeqd %%mm7, %%mm7 \n\t"
1147	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)	1147	WRITEBGR32(%%REGb, 8280(%5), %%REGBP, %%mm2, %%mm4, %%mm5, %%mm7, %%mm0, %%mm1, %%mm3, %%mm6)
1148	"pop %%"REG_BP" \n\t"	1148	"pop %%"REG_rBP" \n\t"
1149	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1149	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1150	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1150	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1151	"a" (&c->redDither)	1151	"a" (&c->redDither)
Lines 1166-1176 static void RENAME(yuv2bgr24_1)(SwsContext c, const int16_t buf0, Link Here
1166	__asm__ volatile(	1166	__asm__ volatile(
1167	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1167	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1168	"mov %4, %%"REG_b" \n\t"	1168	"mov %4, %%"REG_b" \n\t"
1169	"push %%"REG_BP" \n\t"	1169	"push %%"REG_rBP" \n\t"
1170	YSCALEYUV2RGB1(%%REGBP, %5)	1170	YSCALEYUV2RGB1(%%REGBP, %5)
1171	"pxor %%mm7, %%mm7 \n\t"	1171	"pxor %%mm7, %%mm7 \n\t"
1172	WRITEBGR24(%%REGb, 8280(%5), %%REGBP)	1172	WRITEBGR24(%%REGb, 8280(%5), %%REGBP)
1173	"pop %%"REG_BP" \n\t"	1173	"pop %%"REG_rBP" \n\t"
1174	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1174	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1175	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1175	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1176	"a" (&c->redDither)	1176	"a" (&c->redDither)
Lines 1179-1189 static void RENAME(yuv2bgr24_1)(SwsContext c, const int16_t buf0, Link Here
1179	__asm__ volatile(	1179	__asm__ volatile(
1180	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1180	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1181	"mov %4, %%"REG_b" \n\t"	1181	"mov %4, %%"REG_b" \n\t"
1182	"push %%"REG_BP" \n\t"	1182	"push %%"REG_rBP" \n\t"
1183	YSCALEYUV2RGB1b(%%REGBP, %5)	1183	YSCALEYUV2RGB1b(%%REGBP, %5)
1184	"pxor %%mm7, %%mm7 \n\t"	1184	"pxor %%mm7, %%mm7 \n\t"
1185	WRITEBGR24(%%REGb, 8280(%5), %%REGBP)	1185	WRITEBGR24(%%REGb, 8280(%5), %%REGBP)
1186	"pop %%"REG_BP" \n\t"	1186	"pop %%"REG_rBP" \n\t"
1187	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1187	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1188	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1188	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1189	"a" (&c->redDither)	1189	"a" (&c->redDither)
Lines 1203-1209 static void RENAME(yuv2rgb555_1)(SwsContext c, const int16_t buf0, Link Here
1203	__asm__ volatile(	1203	__asm__ volatile(
1204	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1204	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1205	"mov %4, %%"REG_b" \n\t"	1205	"mov %4, %%"REG_b" \n\t"
1206	"push %%"REG_BP" \n\t"	1206	"push %%"REG_rBP" \n\t"
1207	YSCALEYUV2RGB1(%%REGBP, %5)	1207	YSCALEYUV2RGB1(%%REGBP, %5)
1208	"pxor %%mm7, %%mm7 \n\t"	1208	"pxor %%mm7, %%mm7 \n\t"
1209	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */	1209	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */
Lines 1213-1219 static void RENAME(yuv2rgb555_1)(SwsContext c, const int16_t buf0, Link Here
1213	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"	1213	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"
1214	#endif	1214	#endif
1215	WRITERGB15(%%REGb, 8280(%5), %%REGBP)	1215	WRITERGB15(%%REGb, 8280(%5), %%REGBP)
1216	"pop %%"REG_BP" \n\t"	1216	"pop %%"REG_rBP" \n\t"
1217	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1217	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1218	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1218	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1219	"a" (&c->redDither)	1219	"a" (&c->redDither)
Lines 1222-1228 static void RENAME(yuv2rgb555_1)(SwsContext c, const int16_t buf0, Link Here
1222	__asm__ volatile(	1222	__asm__ volatile(
1223	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1223	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1224	"mov %4, %%"REG_b" \n\t"	1224	"mov %4, %%"REG_b" \n\t"
1225	"push %%"REG_BP" \n\t"	1225	"push %%"REG_rBP" \n\t"
1226	YSCALEYUV2RGB1b(%%REGBP, %5)	1226	YSCALEYUV2RGB1b(%%REGBP, %5)
1227	"pxor %%mm7, %%mm7 \n\t"	1227	"pxor %%mm7, %%mm7 \n\t"
1228	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */	1228	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */
Lines 1232-1238 static void RENAME(yuv2rgb555_1)(SwsContext c, const int16_t buf0, Link Here
1232	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"	1232	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"
1233	#endif	1233	#endif
1234	WRITERGB15(%%REGb, 8280(%5), %%REGBP)	1234	WRITERGB15(%%REGb, 8280(%5), %%REGBP)
1235	"pop %%"REG_BP" \n\t"	1235	"pop %%"REG_rBP" \n\t"
1236	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1236	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1237	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1237	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1238	"a" (&c->redDither)	1238	"a" (&c->redDither)
Lines 1252-1258 static void RENAME(yuv2rgb565_1)(SwsContext c, const int16_t buf0, Link Here
1252	__asm__ volatile(	1252	__asm__ volatile(
1253	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1253	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1254	"mov %4, %%"REG_b" \n\t"	1254	"mov %4, %%"REG_b" \n\t"
1255	"push %%"REG_BP" \n\t"	1255	"push %%"REG_rBP" \n\t"
1256	YSCALEYUV2RGB1(%%REGBP, %5)	1256	YSCALEYUV2RGB1(%%REGBP, %5)
1257	"pxor %%mm7, %%mm7 \n\t"	1257	"pxor %%mm7, %%mm7 \n\t"
1258	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */	1258	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */
Lines 1262-1268 static void RENAME(yuv2rgb565_1)(SwsContext c, const int16_t buf0, Link Here
1262	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"	1262	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"
1263	#endif	1263	#endif
1264	WRITERGB16(%%REGb, 8280(%5), %%REGBP)	1264	WRITERGB16(%%REGb, 8280(%5), %%REGBP)
1265	"pop %%"REG_BP" \n\t"	1265	"pop %%"REG_rBP" \n\t"
1266	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1266	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1267	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1267	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1268	"a" (&c->redDither)	1268	"a" (&c->redDither)
Lines 1271-1277 static void RENAME(yuv2rgb565_1)(SwsContext c, const int16_t buf0, Link Here
1271	__asm__ volatile(	1271	__asm__ volatile(
1272	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1272	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1273	"mov %4, %%"REG_b" \n\t"	1273	"mov %4, %%"REG_b" \n\t"
1274	"push %%"REG_BP" \n\t"	1274	"push %%"REG_rBP" \n\t"
1275	YSCALEYUV2RGB1b(%%REGBP, %5)	1275	YSCALEYUV2RGB1b(%%REGBP, %5)
1276	"pxor %%mm7, %%mm7 \n\t"	1276	"pxor %%mm7, %%mm7 \n\t"
1277	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */	1277	/* mm2=B, %%mm4=G, %%mm5=R, %%mm7=0 */
Lines 1281-1287 static void RENAME(yuv2rgb565_1)(SwsContext c, const int16_t buf0, Link Here
1281	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"	1281	"paddusb "RED_DITHER"(%5), %%mm5 \n\t"
1282	#endif	1282	#endif
1283	WRITERGB16(%%REGb, 8280(%5), %%REGBP)	1283	WRITERGB16(%%REGb, 8280(%5), %%REGBP)
1284	"pop %%"REG_BP" \n\t"	1284	"pop %%"REG_rBP" \n\t"
1285	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1285	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1286	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1286	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1287	"a" (&c->redDither)	1287	"a" (&c->redDither)
Lines 1338-1347 static void RENAME(yuv2yuyv422_1)(SwsContext c, const int16_t buf0, Link Here
1338	__asm__ volatile(	1338	__asm__ volatile(
1339	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1339	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1340	"mov %4, %%"REG_b" \n\t"	1340	"mov %4, %%"REG_b" \n\t"
1341	"push %%"REG_BP" \n\t"	1341	"push %%"REG_rBP" \n\t"
1342	YSCALEYUV2PACKED1(%%REGBP, %5)	1342	YSCALEYUV2PACKED1(%%REGBP, %5)
1343	WRITEYUY2(%%REGb, 8280(%5), %%REGBP)	1343	WRITEYUY2(%%REGb, 8280(%5), %%REGBP)
1344	"pop %%"REG_BP" \n\t"	1344	"pop %%"REG_rBP" \n\t"
1345	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1345	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1346	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1346	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1347	"a" (&c->redDither)	1347	"a" (&c->redDither)
Lines 1350-1359 static void RENAME(yuv2yuyv422_1)(SwsContext c, const int16_t buf0, Link Here
1350	__asm__ volatile(	1350	__asm__ volatile(
1351	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"	1351	"mov %%"REG_b", "ESP_OFFSET"(%5) \n\t"
1352	"mov %4, %%"REG_b" \n\t"	1352	"mov %4, %%"REG_b" \n\t"
1353	"push %%"REG_BP" \n\t"	1353	"push %%"REG_rBP" \n\t"
1354	YSCALEYUV2PACKED1b(%%REGBP, %5)	1354	YSCALEYUV2PACKED1b(%%REGBP, %5)
1355	WRITEYUY2(%%REGb, 8280(%5), %%REGBP)	1355	WRITEYUY2(%%REGb, 8280(%5), %%REGBP)
1356	"pop %%"REG_BP" \n\t"	1356	"pop %%"REG_rBP" \n\t"
1357	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"	1357	"mov "ESP_OFFSET"(%5), %%"REG_b" \n\t"
1358	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),	1358	:: "c" (buf0), "d" (buf1), "S" (ubuf0), "D" (ubuf1), "m" (dest),
1359	"a" (&c->redDither)	1359	"a" (&c->redDither)
Lines 1510-1516 static void RENAME(hyscale_fast)(SwsContext c, int16_t dst, Link Here
1510	{	1510	{
1511	int32_t *filterPos = c->hLumFilterPos;	1511	int32_t *filterPos = c->hLumFilterPos;
1512	int16_t *filter = c->hLumFilter;	1512	int16_t *filter = c->hLumFilter;
1513	void *mmx2FilterCode= c->lumMmx2FilterCode;	1513	x86_native_reg mmx2FilterCode = (uintptr_t)c->lumMmx2FilterCode;
1514	int i;	1514	int i;
1515	#if defined(PIC)	1515	#if defined(PIC)
1516	uint64_t ebxsave;	1516	uint64_t ebxsave;
1517	-