[patch] 2700_pegasos-2.6.6.patch

2700_pegasos-2.6.6.patch (text/plain), 12.18 KB, created by David Holm (RETIRED) on 2004-06-21 13:37:23 UTC

diff -urN kernel-source-2.6.5/arch/ppc/platforms/chrp_pci.c kernel-source-2.6.5-powerpc/arch/ppc/platforms/chrp_pci.c
--- kernel-source-2.6.5/arch/ppc/platforms/chrp_pci.c	2003-06-17 06:20:27.000000000 +0200
+++ kernel-source-2.6.5-powerpc/arch/ppc/platforms/chrp_pci.c	2004-04-12 23:43:57.495852656 +0200
@@ -97,8 +97,9 @@
 rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
 		 int len, u32 *val)
 {
+	struct pci_controller *hose = bus->sysdata;
 	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
-		| ((bus->number & 0xff) << 16);
+		| (((bus->number - hose->first_busno) & 0xff) << 16) | (pci_domain_nr(bus) << 24);
         unsigned long ret = ~0UL;
 	int rval;
 
@@ -111,8 +112,9 @@
 rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
 		  int len, u32 val)
 {
+	struct pci_controller *hose = bus->sysdata;
 	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
-		| ((bus->number & 0xff) << 16);
+		| (((bus->number - hose->first_busno) & 0xff) << 16) | (pci_domain_nr(bus) << 24);
 	int rval;
 
 	rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
@@ -186,6 +188,170 @@
 	iounmap(reg);
 }
 
+/* Marvell Discovery II based Pegasos 2 */
+volatile unsigned int *peg2_magic_agp_f118;
+volatile unsigned int *peg2_magic_agp_f11c;
+
+int __chrp peg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
+			   int len, u32 *val)
+{
+	volatile unsigned char *cfg_data;
+	struct pci_controller *hose = bus->sysdata;
+	u32 msr; 
+
+	/* We can read only on function 0 offset 0 to 15 on device 0) */
+	if (bus->number == hose->first_busno) {
+		if (devfn == 0) {
+			if (off > 15) {
+				* val = (u32) 0;
+				return PCIBIOS_SUCCESSFUL;
+			}
+		} else if ((devfn >> 3) == 0)
+			return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/* Magic fix for the agp bus */
+	if (hose->index == 1) {
+		/* Disable cpu interrupts */
+		msr = mfmsr();
+		mtmsr(msr & ~MSR_EE);
+		/* Enable PCI -> AGP idsel mapping */
+		out_be32 (peg2_magic_agp_f118, 0x8000);
+	}
+
+	out_le32 (hose->cfg_addr,
+		0x80000000 | ((bus->number - hose->first_busno) << 16) | (devfn << 8) | (off & 0xfc)); 
+	/*
+	 * Note: the caller has already checked that off is
+	 * suitably aligned and that len is 1, 2 or 4.
+	 */
+	cfg_data = hose->cfg_data + (off & 3);
+	switch (len) {
+	case 1:
+		*val =  in_8((u8 *)cfg_data);
+		break;
+	case 2:
+		*val = in_le16((u16 *)cfg_data);
+		break;
+	default:
+		*val = in_le32((u32 *)cfg_data);
+		break;
+	}
+	/* Magic fix for the agp bus */
+	if (hose->index == 1) {
+		/* Disable PCI -> AGP idsel mapping */
+		out_be32 (peg2_magic_agp_f11c, 0x8000);
+		/* Enable cpu interrupts */
+		mtmsr(msr);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+int __chrp peg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
+			    int len, u32 val)
+{
+	volatile unsigned char *cfg_data;
+	struct pci_controller *hose = bus->sysdata;
+	u32 msr; 
+
+	/* We ignore writes to device 0 */
+	/*if (bus->number == 0) */
+	if (bus->number == hose->first_busno) {
+		if (devfn == 0)
+			return PCIBIOS_SUCCESSFUL;
+		else if ((devfn >> 3) == 0)
+			return PCIBIOS_DEVICE_NOT_FOUND;
+	}
+
+	/* Magic fix for the agp bus */
+	if (hose->index == 1) {
+		/* Disable cpu interrupts */
+		msr = mfmsr();
+		mtmsr(msr & ~MSR_EE);
+		/* Enable PCI -> AGP idsel mapping */
+		out_be32 (peg2_magic_agp_f118, 0x8000);
+	}
+
+	out_le32 (hose->cfg_addr,
+		0x80000000 | ((bus->number - hose->first_busno) << 16) | (devfn << 8) | (off & 0xfc)); 
+	/*
+	 * Note: the caller has already checked that off is
+	 * suitably aligned and that len is 1, 2 or 4.
+	 */
+	cfg_data = hose->cfg_data + (off & 3);
+	switch (len) {
+	case 1:
+		out_8((u8 *)cfg_data, val);
+		break;
+	case 2:
+		out_le16((u16 *)cfg_data, val);
+		break;
+	default:
+		out_le32((u32 *)cfg_data, val);
+		break;
+	}
+	/* Magic fix for the agp bus */
+	if (hose->index == 1) {
+		/* Disable PCI -> AGP idsel mapping */
+		out_be32 (peg2_magic_agp_f11c, 0x8000);
+		/* Enable cpu interrupts */
+		mtmsr(msr);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static struct pci_ops peg2_pci_ops =
+{
+	peg2_read_config,
+	peg2_write_config
+};
+
+#define PEGASOS_USE_RTAS 
+//#define PEGASOS_USE_PCI_DOMAINS
+
+static void __init
+setup_peg2(struct pci_controller *hose, struct device_node *dev)
+{
+	unsigned long base = 0xf1000c78 & PAGE_MASK;
+	char *mbase;
+	unsigned long magic_agp_base = 0xf100f118 & PAGE_MASK;
+	char *magic_agp_mbase;
+#ifdef PEGASOS_USE_RTAS
+	struct device_node *root = find_path_device("/");
+	struct device_node *rtas;
+
+	rtas = of_find_node_by_name (root, "rtas");
+	if (rtas) {
+		hose->ops = &rtas_pci_ops;
+		printk ("Pegasos OF RTAS support detected, using it\n");
+	} else {
+		printk ("Pegasos OF doesn't support RTAS, please upgrade it\n");
+#else
+	{
+#endif
+		if (strncmp(dev->full_name, "/pci@80000000", 13) == 0) {
+			mbase = ioremap (base, PAGE_SIZE);
+			hose->cfg_addr = (unsigned int *) (mbase + (0xf1000c78 & ~PAGE_MASK));
+			hose->cfg_data = (unsigned char *) (mbase + (0xf1000c7c & ~PAGE_MASK));
+			hose->ops = &peg2_pci_ops;
+		} else if (strncmp(dev->full_name, "/pci@C0000000", 13) == 0) {
+			mbase = ioremap (base, PAGE_SIZE);
+			hose->cfg_addr = (unsigned int *) (mbase + (0xf1000cf8 & ~PAGE_MASK));
+			hose->cfg_data = (unsigned char *) (mbase + (0xf1000cfc & ~PAGE_MASK));
+			hose->ops = &peg2_pci_ops;
+			magic_agp_mbase = ioremap (magic_agp_base, PAGE_SIZE);
+			peg2_magic_agp_f118 = (unsigned int *) (magic_agp_mbase + (0xf100f118 & ~PAGE_MASK));
+			peg2_magic_agp_f11c = (unsigned int *) (magic_agp_mbase + (0xf100f1c8 & ~PAGE_MASK));
+		} else
+			printk("Pegasos 2 unknown pci bridge detected %s, type %s, full name %s at %08x, ints %d\n",
+				dev->name, dev->type, dev->full_name, dev->n_addrs, dev->n_intrs);
+	}
+#ifndef PEGASOS_USE_PCI_DOMAINS
+	pci_assign_all_busses = 1;
+#endif
+}
+
 void __init
 chrp_find_bridges(void)
 {
@@ -195,7 +361,7 @@
 	struct pci_controller *hose;
 	unsigned int *dma;
 	char *model, *machine;
-	int is_longtrail = 0, is_mot = 0;
+	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
 	struct device_node *root = find_path_device("/");
 
 	/*
@@ -207,6 +373,8 @@
 	if (machine != NULL) {
 		is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
 		is_mot = strncmp(machine, "MOT", 3) == 0;
+		if (strncmp(machine, "Pegasos2", 8) == 0) is_pegasos = 2;
+		else if (strncmp(machine, "Pegasos", 7) == 0) is_pegasos = 1;
 	}
 	for (dev = root->child; dev != NULL; dev = dev->sibling) {
 		if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
@@ -257,6 +425,10 @@
 			hose->cfg_data = (unsigned char *)
 				ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
 			gg2_pci_config_base = (unsigned long) hose->cfg_data;
+		} else if (is_pegasos == 1) {
+			setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
+		} else if (is_pegasos == 2) {
+			setup_peg2(hose, dev);
 		} else {
 			printk("No methods for %s (model %s), using RTAS\n",
 			       dev->full_name, model);
@@ -274,6 +446,9 @@
 			printk("pci_dram_offset = %lx\n", pci_dram_offset);
 		}
 	}
-
-	ppc_md.pcibios_fixup = chrp_pcibios_fixup;
+	
+	if (is_pegasos)
+		ppc_md.pcibios_fixup = NULL;
+	else
+		ppc_md.pcibios_fixup = chrp_pcibios_fixup;
 }
diff -urN kernel-source-2.6.5/arch/ppc/platforms/chrp_setup.c kernel-source-2.6.5-powerpc/arch/ppc/platforms/chrp_setup.c
--- kernel-source-2.6.5/arch/ppc/platforms/chrp_setup.c	2003-09-28 06:44:11.000000000 +0200
+++ kernel-source-2.6.5-powerpc/arch/ppc/platforms/chrp_setup.c	2004-04-12 23:43:19.915565728 +0200
@@ -214,6 +214,37 @@
 	}
 }
 
+void pegasos_set_l2cr(void)
+{
+	struct device_node *root = find_path_device("/");
+	char *machine;
+	struct device_node *np;
+	int l2cr_value;
+
+	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
+	if (root == NULL)
+		return;
+	machine = get_property(root, "model", NULL);
+	if (machine == NULL)
+		return;
+	if (strncmp(machine, "Pegasos", 7) == 0) {
+		/* Enable L2 cache if needed */
+		np = find_type_devices("cpu");
+		if (np != NULL) {
+			unsigned int *l2cr = (unsigned int *)
+				get_property (np, "l2cr", NULL);
+			if (l2cr == NULL) {
+				printk ("Pegasos l2cr : no cpu l2cr property found\n");
+				return;
+			}
+			if (!((*l2cr) & 0x80000000)) {
+				printk ("Pegasos l2cr : L2 cache was not active, activating\n");
+				_set_L2CR(0);
+				_set_L2CR((*l2cr) | 0x80000000);
+			}
+		}
+	}
+}
 
 void __init
 chrp_setup_arch(void)
@@ -236,6 +267,9 @@
 	/* Lookup PCI host bridges */
 	chrp_find_bridges();
 
+	/* On pegasos, enable the L2 cache if not already done by OF */
+	pegasos_set_l2cr();
+
 #ifndef CONFIG_PPC64BRIDGE
 	/*
 	 *  Temporary fixes for PCI devices.
@@ -387,6 +421,8 @@
 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
 	struct device_node *kbd;
 #endif
+	struct device_node *root = find_path_device ("/");
+	char *machine;
 
 	for (np = find_devices("pci"); np != NULL; np = np->next) {
 		unsigned int *addrp = (unsigned int *)
@@ -400,6 +400,18 @@
 	if (np == NULL)
 		printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
 
+	machine = get_property(root, "model", NULL);
+	if (strncmp(machine, "Pegasos", 7) == 0) {
+		for (i = 0; i < NUM_8259_INTERRUPTS; i++) {
+			if (i<16) {
+				/* byte access */
+				unsigned int port = 0x4d0 + (i >> 3);
+				/* ask HW directly */
+				irq_desc[i].status |= (((inb(port) >> (i & 7)) & 1) ? IRQ_LEVEL : 0 );
+			}
+			irq_desc[i].handler = &i8259_pic;
+		}
+	} else {
 	chrp_find_openpic();
 
 	prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
@@ -413,6 +425,7 @@
 
 	for (i = 0; i < NUM_8259_INTERRUPTS; i++)
 		irq_desc[i].handler = &i8259_pic;
+	}
 	i8259_init(chrp_int_ack);
 
 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
@@ -450,6 +499,8 @@
 chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
 	  unsigned long r6, unsigned long r7)
 {
+	struct device_node *root = find_path_device ("/");
+	char *machine;
 #ifdef CONFIG_BLK_DEV_INITRD
 	/* take care of initrd if we have one */
 	if ( r6 )
@@ -469,7 +520,11 @@
 	ppc_md.show_cpuinfo   = chrp_show_cpuinfo;
 	ppc_md.irq_canonicalize = chrp_irq_canonicalize;
 	ppc_md.init_IRQ       = chrp_init_IRQ;
-	ppc_md.get_irq        = openpic_get_irq;
+	machine = get_property(root, "model", NULL);
+	if (strncmp(machine, "Pegasos", 7) == 0)
+		ppc_md.get_irq        = i8259_irq;
+	else
+		ppc_md.get_irq        = openpic_get_irq;
 
 	ppc_md.init           = chrp_init2;
 
diff -urN kernel-source-2.6.5/arch/ppc/platforms/chrp_time.c kernel-source-2.6.5-powerpc/arch/ppc/platforms/chrp_time.c
--- kernel-source-2.6.5/arch/ppc/platforms/chrp_time.c	2003-09-28 06:44:11.000000000 +0200
+++ kernel-source-2.6.5-powerpc/arch/ppc/platforms/chrp_time.c	2004-04-12 23:43:19.915565728 +0200
@@ -41,6 +41,8 @@
 	int base;
 
 	rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
+	if (rtcs == NULL)
+		rtcs = find_compatible_devices("rtc", "ds1385-rtc");
 	if (rtcs == NULL || rtcs->addrs == NULL)
 		return 0;
 	base = rtcs->addrs[0].address;
diff -urN kernel-source-2.6.5/arch/ppc/syslib/prom_init.c kernel-source-2.6.5-powerpc/arch/ppc/syslib/prom_init.c
--- kernel-source-2.6.5/arch/ppc/syslib/prom_init.c	2004-02-19 09:54:39.000000000 +0100
+++ kernel-source-2.6.5-powerpc/arch/ppc/syslib/prom_init.c	2004-04-12 23:43:19.949560560 +0200
@@ -794,6 +794,9 @@
 	char *p, *d;
  	unsigned long phys;
 	void *result[3];
+	char model[32];
+	phandle node;
+	int rc;
 
  	/* Default */
  	phys = (unsigned long) &_stext;
@@ -881,6 +884,10 @@
 	for (i = 0; i < prom_num_displays; ++i)
 		prom_display_paths[i] = PTRUNRELOC(prom_display_paths[i]);
 
+	node = call_prom("finddevice", 1, 1, "/");
+	rc = call_prom("getprop", 4, 1, node, "model", model, sizeof(model));
+	if (rc > 0 && !strncmp (model, "Pegasos", 7)) phys = 0x00010000;
+
 	prom_print("returning 0x");
 	prom_print_hex(phys);
 	prom_print("from prom_init\n");
diff -urN kernel-source-2.6.5/drivers/ide/pci/via82cxxx.c kernel-source-2.6.5-powerpc/drivers/ide/pci/via82cxxx.c
--- kernel-source-2.6.5/drivers/ide/pci/via82cxxx.c	2004-04-05 12:54:35.000000000 +0200
+++ kernel-source-2.6.5-powerpc/drivers/ide/pci/via82cxxx.c	2004-04-12 23:43:19.967557824 +0200
@@ -583,6 +583,8 @@
 	hwif->tuneproc = &via82cxxx_tune_drive;
 	hwif->speedproc = &via_set_drive;
 
+	hwif->irq = hwif->channel ? 15 : 14;
+
 	for (i = 0; i < 2; i++) {
 		hwif->drives[i].io_32bit = 1;
 		hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;