Attachment #33770 for bug #54684




rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
		 int len, u32 *val)
{
	struct pci_controller *hose = bus->sysdata;
	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
		| (((bus->number - hose->first_busno) & 0xff) << 16) | (pci_domain_nr(bus) << 24);
        unsigned long ret = ~0UL;
	int rval;


rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
		  int len, u32 val)
{
	struct pci_controller *hose = bus->sysdata;
	unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
		| (((bus->number - hose->first_busno) & 0xff) << 16) | (pci_domain_nr(bus) << 24);
	int rval;

	rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);

	iounmap(reg);
}

/* Marvell Discovery II based Pegasos 2 */
volatile unsigned int *peg2_magic_agp_f118;
volatile unsigned int *peg2_magic_agp_f11c;

int __chrp peg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
			   int len, u32 *val)
{
	volatile unsigned char *cfg_data;
	struct pci_controller *hose = bus->sysdata;
	u32 msr; 

	/* We can read only on function 0 offset 0 to 15 on device 0) */
	if (bus->number == hose->first_busno) {
		if (devfn == 0) {
			if (off > 15) {
				* val = (u32) 0;
				return PCIBIOS_SUCCESSFUL;
			}
		} else if ((devfn >> 3) == 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/* Magic fix for the agp bus */
	if (hose->index == 1) {
		/* Disable cpu interrupts */
		msr = mfmsr();
		mtmsr(msr & ~MSR_EE);
		/* Enable PCI -> AGP idsel mapping */
		out_be32 (peg2_magic_agp_f118, 0x8000);
	}

	out_le32 (hose->cfg_addr,
		0x80000000 | ((bus->number - hose->first_busno) << 16) | (devfn << 8) | (off & 0xfc)); 
	/*
	 * Note: the caller has already checked that off is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + (off & 3);
	switch (len) {
	case 1:
		*val =  in_8((u8 *)cfg_data);
		break;
	case 2:
		*val = in_le16((u16 *)cfg_data);
		break;
	default:
		*val = in_le32((u32 *)cfg_data);
		break;
	}
	/* Magic fix for the agp bus */
	if (hose->index == 1) {
		/* Disable PCI -> AGP idsel mapping */
		out_be32 (peg2_magic_agp_f11c, 0x8000);
		/* Enable cpu interrupts */
		mtmsr(msr);
	}
	return PCIBIOS_SUCCESSFUL;
}

int __chrp peg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
			    int len, u32 val)
{
	volatile unsigned char *cfg_data;
	struct pci_controller *hose = bus->sysdata;
	u32 msr; 

	/* We ignore writes to device 0 */
	/*if (bus->number == 0) */
	if (bus->number == hose->first_busno) {
		if (devfn == 0)
			return PCIBIOS_SUCCESSFUL;
		else if ((devfn >> 3) == 0)
			return PCIBIOS_DEVICE_NOT_FOUND;
	}

	/* Magic fix for the agp bus */
	if (hose->index == 1) {
		/* Disable cpu interrupts */
		msr = mfmsr();
		mtmsr(msr & ~MSR_EE);
		/* Enable PCI -> AGP idsel mapping */
		out_be32 (peg2_magic_agp_f118, 0x8000);
	}

	out_le32 (hose->cfg_addr,
		0x80000000 | ((bus->number - hose->first_busno) << 16) | (devfn << 8) | (off & 0xfc)); 
	/*
	 * Note: the caller has already checked that off is
	 * suitably aligned and that len is 1, 2 or 4.
	 */
	cfg_data = hose->cfg_data + (off & 3);
	switch (len) {
	case 1:
		out_8((u8 *)cfg_data, val);
		break;
	case 2:
		out_le16((u16 *)cfg_data, val);
		break;
	default:
		out_le32((u32 *)cfg_data, val);
		break;
	}
	/* Magic fix for the agp bus */
	if (hose->index == 1) {
		/* Disable PCI -> AGP idsel mapping */
		out_be32 (peg2_magic_agp_f11c, 0x8000);
		/* Enable cpu interrupts */
		mtmsr(msr);
	}
	return PCIBIOS_SUCCESSFUL;
}


static struct pci_ops peg2_pci_ops =
{
	peg2_read_config,
	peg2_write_config
};

#define PEGASOS_USE_RTAS 
//#define PEGASOS_USE_PCI_DOMAINS

static void __init
setup_peg2(struct pci_controller *hose, struct device_node *dev)
{
	unsigned long base = 0xf1000c78 & PAGE_MASK;
	char *mbase;
	unsigned long magic_agp_base = 0xf100f118 & PAGE_MASK;
	char *magic_agp_mbase;
#ifdef PEGASOS_USE_RTAS
	struct device_node *root = find_path_device("/");
	struct device_node *rtas;

	rtas = of_find_node_by_name (root, "rtas");
	if (rtas) {
		hose->ops = &rtas_pci_ops;
		printk ("Pegasos OF RTAS support detected, using it\n");
	} else {
		printk ("Pegasos OF doesn't support RTAS, please upgrade it\n");
#else
	{
#endif
		if (strncmp(dev->full_name, "/pci@80000000", 13) == 0) {
			mbase = ioremap (base, PAGE_SIZE);
			hose->cfg_addr = (unsigned int *) (mbase + (0xf1000c78 & ~PAGE_MASK));
			hose->cfg_data = (unsigned char *) (mbase + (0xf1000c7c & ~PAGE_MASK));
			hose->ops = &peg2_pci_ops;
		} else if (strncmp(dev->full_name, "/pci@C0000000", 13) == 0) {
			mbase = ioremap (base, PAGE_SIZE);
			hose->cfg_addr = (unsigned int *) (mbase + (0xf1000cf8 & ~PAGE_MASK));
			hose->cfg_data = (unsigned char *) (mbase + (0xf1000cfc & ~PAGE_MASK));
			hose->ops = &peg2_pci_ops;
			magic_agp_mbase = ioremap (magic_agp_base, PAGE_SIZE);
			peg2_magic_agp_f118 = (unsigned int *) (magic_agp_mbase + (0xf100f118 & ~PAGE_MASK));
			peg2_magic_agp_f11c = (unsigned int *) (magic_agp_mbase + (0xf100f1c8 & ~PAGE_MASK));
		} else
			printk("Pegasos 2 unknown pci bridge detected %s, type %s, full name %s at %08x, ints %d\n",
				dev->name, dev->type, dev->full_name, dev->n_addrs, dev->n_intrs);
	}
#ifndef PEGASOS_USE_PCI_DOMAINS
	pci_assign_all_busses = 1;
#endif
}

void __init
chrp_find_bridges(void)
{

	struct pci_controller *hose;
	unsigned int *dma;
	char *model, *machine;
	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
	struct device_node *root = find_path_device("/");

	/*

	if (machine != NULL) {
		is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
		is_mot = strncmp(machine, "MOT", 3) == 0;
		if (strncmp(machine, "Pegasos2", 8) == 0) is_pegasos = 2;
		else if (strncmp(machine, "Pegasos", 7) == 0) is_pegasos = 1;
	}
	for (dev = root->child; dev != NULL; dev = dev->sibling) {
		if (dev->type == NULL || strcmp(dev->type, "pci") != 0)

			hose->cfg_data = (unsigned char *)
				ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
			gg2_pci_config_base = (unsigned long) hose->cfg_data;
		} else if (is_pegasos == 1) {
			setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
		} else if (is_pegasos == 2) {
			setup_peg2(hose, dev);
		} else {
			printk("No methods for %s (model %s), using RTAS\n",
			       dev->full_name, model);

			printk("pci_dram_offset = %lx\n", pci_dram_offset);
		}
	}
	
	if (is_pegasos)
		ppc_md.pcibios_fixup = NULL;
	else
		ppc_md.pcibios_fixup = chrp_pcibios_fixup;
}




	}
}

void pegasos_set_l2cr(void)
{
	struct device_node *root = find_path_device("/");
	char *machine;
	struct device_node *np;
	int l2cr_value;

	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
	if (root == NULL)
		return;
	machine = get_property(root, "model", NULL);
	if (machine == NULL)
		return;
	if (strncmp(machine, "Pegasos", 7) == 0) {
		/* Enable L2 cache if needed */
		np = find_type_devices("cpu");
		if (np != NULL) {
			unsigned int *l2cr = (unsigned int *)
				get_property (np, "l2cr", NULL);
			if (l2cr == NULL) {
				printk ("Pegasos l2cr : no cpu l2cr property found\n");
				return;
			}
			if (!((*l2cr) & 0x80000000)) {
				printk ("Pegasos l2cr : L2 cache was not active, activating\n");
				_set_L2CR(0);
				_set_L2CR((*l2cr) | 0x80000000);
			}
		}
	}
}

void __init
chrp_setup_arch(void)

	/* Lookup PCI host bridges */
	chrp_find_bridges();

	/* On pegasos, enable the L2 cache if not already done by OF */
	pegasos_set_l2cr();

#ifndef CONFIG_PPC64BRIDGE
	/*
	 *  Temporary fixes for PCI devices.

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
	struct device_node *kbd;
#endif
	struct device_node *root = find_path_device ("/");
	char *machine;

	for (np = find_devices("pci"); np != NULL; np = np->next) {
		unsigned int *addrp = (unsigned int *)

	if (np == NULL)
		printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");

	machine = get_property(root, "model", NULL);
	if (strncmp(machine, "Pegasos", 7) == 0) {
		for (i = 0; i < NUM_8259_INTERRUPTS; i++) {
			if (i<16) {
				/* byte access */
				unsigned int port = 0x4d0 + (i >> 3);
				/* ask HW directly */
				irq_desc[i].status |= (((inb(port) >> (i & 7)) & 1) ? IRQ_LEVEL : 0 );
			}
			irq_desc[i].handler = &i8259_pic;
		}
	} else {
	chrp_find_openpic();

	prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);


	for (i = 0; i < NUM_8259_INTERRUPTS; i++)
		irq_desc[i].handler = &i8259_pic;
	}
	i8259_init(chrp_int_ack);

#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)

chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
	  unsigned long r6, unsigned long r7)
{
	struct device_node *root = find_path_device ("/");
	char *machine;
#ifdef CONFIG_BLK_DEV_INITRD
	/* take care of initrd if we have one */
	if ( r6 )

	ppc_md.show_cpuinfo   = chrp_show_cpuinfo;
	ppc_md.irq_canonicalize = chrp_irq_canonicalize;
	ppc_md.init_IRQ       = chrp_init_IRQ;
	machine = get_property(root, "model", NULL);
	if (strncmp(machine, "Pegasos", 7) == 0)
		ppc_md.get_irq        = i8259_irq;
	else
		ppc_md.get_irq        = openpic_get_irq;

	ppc_md.init           = chrp_init2;


Lines 41-46 Link Here

(-)kernel-source-2.6.5/arch/ppc/platforms/chrp_time.c (+2 lines)
41	int base;	41	int base;
42		42
43	rtcs = find_compatible_devices("rtc", "pnpPNP,b00");	43	rtcs = find_compatible_devices("rtc", "pnpPNP,b00");
		44	if (rtcs == NULL)
		45	rtcs = find_compatible_devices("rtc", "ds1385-rtc");
44	if (rtcs == NULL \|\| rtcs->addrs == NULL)	46	if (rtcs == NULL \|\| rtcs->addrs == NULL)
45	return 0;	47	return 0;
46	base = rtcs->addrs[0].address;	48	base = rtcs->addrs[0].address;

Lines 794-799 Link Here

(-)kernel-source-2.6.5/arch/ppc/syslib/prom_init.c (+7 lines)
794	char p, d;	794	char p, d;
795	unsigned long phys;	795	unsigned long phys;
796	void *result[3];	796	void *result[3];
		797	char model[32];
		798	phandle node;
		799	int rc;
797		800
798	/* Default */	801	/* Default */
799	phys = (unsigned long) &_stext;	802	phys = (unsigned long) &_stext;
Lines 881-886 Link Here
881	for (i = 0; i < prom_num_displays; ++i)	884	for (i = 0; i < prom_num_displays; ++i)
882	prom_display_paths[i] = PTRUNRELOC(prom_display_paths[i]);	885	prom_display_paths[i] = PTRUNRELOC(prom_display_paths[i]);
883		886
		887	node = call_prom("finddevice", 1, 1, "/");
		888	rc = call_prom("getprop", 4, 1, node, "model", model, sizeof(model));
		889	if (rc > 0 && !strncmp (model, "Pegasos", 7)) phys = 0x00010000;
		890
884	prom_print("returning 0x");	891	prom_print("returning 0x");
885	prom_print_hex(phys);	892	prom_print_hex(phys);
886	prom_print("from prom_init\n");	893	prom_print("from prom_init\n");

Lines 583-588 Link Here

(-)kernel-source-2.6.5/drivers/ide/pci/via82cxxx.c (+2 lines)
583	hwif->tuneproc = &via82cxxx_tune_drive;	583	hwif->tuneproc = &via82cxxx_tune_drive;
584	hwif->speedproc = &via_set_drive;	584	hwif->speedproc = &via_set_drive;
585		585
		586	hwif->irq = hwif->channel ? 15 : 14;
		587
586	for (i = 0; i < 2; i++) {	588	for (i = 0; i < 2; i++) {
587	hwif->drives[i].io_32bit = 1;	589	hwif->drives[i].io_32bit = 1;
588	hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;	590	hwif->drives[i].unmask = (via_config->flags & VIA_NO_UNMASK) ? 0 : 1;

Return to bug 54684

Lines 214-219 Link Here

(-)kernel-source-2.6.5/arch/ppc/platforms/chrp_setup.c (-1 / +56 lines)
214	}	214	}
215	}	215	}
216		216
		217	void pegasos_set_l2cr(void)
		218	{
		219	struct device_node *root = find_path_device("/");
		220	char *machine;
		221	struct device_node *np;
		222	int l2cr_value;
		223
		224	/* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
		225	if (root == NULL)
		226	return;
		227	machine = get_property(root, "model", NULL);
		228	if (machine == NULL)
		229	return;
		230	if (strncmp(machine, "Pegasos", 7) == 0) {
		231	/* Enable L2 cache if needed */
		232	np = find_type_devices("cpu");
		233	if (np != NULL) {
		234	unsigned int l2cr = (unsigned int )
		235	get_property (np, "l2cr", NULL);
		236	if (l2cr == NULL) {
		237	printk ("Pegasos l2cr : no cpu l2cr property found\n");
		238	return;
		239	}
		240	if (!((*l2cr) & 0x80000000)) {
		241	printk ("Pegasos l2cr : L2 cache was not active, activating\n");
		242	_set_L2CR(0);
		243	_set_L2CR((*l2cr) \| 0x80000000);
		244	}
		245	}
		246	}
		247	}
217		248
218	void __init	249	void __init
219	chrp_setup_arch(void)	250	chrp_setup_arch(void)
Lines 236-241 Link Here
236	/* Lookup PCI host bridges */	267	/* Lookup PCI host bridges */
237	chrp_find_bridges();	268	chrp_find_bridges();
238		269
		270	/* On pegasos, enable the L2 cache if not already done by OF */
		271	pegasos_set_l2cr();
		272
239	#ifndef CONFIG_PPC64BRIDGE	273	#ifndef CONFIG_PPC64BRIDGE
240	/*	274	/*
241	* Temporary fixes for PCI devices.	275	* Temporary fixes for PCI devices.
Lines 387-392 Link Here
387	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)	421	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
388	struct device_node *kbd;	422	struct device_node *kbd;
389	#endif	423	#endif
		424	struct device_node *root = find_path_device ("/");
		425	char *machine;
390		426
391	for (np = find_devices("pci"); np != NULL; np = np->next) {	427	for (np = find_devices("pci"); np != NULL; np = np->next) {
392	unsigned int addrp = (unsigned int )	428	unsigned int addrp = (unsigned int )
Lines 400-405 Link Here
400	if (np == NULL)	400	if (np == NULL)
401	printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");	401	printk(KERN_ERR "Cannot find PCI interrupt acknowledge address\n");
402		402
		403	machine = get_property(root, "model", NULL);
		404	if (strncmp(machine, "Pegasos", 7) == 0) {
		405	for (i = 0; i < NUM_8259_INTERRUPTS; i++) {
		406	if (i<16) {
		407	/* byte access */
		408	unsigned int port = 0x4d0 + (i >> 3);
		409	/* ask HW directly */
		410	irq_desc[i].status \|= (((inb(port) >> (i & 7)) & 1) ? IRQ_LEVEL : 0 );
		411	}
		412	irq_desc[i].handler = &i8259_pic;
		413	}
		414	} else {
403	chrp_find_openpic();	415	chrp_find_openpic();
404		416
405	prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);	417	prom_get_irq_senses(init_senses, NUM_8259_INTERRUPTS, NR_IRQS);
Lines 413-418 Link Here
413		425
414	for (i = 0; i < NUM_8259_INTERRUPTS; i++)	426	for (i = 0; i < NUM_8259_INTERRUPTS; i++)
415	irq_desc[i].handler = &i8259_pic;	427	irq_desc[i].handler = &i8259_pic;
		428	}
416	i8259_init(chrp_int_ack);	429	i8259_init(chrp_int_ack);
417		430
418	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)	431	#if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(XMON)
Lines 450-455 Link Here
450	chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,	499	chrp_init(unsigned long r3, unsigned long r4, unsigned long r5,
451	unsigned long r6, unsigned long r7)	500	unsigned long r6, unsigned long r7)
452	{	501	{
		502	struct device_node *root = find_path_device ("/");
		503	char *machine;
453	#ifdef CONFIG_BLK_DEV_INITRD	504	#ifdef CONFIG_BLK_DEV_INITRD
454	/* take care of initrd if we have one */	505	/* take care of initrd if we have one */
455	if ( r6 )	506	if ( r6 )
Lines 469-475 Link Here
469	ppc_md.show_cpuinfo = chrp_show_cpuinfo;	520	ppc_md.show_cpuinfo = chrp_show_cpuinfo;
470	ppc_md.irq_canonicalize = chrp_irq_canonicalize;	521	ppc_md.irq_canonicalize = chrp_irq_canonicalize;
471	ppc_md.init_IRQ = chrp_init_IRQ;	522	ppc_md.init_IRQ = chrp_init_IRQ;
472	ppc_md.get_irq = openpic_get_irq;	523	machine = get_property(root, "model", NULL);
		524	if (strncmp(machine, "Pegasos", 7) == 0)
		525	ppc_md.get_irq = i8259_irq;
		526	else
		527	ppc_md.get_irq = openpic_get_irq;
473		528
474	ppc_md.init = chrp_init2;	529	ppc_md.init = chrp_init2;
475		530

Lines 97-104 Link Here

(-)kernel-source-2.6.5/arch/ppc/platforms/chrp_pci.c (-5 / +180 lines)
97	rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,	97	rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
98	int len, u32 *val)	98	int len, u32 *val)
99	{	99	{
		100	struct pci_controller *hose = bus->sysdata;
100	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)	101	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
101	\| ((bus->number & 0xff) << 16);	102	\| (((bus->number - hose->first_busno) & 0xff) << 16) \| (pci_domain_nr(bus) << 24);
102	unsigned long ret = ~0UL;	103	unsigned long ret = ~0UL;
103	int rval;	104	int rval;
104		105
Lines 111-118 Link Here
111	rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,	112	rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
112	int len, u32 val)	113	int len, u32 val)
113	{	114	{
		115	struct pci_controller *hose = bus->sysdata;
114	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)	116	unsigned long addr = (offset & 0xff) \| ((devfn & 0xff) << 8)
115	\| ((bus->number & 0xff) << 16);	117	\| (((bus->number - hose->first_busno) & 0xff) << 16) \| (pci_domain_nr(bus) << 24);
116	int rval;	118	int rval;
117		119
118	rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);	120	rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
Lines 186-191 Link Here
186	iounmap(reg);	188	iounmap(reg);
187	}	189	}
188		190
		191	/* Marvell Discovery II based Pegasos 2 */
		192	volatile unsigned int *peg2_magic_agp_f118;
		193	volatile unsigned int *peg2_magic_agp_f11c;
		194
		195	int __chrp peg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
		196	int len, u32 *val)
		197	{
		198	volatile unsigned char *cfg_data;
		199	struct pci_controller *hose = bus->sysdata;
		200	u32 msr;
		201
		202	/* We can read only on function 0 offset 0 to 15 on device 0) */
		203	if (bus->number == hose->first_busno) {
		204	if (devfn == 0) {
		205	if (off > 15) {
		206	* val = (u32) 0;
		207	return PCIBIOS_SUCCESSFUL;
		208	}
		209	} else if ((devfn >> 3) == 0)
		210	return PCIBIOS_DEVICE_NOT_FOUND;
		211	}
		212
		213	/* Magic fix for the agp bus */
		214	if (hose->index == 1) {
		215	/* Disable cpu interrupts */
		216	msr = mfmsr();
		217	mtmsr(msr & ~MSR_EE);
		218	/* Enable PCI -> AGP idsel mapping */
		219	out_be32 (peg2_magic_agp_f118, 0x8000);
		220	}
		221
		222	out_le32 (hose->cfg_addr,
		223	0x80000000 \| ((bus->number - hose->first_busno) << 16) \| (devfn << 8) \| (off & 0xfc));
		224	/*
		225	* Note: the caller has already checked that off is
		226	* suitably aligned and that len is 1, 2 or 4.
		227	*/
		228	cfg_data = hose->cfg_data + (off & 3);
		229	switch (len) {
		230	case 1:
		231	val = in_8((u8 )cfg_data);
		232	break;
		233	case 2:
		234	val = in_le16((u16 )cfg_data);
		235	break;
		236	default:
		237	val = in_le32((u32 )cfg_data);
		238	break;
		239	}
		240	/* Magic fix for the agp bus */
		241	if (hose->index == 1) {
		242	/* Disable PCI -> AGP idsel mapping */
		243	out_be32 (peg2_magic_agp_f11c, 0x8000);
		244	/* Enable cpu interrupts */
		245	mtmsr(msr);
		246	}
		247	return PCIBIOS_SUCCESSFUL;
		248	}
		249
		250	int __chrp peg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
		251	int len, u32 val)
		252	{
		253	volatile unsigned char *cfg_data;
		254	struct pci_controller *hose = bus->sysdata;
255	u32 msr;
256
257	/* We ignore writes to device 0 */
258	/if (bus->number == 0) /
259	if (bus->number == hose->first_busno) {
260	if (devfn == 0)
261	return PCIBIOS_SUCCESSFUL;
262	else if ((devfn >> 3) == 0)
263	return PCIBIOS_DEVICE_NOT_FOUND;
264	}
265
266	/* Magic fix for the agp bus */
267	if (hose->index == 1) {
268	/* Disable cpu interrupts */
269	msr = mfmsr();
270	mtmsr(msr & ~MSR_EE);
271	/* Enable PCI -> AGP idsel mapping */
272	out_be32 (peg2_magic_agp_f118, 0x8000);
273	}
274
275	out_le32 (hose->cfg_addr,
276	0x80000000 \| ((bus->number - hose->first_busno) << 16) \| (devfn << 8) \| (off & 0xfc));
277	/*
278	* Note: the caller has already checked that off is
279	* suitably aligned and that len is 1, 2 or 4.
280	*/
281	cfg_data = hose->cfg_data + (off & 3);
282	switch (len) {
283	case 1:
284	out_8((u8 *)cfg_data, val);
285	break;
286	case 2:
287	out_le16((u16 *)cfg_data, val);
288	break;
289	default:
290	out_le32((u32 *)cfg_data, val);
291	break;
292	}
293	/* Magic fix for the agp bus */
294	if (hose->index == 1) {
295	/* Disable PCI -> AGP idsel mapping */
296	out_be32 (peg2_magic_agp_f11c, 0x8000);
297	/* Enable cpu interrupts */
298	mtmsr(msr);
299	}
300	return PCIBIOS_SUCCESSFUL;
301	}
302
303
304	static struct pci_ops peg2_pci_ops =
305	{
306	peg2_read_config,
307	peg2_write_config
308	};
309
310	#define PEGASOS_USE_RTAS
311	//#define PEGASOS_USE_PCI_DOMAINS
312
313	static void __init
314	setup_peg2(struct pci_controller hose, struct device_node dev)
315	{
316	unsigned long base = 0xf1000c78 & PAGE_MASK;
317	char *mbase;
318	unsigned long magic_agp_base = 0xf100f118 & PAGE_MASK;
319	char *magic_agp_mbase;
320	#ifdef PEGASOS_USE_RTAS
321	struct device_node *root = find_path_device("/");
322	struct device_node *rtas;
323
324	rtas = of_find_node_by_name (root, "rtas");
325	if (rtas) {
326	hose->ops = &rtas_pci_ops;
327	printk ("Pegasos OF RTAS support detected, using it\n");
328	} else {
329	printk ("Pegasos OF doesn't support RTAS, please upgrade it\n");
330	#else
331	{
332	#endif
333	if (strncmp(dev->full_name, "/pci@80000000", 13) == 0) {
334	mbase = ioremap (base, PAGE_SIZE);
335	hose->cfg_addr = (unsigned int *) (mbase + (0xf1000c78 & ~PAGE_MASK));
336	hose->cfg_data = (unsigned char *) (mbase + (0xf1000c7c & ~PAGE_MASK));
337	hose->ops = &peg2_pci_ops;
338	} else if (strncmp(dev->full_name, "/pci@C0000000", 13) == 0) {
339	mbase = ioremap (base, PAGE_SIZE);
340	hose->cfg_addr = (unsigned int *) (mbase + (0xf1000cf8 & ~PAGE_MASK));
341	hose->cfg_data = (unsigned char *) (mbase + (0xf1000cfc & ~PAGE_MASK));
342	hose->ops = &peg2_pci_ops;
343	magic_agp_mbase = ioremap (magic_agp_base, PAGE_SIZE);
344	peg2_magic_agp_f118 = (unsigned int *) (magic_agp_mbase + (0xf100f118 & ~PAGE_MASK));
345	peg2_magic_agp_f11c = (unsigned int *) (magic_agp_mbase + (0xf100f1c8 & ~PAGE_MASK));
346	} else
347	printk("Pegasos 2 unknown pci bridge detected %s, type %s, full name %s at %08x, ints %d\n",
348	dev->name, dev->type, dev->full_name, dev->n_addrs, dev->n_intrs);
349	}
350	#ifndef PEGASOS_USE_PCI_DOMAINS
351	pci_assign_all_busses = 1;
352	#endif
353	}
354
189	void __init	355	void __init
190	chrp_find_bridges(void)	356	chrp_find_bridges(void)
191	{	357	{
Lines 195-201 Link Here
195	struct pci_controller *hose;	361	struct pci_controller *hose;
196	unsigned int *dma;	362	unsigned int *dma;
197	char model, machine;	363	char model, machine;
198	int is_longtrail = 0, is_mot = 0;	364	int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
199	struct device_node *root = find_path_device("/");	365	struct device_node *root = find_path_device("/");
200		366
201	/*	367	/*
Lines 207-212 Link Here
207	if (machine != NULL) {	373	if (machine != NULL) {
208	is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;	374	is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
209	is_mot = strncmp(machine, "MOT", 3) == 0;	375	is_mot = strncmp(machine, "MOT", 3) == 0;
		376	if (strncmp(machine, "Pegasos2", 8) == 0) is_pegasos = 2;
		377	else if (strncmp(machine, "Pegasos", 7) == 0) is_pegasos = 1;
210	}	378	}
211	for (dev = root->child; dev != NULL; dev = dev->sibling) {	379	for (dev = root->child; dev != NULL; dev = dev->sibling) {
212	if (dev->type == NULL \|\| strcmp(dev->type, "pci") != 0)	380	if (dev->type == NULL \|\| strcmp(dev->type, "pci") != 0)
Lines 257-262 Link Here
257	hose->cfg_data = (unsigned char *)	425	hose->cfg_data = (unsigned char *)
258	ioremap(GG2_PCI_CONFIG_BASE, 0x80000);	426	ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
259	gg2_pci_config_base = (unsigned long) hose->cfg_data;	427	gg2_pci_config_base = (unsigned long) hose->cfg_data;
		428	} else if (is_pegasos == 1) {
		429	setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
		430	} else if (is_pegasos == 2) {
		431	setup_peg2(hose, dev);
260	} else {	432	} else {
261	printk("No methods for %s (model %s), using RTAS\n",	433	printk("No methods for %s (model %s), using RTAS\n",
262	dev->full_name, model);	434	dev->full_name, model);
Lines 274-279 Link Here
274	printk("pci_dram_offset = %lx\n", pci_dram_offset);	446	printk("pci_dram_offset = %lx\n", pci_dram_offset);
275	}	447	}
276	}	448	}
277		449
278	ppc_md.pcibios_fixup = chrp_pcibios_fixup;	450	if (is_pegasos)
		451	ppc_md.pcibios_fixup = NULL;
		452	else
		453	ppc_md.pcibios_fixup = chrp_pcibios_fixup;
279	}	454	}