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/***************************************************************************\ |
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|* *| |
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|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| |
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|* *| |
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|* NOTICE TO USER: The source code is copyrighted under U.S. and *| |
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|* international laws. Users and possessors of this source code are *| |
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|* hereby granted a nonexclusive, royalty-free copyright license to *| |
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|* use this code in individual and commercial software. *| |
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|* *| |
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|* Any use of this source code must include, in the user documenta- *| |
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|* tion and internal comments to the code, notices to the end user *| |
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|* as follows: *| |
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|* *| |
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|* Copyright 1993-1998 NVIDIA, Corporation. All rights reserved. *| |
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|* *| |
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|* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *| |
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|* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *| |
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|* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *| |
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|* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *| |
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|* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *| |
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|* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *| |
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|* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *| |
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|* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *| |
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|* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *| |
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|* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *| |
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|* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *| |
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|* *| |
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|* U.S. Government End Users. This source code is a "commercial *| |
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|* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *| |
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|* consisting of "commercial computer software" and "commercial *| |
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|* computer software documentation," as such terms are used in *| |
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|* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *| |
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|* ment only as a commercial end item. Consistent with 48 C.F.R. *| |
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|* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *| |
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|* all U.S. Government End Users acquire the source code with only *| |
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|* those rights set forth herein. *| |
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|* *| |
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\***************************************************************************/ |
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|
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/* |
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* GPL licensing note -- nVidia is allowing a liberal interpretation of |
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* the documentation restriction above, to merely say that this nVidia's |
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* copyright and disclaimer should be included with all code derived |
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* from this source. -- Jeff Garzik <jgarzik@mandrakesoft.com>, 01/Nov/99 |
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*/ |
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|
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/***************************************************************************\ |
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|* Modified 1999 by Fredrik Reite (fredrik@reite.com) *| |
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\***************************************************************************/ |
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#ifndef __NV4REF_H__ |
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#define __NV4REF_H__ |
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|
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/* Magic values to lock/unlock extended regs */ |
56 |
#define NV_CIO_SR_LOCK_INDEX 0x0000001F /* */ |
57 |
#define NV_CIO_SR_UNLOCK_RW_VALUE 0x00000057 /* */ |
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#define NV_CIO_SR_UNLOCK_RO_VALUE 0x00000075 /* */ |
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#define NV_CIO_SR_LOCK_VALUE 0x00000099 /* */ |
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|
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#define UNLOCK_EXT_MAGIC 0x57 |
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#define LOCK_EXT_MAGIC 0x99 /* Any value other than 0x57 will do */ |
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|
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#define LOCK_EXT_INDEX 0x6 |
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|
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#define NV_PCRTC_HORIZ_TOTAL 0x00 |
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#define NV_PCRTC_HORIZ_DISPLAY_END 0x01 |
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#define NV_PCRTC_HORIZ_BLANK_START 0x02 |
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|
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#define NV_PCRTC_HORIZ_BLANK_END 0x03 |
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#define NV_PCRTC_HORIZ_BLANK_END_EVRA 7:7 |
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#define NV_PCRTC_HORIZ_BLANK_END_DISPLAY_END_SKEW 6:5 |
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#define NV_PCRTC_HORIZ_BLANK_END_HORIZ_BLANK_END 4:0 |
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|
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#define NV_PCRTC_HORIZ_RETRACE_START 0x04 |
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|
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#define NV_PCRTC_HORIZ_RETRACE_END 0x05 |
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#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_BLANK_END_5 7:7 |
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#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_SKEW 6:5 |
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#define NV_PCRTC_HORIZ_RETRACE_END_HORIZ_RETRACE_END 4:0 |
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|
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#define NV_PCRTC_VERT_TOTAL 0x06 |
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|
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#define NV_PCRTC_OVERFLOW 0x07 |
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#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_9 7:7 |
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#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_9 6:6 |
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#define NV_PCRTC_OVERFLOW_VERT_TOTAL_9 5:5 |
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#define NV_PCRTC_OVERFLOW_LINE_COMPARE_8 4:4 |
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#define NV_PCRTC_OVERFLOW_VERT_BLANK_START_8 3:3 |
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#define NV_PCRTC_OVERFLOW_VERT_RETRACE_START_8 2:2 |
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#define NV_PCRTC_OVERFLOW_VERT_DISPLAY_END_8 1:1 |
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#define NV_PCRTC_OVERFLOW_VERT_TOTAL_8 0:0 |
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|
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#define NV_PCRTC_PRESET_ROW_SCAN 0x08 |
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|
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#define NV_PCRTC_MAX_SCAN_LINE 0x09 |
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#define NV_PCRTC_MAX_SCAN_LINE_DOUBLE_SCAN 7:7 |
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#define NV_PCRTC_MAX_SCAN_LINE_LINE_COMPARE_9 6:6 |
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#define NV_PCRTC_MAX_SCAN_LINE_VERT_BLANK_START_9 5:5 |
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#define NV_PCRTC_MAX_SCAN_LINE_MAX_SCAN_LINE 4:0 |
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|
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#define NV_PCRTC_CURSOR_START 0x0A |
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#define NV_PCRTC_CURSOR_END 0x0B |
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#define NV_PCRTC_START_ADDR_HIGH 0x0C |
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#define NV_PCRTC_START_ADDR_LOW 0x0D |
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#define NV_PCRTC_CURSOR_LOCATION_HIGH 0x0E |
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#define NV_PCRTC_CURSOR_LOCATION_LOW 0x0F |
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|
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#define NV_PCRTC_VERT_RETRACE_START 0x10 |
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#define NV_PCRTC_VERT_RETRACE_END 0x11 |
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#define NV_PCRTC_VERT_DISPLAY_END 0x12 |
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#define NV_PCRTC_OFFSET 0x13 |
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#define NV_PCRTC_UNDERLINE_LOCATION 0x14 |
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#define NV_PCRTC_VERT_BLANK_START 0x15 |
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#define NV_PCRTC_VERT_BLANK_END 0x16 |
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#define NV_PCRTC_MODE_CONTROL 0x17 |
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#define NV_PCRTC_LINE_COMPARE 0x18 |
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|
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/* Extended offset and start address */ |
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#define NV_PCRTC_REPAINT0 0x19 |
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#define NV_PCRTC_REPAINT0_OFFSET_10_8 7:5 |
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#define NV_PCRTC_REPAINT0_START_ADDR_20_16 4:0 |
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|
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/* Horizonal extended bits */ |
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#define NV_PCRTC_HORIZ_EXTRA 0x2d |
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#define NV_PCRTC_HORIZ_EXTRA_INTER_HALF_START_8 4:4 |
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#define NV_PCRTC_HORIZ_EXTRA_HORIZ_RETRACE_START_8 3:3 |
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#define NV_PCRTC_HORIZ_EXTRA_HORIZ_BLANK_START_8 2:2 |
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#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 1:1 |
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#define NV_PCRTC_HORIZ_EXTRA_DISPLAY_TOTAL_8 0:0 |
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|
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/* Assorted extra bits */ |
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#define NV_PCRTC_EXTRA 0x25 |
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#define NV_PCRTC_EXTRA_OFFSET_11 5:5 |
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#define NV_PCRTC_EXTRA_HORIZ_BLANK_END_6 4:4 |
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#define NV_PCRTC_EXTRA_VERT_BLANK_START_10 3:3 |
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#define NV_PCRTC_EXTRA_VERT_RETRACE_START_10 2:2 |
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#define NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 1:1 |
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#define NV_PCRTC_EXTRA_VERT_TOTAL_10 0:0 |
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|
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/* Controls how much data the refresh fifo requests */ |
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#define NV_PCRTC_FIFO_CONTROL 0x1b |
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#define NV_PCRTC_FIFO_CONTROL_UNDERFLOW_WARN 7:7 |
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#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH 2:0 |
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#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_8 0x0 |
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#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_32 0x1 |
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#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_64 0x2 |
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#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_128 0x3 |
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#define NV_PCRTC_FIFO_CONTROL_BURST_LENGTH_256 0x4 |
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|
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/* When the fifo occupancy falls below *twice* the watermark, |
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* the refresh fifo will start to be refilled. If this value is |
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* too low, you will get junk on the screen. Too high, and performance |
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* will suffer. Watermark in units of 8 bytes |
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*/ |
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#define NV_PCRTC_FIFO 0x20 |
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#define NV_PCRTC_FIFO_RESET 7:7 |
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#define NV_PCRTC_FIFO_WATERMARK 5:0 |
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|
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/* Various flags */ |
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#define NV_PCRTC_REPAINT1 0x1a |
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#define NV_PCRTC_REPAINT1_HSYNC 7:7 |
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#define NV_PCRTC_REPAINT1_HYSNC_DISABLE 0x01 |
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#define NV_PCRTC_REPAINT1_HYSNC_ENABLE 0x00 |
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#define NV_PCRTC_REPAINT1_VSYNC 6:6 |
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#define NV_PCRTC_REPAINT1_VYSNC_DISABLE 0x01 |
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#define NV_PCRTC_REPAINT1_VYSNC_ENABLE 0x00 |
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#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT 4:4 |
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#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_ENABLE 0x01 |
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#define NV_PCRTC_REPAINT1_COMPATIBLE_TEXT_DISABLE 0x00 |
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#define NV_PCRTC_REPAINT1_LARGE_SCREEN 2:2 |
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#define NV_PCRTC_REPAINT1_LARGE_SCREEN_DISABLE 0x01 |
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#define NV_PCRTC_REPAINT1_LARGE_SCREEN_ENABLE 0x00 /* >=1280 */ |
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#define NV_PCRTC_REPAINT1_PALETTE_WIDTH 1:1 |
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#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_8BITS 0x00 |
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#define NV_PCRTC_REPAINT1_PALETTE_WIDTH_6BITS 0x01 |
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|
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#define NV_PCRTC_GRCURSOR0 0x30 |
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#define NV_PCRTC_GRCURSOR0_START_ADDR_21_16 5:0 |
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|
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#define NV_PCRTC_GRCURSOR1 0x31 |
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#define NV_PCRTC_GRCURSOR1_START_ADDR_15_11 7:3 |
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#define NV_PCRTC_GRCURSOR1_SCAN_DBL 1:1 |
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#define NV_PCRTC_GRCURSOR1_SCAN_DBL_DISABLE 0 |
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#define NV_PCRTC_GRCURSOR1_SCAN_DBL_ENABLE 1 |
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#define NV_PCRTC_GRCURSOR1_CURSOR 0:0 |
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#define NV_PCRTC_GRCURSOR1_CURSOR_DISABLE 0 |
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#define NV_PCRTC_GRCURSOR1_CURSOR_ENABLE 1 |
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|
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/* Controls what the format of the framebuffer is */ |
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#define NV_PCRTC_PIXEL 0x28 |
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#define NV_PCRTC_PIXEL_MODE 7:7 |
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#define NV_PCRTC_PIXEL_MODE_TV 0x01 |
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#define NV_PCRTC_PIXEL_MODE_VGA 0x00 |
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#define NV_PCRTC_PIXEL_TV_MODE 6:6 |
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#define NV_PCRTC_PIXEL_TV_MODE_NTSC 0x00 |
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#define NV_PCRTC_PIXEL_TV_MODE_PAL 0x01 |
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#define NV_PCRTC_PIXEL_TV_HORIZ_ADJUST 5:3 |
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#define NV_PCRTC_PIXEL_FORMAT 1:0 |
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#define NV_PCRTC_PIXEL_FORMAT_VGA 0x00 |
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#define NV_PCRTC_PIXEL_FORMAT_8BPP 0x01 |
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#define NV_PCRTC_PIXEL_FORMAT_16BPP 0x02 |
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#define NV_PCRTC_PIXEL_FORMAT_32BPP 0x03 |
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|
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/* RAMDAC registers and fields */ |
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#define NV_PRAMDAC 0x00680FFF:0x00680000 /* RW--D */ |
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#define NV_PRAMDAC_GRCURSOR_START_POS 0x00680300 /* RW-4R */ |
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#define NV_PRAMDAC_GRCURSOR_START_POS_X 11:0 /* RWXSF */ |
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#define NV_PRAMDAC_GRCURSOR_START_POS_Y 27:16 /* RWXSF */ |
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#define NV_PRAMDAC_NVPLL_COEFF 0x00680500 /* RW-4R */ |
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#define NV_PRAMDAC_NVPLL_COEFF_MDIV 7:0 /* RWIUF */ |
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#define NV_PRAMDAC_NVPLL_COEFF_NDIV 15:8 /* RWIUF */ |
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#define NV_PRAMDAC_NVPLL_COEFF_PDIV 18:16 /* RWIVF */ |
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#define NV_PRAMDAC_MPLL_COEFF 0x00680504 /* RW-4R */ |
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#define NV_PRAMDAC_MPLL_COEFF_MDIV 7:0 /* RWIUF */ |
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#define NV_PRAMDAC_MPLL_COEFF_NDIV 15:8 /* RWIUF */ |
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#define NV_PRAMDAC_MPLL_COEFF_PDIV 18:16 /* RWIVF */ |
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#define NV_PRAMDAC_VPLL_COEFF 0x00680508 /* RW-4R */ |
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#define NV_PRAMDAC_VPLL_COEFF_MDIV 7:0 /* RWIUF */ |
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#define NV_PRAMDAC_VPLL_COEFF_NDIV 15:8 /* RWIUF */ |
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#define NV_PRAMDAC_VPLL_COEFF_PDIV 18:16 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT 0x0068050C /* RW-4R */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS 4:4 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_FALSE 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_DLL_BYPASS_TRUE 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE 8:8 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_SOURCE_PROG 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS 12:12 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_MPLL_BYPASS_TRUE 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE 16:16 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_DEFAULT 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_SOURCE_PROG 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS 20:20 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_FALSE 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VPLL_BYPASS_TRUE 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE 25:24 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VPLL 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_VIP 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_PCLK_SOURCE_XTALOSC 0x00000002 /* RW--V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO 28:28 /* RWIVF */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB1 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2 0x00000001 /* RW--V */ |
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#define NV_PRAMDAC_GENERAL_CONTROL 0x00680600 /* RW-4R */ |
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#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF 1:0 /* RWIVF */ |
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#define NV_PRAMDAC_GENERAL_CONTROL_FF_COEFF_DEF 0x00000000 /* RWI-V */ |
248 |
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE 4:4 /* RWIVF */ |
249 |
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_GAMMA 0x00000000 /* RWI-V */ |
250 |
#define NV_PRAMDAC_GENERAL_CONTROL_IDC_MODE_INDEX 0x00000001 /* RW--V */ |
251 |
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE 8:8 /* RWIVF */ |
252 |
#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_NOTSE 0x00000000 /* RWI-V */ |
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#define NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL 0x00000001 /* RW--V */ |
254 |
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE 12:12 /* RWIVF */ |
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#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_NOTSEL 0x00000000 /* RWI-V */ |
256 |
#define NV_PRAMDAC_GENERAL_CONTROL_565_MODE_SEL 0x00000001 /* RW--V */ |
257 |
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL 16:16 /* RWIVF */ |
258 |
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_OFF 0x00000000 /* RWI-V */ |
259 |
#define NV_PRAMDAC_GENERAL_CONTROL_BLK_PEDSTL_ON 0x00000001 /* RW--V */ |
260 |
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION 17:17 /* RWIVF */ |
261 |
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_37OHM 0x00000000 /* RWI-V */ |
262 |
#define NV_PRAMDAC_GENERAL_CONTROL_TERMINATION_75OHM 0x00000001 /* RW--V */ |
263 |
#define NV_PRAMDAC_GENERAL_CONTROL_BPC 20:20 /* RWIVF */ |
264 |
#define NV_PRAMDAC_GENERAL_CONTROL_BPC_6BITS 0x00000000 /* RWI-V */ |
265 |
#define NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS 0x00000001 /* RW--V */ |
266 |
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP 24:24 /* RWIVF */ |
267 |
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_DIS 0x00000000 /* RWI-V */ |
268 |
#define NV_PRAMDAC_GENERAL_CONTROL_DAC_SLEEP_EN 0x00000001 /* RW--V */ |
269 |
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK 28:28 /* RWIVF */ |
270 |
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_EN 0x00000000 /* RWI-V */ |
271 |
#define NV_PRAMDAC_GENERAL_CONTROL_PALETTE_CLK_DIS 0x00000001 /* RW--V */ |
272 |
|
273 |
/* Master Control */ |
274 |
#define NV_PMC 0x00000FFF:0x00000000 /* RW--D */ |
275 |
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ |
276 |
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* C--VF */ |
277 |
#define NV_PMC_BOOT_0_MINOR_REVISION_0 0x00000000 /* C---V */ |
278 |
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* C--VF */ |
279 |
#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x00000000 /* C---V */ |
280 |
#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x00000001 /* ----V */ |
281 |
#define NV_PMC_BOOT_0_IMPLEMENTATION 11:8 /* C--VF */ |
282 |
#define NV_PMC_BOOT_0_IMPLEMENTATION_NV4_0 0x00000000 /* C---V */ |
283 |
#define NV_PMC_BOOT_0_ARCHITECTURE 15:12 /* C--VF */ |
284 |
#define NV_PMC_BOOT_0_ARCHITECTURE_NV0 0x00000000 /* ----V */ |
285 |
#define NV_PMC_BOOT_0_ARCHITECTURE_NV1 0x00000001 /* ----V */ |
286 |
#define NV_PMC_BOOT_0_ARCHITECTURE_NV2 0x00000002 /* ----V */ |
287 |
#define NV_PMC_BOOT_0_ARCHITECTURE_NV3 0x00000003 /* ----V */ |
288 |
#define NV_PMC_BOOT_0_ARCHITECTURE_NV4 0x00000004 /* C---V */ |
289 |
#define NV_PMC_BOOT_0_FIB_REVISION 19:16 /* C--VF */ |
290 |
#define NV_PMC_BOOT_0_FIB_REVISION_0 0x00000000 /* C---V */ |
291 |
#define NV_PMC_BOOT_0_MASK_REVISION 23:20 /* C--VF */ |
292 |
#define NV_PMC_BOOT_0_MASK_REVISION_A 0x00000000 /* C---V */ |
293 |
#define NV_PMC_BOOT_0_MASK_REVISION_B 0x00000001 /* ----V */ |
294 |
#define NV_PMC_BOOT_0_MANUFACTURER 27:24 /* C--UF */ |
295 |
#define NV_PMC_BOOT_0_MANUFACTURER_NVIDIA 0x00000000 /* C---V */ |
296 |
#define NV_PMC_BOOT_0_FOUNDRY 31:28 /* C--VF */ |
297 |
#define NV_PMC_BOOT_0_FOUNDRY_SGS 0x00000000 /* ----V */ |
298 |
#define NV_PMC_BOOT_0_FOUNDRY_HELIOS 0x00000001 /* ----V */ |
299 |
#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000002 /* C---V */ |
300 |
#define NV_PMC_INTR_0 0x00000100 /* RW-4R */ |
301 |
#define NV_PMC_INTR_0_PMEDIA 4:4 /* R--VF */ |
302 |
#define NV_PMC_INTR_0_PMEDIA_NOT_PENDING 0x00000000 /* R---V */ |
303 |
#define NV_PMC_INTR_0_PMEDIA_PENDING 0x00000001 /* R---V */ |
304 |
#define NV_PMC_INTR_0_PFIFO 8:8 /* R--VF */ |
305 |
#define NV_PMC_INTR_0_PFIFO_NOT_PENDING 0x00000000 /* R---V */ |
306 |
#define NV_PMC_INTR_0_PFIFO_PENDING 0x00000001 /* R---V */ |
307 |
#define NV_PMC_INTR_0_PGRAPH 12:12 /* R--VF */ |
308 |
#define NV_PMC_INTR_0_PGRAPH_NOT_PENDING 0x00000000 /* R---V */ |
309 |
#define NV_PMC_INTR_0_PGRAPH_PENDING 0x00000001 /* R---V */ |
310 |
#define NV_PMC_INTR_0_PVIDEO 16:16 /* R--VF */ |
311 |
#define NV_PMC_INTR_0_PVIDEO_NOT_PENDING 0x00000000 /* R---V */ |
312 |
#define NV_PMC_INTR_0_PVIDEO_PENDING 0x00000001 /* R---V */ |
313 |
#define NV_PMC_INTR_0_PTIMER 20:20 /* R--VF */ |
314 |
#define NV_PMC_INTR_0_PTIMER_NOT_PENDING 0x00000000 /* R---V */ |
315 |
#define NV_PMC_INTR_0_PTIMER_PENDING 0x00000001 /* R---V */ |
316 |
#define NV_PMC_INTR_0_PCRTC 24:24 /* R--VF */ |
317 |
#define NV_PMC_INTR_0_PCRTC_NOT_PENDING 0x00000000 /* R---V */ |
318 |
#define NV_PMC_INTR_0_PCRTC_PENDING 0x00000001 /* R---V */ |
319 |
#define NV_PMC_INTR_0_PBUS 28:28 /* R--VF */ |
320 |
#define NV_PMC_INTR_0_PBUS_NOT_PENDING 0x00000000 /* R---V */ |
321 |
#define NV_PMC_INTR_0_PBUS_PENDING 0x00000001 /* R---V */ |
322 |
#define NV_PMC_INTR_0_SOFTWARE 31:31 /* RWIVF */ |
323 |
#define NV_PMC_INTR_0_SOFTWARE_NOT_PENDING 0x00000000 /* RWI-V */ |
324 |
#define NV_PMC_INTR_0_SOFTWARE_PENDING 0x00000001 /* RW--V */ |
325 |
#define NV_PMC_INTR_EN_0 0x00000140 /* RW-4R */ |
326 |
#define NV_PMC_INTR_EN_0_INTA 1:0 /* RWIVF */ |
327 |
#define NV_PMC_INTR_EN_0_INTA_DISABLED 0x00000000 /* RWI-V */ |
328 |
#define NV_PMC_INTR_EN_0_INTA_HARDWARE 0x00000001 /* RW--V */ |
329 |
#define NV_PMC_INTR_EN_0_INTA_SOFTWARE 0x00000002 /* RW--V */ |
330 |
#define NV_PMC_INTR_READ_0 0x00000160 /* R--4R */ |
331 |
#define NV_PMC_INTR_READ_0_INTA 0:0 /* R--VF */ |
332 |
#define NV_PMC_INTR_READ_0_INTA_LOW 0x00000000 /* R---V */ |
333 |
#define NV_PMC_INTR_READ_0_INTA_HIGH 0x00000001 /* R---V */ |
334 |
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ |
335 |
#define NV_PMC_ENABLE_PMEDIA 4:4 /* RWIVF */ |
336 |
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* RWI-V */ |
337 |
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* RW--V */ |
338 |
#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ |
339 |
#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ |
340 |
#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ |
341 |
#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ |
342 |
#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ |
343 |
#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ |
344 |
#define NV_PMC_ENABLE_PPMI 16:16 /* RWIVF */ |
345 |
#define NV_PMC_ENABLE_PPMI_DISABLED 0x00000000 /* RWI-V */ |
346 |
#define NV_PMC_ENABLE_PPMI_ENABLED 0x00000001 /* RW--V */ |
347 |
#define NV_PMC_ENABLE_PFB 20:20 /* RWIVF */ |
348 |
#define NV_PMC_ENABLE_PFB_DISABLED 0x00000000 /* RW--V */ |
349 |
#define NV_PMC_ENABLE_PFB_ENABLED 0x00000001 /* RWI-V */ |
350 |
#define NV_PMC_ENABLE_PCRTC 24:24 /* RWIVF */ |
351 |
#define NV_PMC_ENABLE_PCRTC_DISABLED 0x00000000 /* RW--V */ |
352 |
#define NV_PMC_ENABLE_PCRTC_ENABLED 0x00000001 /* RWI-V */ |
353 |
#define NV_PMC_ENABLE_PVIDEO 28:28 /* RWIVF */ |
354 |
#define NV_PMC_ENABLE_PVIDEO_DISABLED 0x00000000 /* RWI-V */ |
355 |
#define NV_PMC_ENABLE_PVIDEO_ENABLED 0x00000001 /* RW--V */ |
356 |
|
357 |
/* dev_timer.ref */ |
358 |
#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */ |
359 |
#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ |
360 |
#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ |
361 |
#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ |
362 |
#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ |
363 |
#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--V */ |
364 |
#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ |
365 |
#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ |
366 |
#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ |
367 |
#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ |
368 |
#define NV_PTIMER_NUMERATOR 0x00009200 /* RW-4R */ |
369 |
#define NV_PTIMER_NUMERATOR_VALUE 15:0 /* RWIUF */ |
370 |
#define NV_PTIMER_NUMERATOR_VALUE_0 0x00000000 /* RWI-V */ |
371 |
#define NV_PTIMER_DENOMINATOR 0x00009210 /* RW-4R */ |
372 |
#define NV_PTIMER_DENOMINATOR_VALUE 15:0 /* RWIUF */ |
373 |
#define NV_PTIMER_DENOMINATOR_VALUE_0 0x00000000 /* RWI-V */ |
374 |
#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */ |
375 |
#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */ |
376 |
#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */ |
377 |
#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */ |
378 |
#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ |
379 |
#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWXUF */ |
380 |
|
381 |
/* dev_fifo.ref */ |
382 |
#define NV_PFIFO 0x00003FFF:0x00002000 /* RW--D */ |
383 |
#define NV_PFIFO_DELAY_0 0x00002040 /* RW-4R */ |
384 |
#define NV_PFIFO_DELAY_0_WAIT_RETRY 9:0 /* RWIUF */ |
385 |
#define NV_PFIFO_DELAY_0_WAIT_RETRY_0 0x00000000 /* RWI-V */ |
386 |
#define NV_PFIFO_DMA_TIMESLICE 0x00002044 /* RW-4R */ |
387 |
#define NV_PFIFO_DMA_TIMESLICE_SELECT 16:0 /* RWIUF */ |
388 |
#define NV_PFIFO_DMA_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ |
389 |
#define NV_PFIFO_DMA_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ |
390 |
#define NV_PFIFO_DMA_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ |
391 |
#define NV_PFIFO_DMA_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ |
392 |
#define NV_PFIFO_DMA_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ |
393 |
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ |
394 |
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ |
395 |
#define NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ |
396 |
#define NV_PFIFO_PIO_TIMESLICE 0x00002048 /* RW-4R */ |
397 |
#define NV_PFIFO_PIO_TIMESLICE_SELECT 16:0 /* RWIUF */ |
398 |
#define NV_PFIFO_PIO_TIMESLICE_SELECT_1 0x00000000 /* RWI-V */ |
399 |
#define NV_PFIFO_PIO_TIMESLICE_SELECT_16K 0x00003fff /* RW--V */ |
400 |
#define NV_PFIFO_PIO_TIMESLICE_SELECT_32K 0x00007fff /* RW--V */ |
401 |
#define NV_PFIFO_PIO_TIMESLICE_SELECT_64K 0x0000ffff /* RW--V */ |
402 |
#define NV_PFIFO_PIO_TIMESLICE_SELECT_128K 0x0001ffff /* RW--V */ |
403 |
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT 24:24 /* RWIUF */ |
404 |
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_DISABLED 0x00000000 /* RW--V */ |
405 |
#define NV_PFIFO_PIO_TIMESLICE_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ |
406 |
#define NV_PFIFO_TIMESLICE 0x0000204C /* RW-4R */ |
407 |
#define NV_PFIFO_TIMESLICE_TIMER 17:0 /* RWIUF */ |
408 |
#define NV_PFIFO_TIMESLICE_TIMER_EXPIRED 0x0003FFFF /* RWI-V */ |
409 |
#define NV_PFIFO_NEXT_CHANNEL 0x00002050 /* RW-4R */ |
410 |
#define NV_PFIFO_NEXT_CHANNEL_CHID 3:0 /* RWXUF */ |
411 |
#define NV_PFIFO_NEXT_CHANNEL_MODE 8:8 /* RWXVF */ |
412 |
#define NV_PFIFO_NEXT_CHANNEL_MODE_PIO 0x00000000 /* RW--V */ |
413 |
#define NV_PFIFO_NEXT_CHANNEL_MODE_DMA 0x00000001 /* RW--V */ |
414 |
#define NV_PFIFO_NEXT_CHANNEL_SWITCH 12:12 /* RWIVF */ |
415 |
#define NV_PFIFO_NEXT_CHANNEL_SWITCH_NOT_PENDING 0x00000000 /* RWI-V */ |
416 |
#define NV_PFIFO_NEXT_CHANNEL_SWITCH_PENDING 0x00000001 /* RW--V */ |
417 |
#define NV_PFIFO_DEBUG_0 0x00002080 /* R--4R */ |
418 |
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0 0:0 /* R-XVF */ |
419 |
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_NOT_PENDING 0x00000000 /* R---V */ |
420 |
#define NV_PFIFO_DEBUG_0_CACHE_ERROR0_PENDING 0x00000001 /* R---V */ |
421 |
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1 4:4 /* R-XVF */ |
422 |
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_NOT_PENDING 0x00000000 /* R---V */ |
423 |
#define NV_PFIFO_DEBUG_0_CACHE_ERROR1_PENDING 0x00000001 /* R---V */ |
424 |
#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ |
425 |
#define NV_PFIFO_INTR_0_CACHE_ERROR 0:0 /* RWXVF */ |
426 |
#define NV_PFIFO_INTR_0_CACHE_ERROR_NOT_PENDING 0x00000000 /* R---V */ |
427 |
#define NV_PFIFO_INTR_0_CACHE_ERROR_PENDING 0x00000001 /* R---V */ |
428 |
#define NV_PFIFO_INTR_0_CACHE_ERROR_RESET 0x00000001 /* -W--V */ |
429 |
#define NV_PFIFO_INTR_0_RUNOUT 4:4 /* RWXVF */ |
430 |
#define NV_PFIFO_INTR_0_RUNOUT_NOT_PENDING 0x00000000 /* R---V */ |
431 |
#define NV_PFIFO_INTR_0_RUNOUT_PENDING 0x00000001 /* R---V */ |
432 |
#define NV_PFIFO_INTR_0_RUNOUT_RESET 0x00000001 /* -W--V */ |
433 |
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW 8:8 /* RWXVF */ |
434 |
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ |
435 |
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_PENDING 0x00000001 /* R---V */ |
436 |
#define NV_PFIFO_INTR_0_RUNOUT_OVERFLOW_RESET 0x00000001 /* -W--V */ |
437 |
#define NV_PFIFO_INTR_0_DMA_PUSHER 12:12 /* RWXVF */ |
438 |
#define NV_PFIFO_INTR_0_DMA_PUSHER_NOT_PENDING 0x00000000 /* R---V */ |
439 |
#define NV_PFIFO_INTR_0_DMA_PUSHER_PENDING 0x00000001 /* R---V */ |
440 |
#define NV_PFIFO_INTR_0_DMA_PUSHER_RESET 0x00000001 /* -W--V */ |
441 |
#define NV_PFIFO_INTR_0_DMA_PT 16:16 /* RWXVF */ |
442 |
#define NV_PFIFO_INTR_0_DMA_PT_NOT_PENDING 0x00000000 /* R---V */ |
443 |
#define NV_PFIFO_INTR_0_DMA_PT_PENDING 0x00000001 /* R---V */ |
444 |
#define NV_PFIFO_INTR_0_DMA_PT_RESET 0x00000001 /* -W--V */ |
445 |
#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ |
446 |
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR 0:0 /* RWIVF */ |
447 |
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_DISABLED 0x00000000 /* RWI-V */ |
448 |
#define NV_PFIFO_INTR_EN_0_CACHE_ERROR_ENABLED 0x00000001 /* RW--V */ |
449 |
#define NV_PFIFO_INTR_EN_0_RUNOUT 4:4 /* RWIVF */ |
450 |
#define NV_PFIFO_INTR_EN_0_RUNOUT_DISABLED 0x00000000 /* RWI-V */ |
451 |
#define NV_PFIFO_INTR_EN_0_RUNOUT_ENABLED 0x00000001 /* RW--V */ |
452 |
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW 8:8 /* RWIVF */ |
453 |
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_DISABLED 0x00000000 /* RWI-V */ |
454 |
#define NV_PFIFO_INTR_EN_0_RUNOUT_OVERFLOW_ENABLED 0x00000001 /* RW--V */ |
455 |
#define NV_PFIFO_INTR_EN_0_DMA_PUSHER 12:12 /* RWIVF */ |
456 |
#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_DISABLED 0x00000000 /* RWI-V */ |
457 |
#define NV_PFIFO_INTR_EN_0_DMA_PUSHER_ENABLED 0x00000001 /* RW--V */ |
458 |
#define NV_PFIFO_INTR_EN_0_DMA_PT 16:16 /* RWIVF */ |
459 |
#define NV_PFIFO_INTR_EN_0_DMA_PT_DISABLED 0x00000000 /* RWI-V */ |
460 |
#define NV_PFIFO_INTR_EN_0_DMA_PT_ENABLED 0x00000001 /* RW--V */ |
461 |
#define NV_PFIFO_RAMHT 0x00002210 /* RW-4R */ |
462 |
#define NV_PFIFO_RAMHT_BASE_ADDRESS 8:4 /* RWIUF */ |
463 |
#define NV_PFIFO_RAMHT_BASE_ADDRESS_10000 0x00000010 /* RWI-V */ |
464 |
#define NV_PFIFO_RAMHT_SIZE 17:16 /* RWIUF */ |
465 |
#define NV_PFIFO_RAMHT_SIZE_4K 0x00000000 /* RWI-V */ |
466 |
#define NV_PFIFO_RAMHT_SIZE_8K 0x00000001 /* RW--V */ |
467 |
#define NV_PFIFO_RAMHT_SIZE_16K 0x00000002 /* RW--V */ |
468 |
#define NV_PFIFO_RAMHT_SIZE_32K 0x00000003 /* RW--V */ |
469 |
#define NV_PFIFO_RAMHT_SEARCH 25:24 /* RWIUF */ |
470 |
#define NV_PFIFO_RAMHT_SEARCH_16 0x00000000 /* RWI-V */ |
471 |
#define NV_PFIFO_RAMHT_SEARCH_32 0x00000001 /* RW--V */ |
472 |
#define NV_PFIFO_RAMHT_SEARCH_64 0x00000002 /* RW--V */ |
473 |
#define NV_PFIFO_RAMHT_SEARCH_128 0x00000003 /* RW--V */ |
474 |
#define NV_PFIFO_RAMFC 0x00002214 /* RW-4R */ |
475 |
#define NV_PFIFO_RAMFC_BASE_ADDRESS 8:1 /* RWIUF */ |
476 |
#define NV_PFIFO_RAMFC_BASE_ADDRESS_11000 0x00000088 /* RWI-V */ |
477 |
#define NV_PFIFO_RAMRO 0x00002218 /* RW-4R */ |
478 |
#define NV_PFIFO_RAMRO_BASE_ADDRESS 8:1 /* RWIUF */ |
479 |
#define NV_PFIFO_RAMRO_BASE_ADDRESS_11200 0x00000089 /* RWI-V */ |
480 |
#define NV_PFIFO_RAMRO_BASE_ADDRESS_12000 0x00000090 /* RW--V */ |
481 |
#define NV_PFIFO_RAMRO_SIZE 16:16 /* RWIVF */ |
482 |
#define NV_PFIFO_RAMRO_SIZE_512 0x00000000 /* RWI-V */ |
483 |
#define NV_PFIFO_RAMRO_SIZE_8K 0x00000001 /* RW--V */ |
484 |
#define NV_PFIFO_CACHES 0x00002500 /* RW-4R */ |
485 |
#define NV_PFIFO_CACHES_REASSIGN 0:0 /* RWIVF */ |
486 |
#define NV_PFIFO_CACHES_REASSIGN_DISABLED 0x00000000 /* RWI-V */ |
487 |
#define NV_PFIFO_CACHES_REASSIGN_ENABLED 0x00000001 /* RW--V */ |
488 |
#define NV_PFIFO_CACHES_DMA_SUSPEND 4:4 /* R--VF */ |
489 |
#define NV_PFIFO_CACHES_DMA_SUSPEND_IDLE 0x00000000 /* R---V */ |
490 |
#define NV_PFIFO_CACHES_DMA_SUSPEND_BUSY 0x00000001 /* R---V */ |
491 |
#define NV_PFIFO_MODE 0x00002504 /* RW-4R */ |
492 |
#define NV_PFIFO_MODE_CHANNEL_0 0:0 /* RWIVF */ |
493 |
#define NV_PFIFO_MODE_CHANNEL_0_PIO 0x00000000 /* RWI-V */ |
494 |
#define NV_PFIFO_MODE_CHANNEL_0_DMA 0x00000001 /* RW--V */ |
495 |
#define NV_PFIFO_MODE_CHANNEL_1 1:1 /* RWIVF */ |
496 |
#define NV_PFIFO_MODE_CHANNEL_1_PIO 0x00000000 /* RWI-V */ |
497 |
#define NV_PFIFO_MODE_CHANNEL_1_DMA 0x00000001 /* RW--V */ |
498 |
#define NV_PFIFO_MODE_CHANNEL_2 2:2 /* RWIVF */ |
499 |
#define NV_PFIFO_MODE_CHANNEL_2_PIO 0x00000000 /* RWI-V */ |
500 |
#define NV_PFIFO_MODE_CHANNEL_2_DMA 0x00000001 /* RW--V */ |
501 |
#define NV_PFIFO_MODE_CHANNEL_3 3:3 /* RWIVF */ |
502 |
#define NV_PFIFO_MODE_CHANNEL_3_PIO 0x00000000 /* RWI-V */ |
503 |
#define NV_PFIFO_MODE_CHANNEL_3_DMA 0x00000001 /* RW--V */ |
504 |
#define NV_PFIFO_MODE_CHANNEL_4 4:4 /* RWIVF */ |
505 |
#define NV_PFIFO_MODE_CHANNEL_4_PIO 0x00000000 /* RWI-V */ |
506 |
#define NV_PFIFO_MODE_CHANNEL_4_DMA 0x00000001 /* RW--V */ |
507 |
#define NV_PFIFO_MODE_CHANNEL_5 5:5 /* RWIVF */ |
508 |
#define NV_PFIFO_MODE_CHANNEL_5_PIO 0x00000000 /* RWI-V */ |
509 |
#define NV_PFIFO_MODE_CHANNEL_5_DMA 0x00000001 /* RW--V */ |
510 |
#define NV_PFIFO_MODE_CHANNEL_6 6:6 /* RWIVF */ |
511 |
#define NV_PFIFO_MODE_CHANNEL_6_PIO 0x00000000 /* RWI-V */ |
512 |
#define NV_PFIFO_MODE_CHANNEL_6_DMA 0x00000001 /* RW--V */ |
513 |
#define NV_PFIFO_MODE_CHANNEL_7 7:7 /* RWIVF */ |
514 |
#define NV_PFIFO_MODE_CHANNEL_7_PIO 0x00000000 /* RWI-V */ |
515 |
#define NV_PFIFO_MODE_CHANNEL_7_DMA 0x00000001 /* RW--V */ |
516 |
#define NV_PFIFO_MODE_CHANNEL_8 8:8 /* RWIVF */ |
517 |
#define NV_PFIFO_MODE_CHANNEL_8_PIO 0x00000000 /* RWI-V */ |
518 |
#define NV_PFIFO_MODE_CHANNEL_8_DMA 0x00000001 /* RW--V */ |
519 |
#define NV_PFIFO_MODE_CHANNEL_9 9:9 /* RWIVF */ |
520 |
#define NV_PFIFO_MODE_CHANNEL_9_PIO 0x00000000 /* RWI-V */ |
521 |
#define NV_PFIFO_MODE_CHANNEL_9_DMA 0x00000001 /* RW--V */ |
522 |
#define NV_PFIFO_MODE_CHANNEL_10 10:10 /* RWIVF */ |
523 |
#define NV_PFIFO_MODE_CHANNEL_10_PIO 0x00000000 /* RWI-V */ |
524 |
#define NV_PFIFO_MODE_CHANNEL_10_DMA 0x00000001 /* RW--V */ |
525 |
#define NV_PFIFO_MODE_CHANNEL_11 11:11 /* RWIVF */ |
526 |
#define NV_PFIFO_MODE_CHANNEL_11_PIO 0x00000000 /* RWI-V */ |
527 |
#define NV_PFIFO_MODE_CHANNEL_11_DMA 0x00000001 /* RW--V */ |
528 |
#define NV_PFIFO_MODE_CHANNEL_12 12:12 /* RWIVF */ |
529 |
#define NV_PFIFO_MODE_CHANNEL_12_PIO 0x00000000 /* RWI-V */ |
530 |
#define NV_PFIFO_MODE_CHANNEL_12_DMA 0x00000001 /* RW--V */ |
531 |
#define NV_PFIFO_MODE_CHANNEL_13 13:13 /* RWIVF */ |
532 |
#define NV_PFIFO_MODE_CHANNEL_13_PIO 0x00000000 /* RWI-V */ |
533 |
#define NV_PFIFO_MODE_CHANNEL_13_DMA 0x00000001 /* RW--V */ |
534 |
#define NV_PFIFO_MODE_CHANNEL_14 14:14 /* RWIVF */ |
535 |
#define NV_PFIFO_MODE_CHANNEL_14_PIO 0x00000000 /* RWI-V */ |
536 |
#define NV_PFIFO_MODE_CHANNEL_14_DMA 0x00000001 /* RW--V */ |
537 |
#define NV_PFIFO_MODE_CHANNEL_15 15:15 /* RWIVF */ |
538 |
#define NV_PFIFO_MODE_CHANNEL_15_PIO 0x00000000 /* RWI-V */ |
539 |
#define NV_PFIFO_MODE_CHANNEL_15_DMA 0x00000001 /* RW--V */ |
540 |
#define NV_PFIFO_DMA 0x00002508 /* RW-4R */ |
541 |
#define NV_PFIFO_DMA_CHANNEL_0 0:0 /* RWIVF */ |
542 |
#define NV_PFIFO_DMA_CHANNEL_0_NOT_PENDING 0x00000000 /* RWI-V */ |
543 |
#define NV_PFIFO_DMA_CHANNEL_0_PENDING 0x00000001 /* RW--V */ |
544 |
#define NV_PFIFO_DMA_CHANNEL_1 1:1 /* RWIVF */ |
545 |
#define NV_PFIFO_DMA_CHANNEL_1_NOT_PENDING 0x00000000 /* RWI-V */ |
546 |
#define NV_PFIFO_DMA_CHANNEL_1_PENDING 0x00000001 /* RW--V */ |
547 |
#define NV_PFIFO_DMA_CHANNEL_2 2:2 /* RWIVF */ |
548 |
#define NV_PFIFO_DMA_CHANNEL_2_NOT_PENDING 0x00000000 /* RWI-V */ |
549 |
#define NV_PFIFO_DMA_CHANNEL_2_PENDING 0x00000001 /* RW--V */ |
550 |
#define NV_PFIFO_DMA_CHANNEL_3 3:3 /* RWIVF */ |
551 |
#define NV_PFIFO_DMA_CHANNEL_3_NOT_PENDING 0x00000000 /* RWI-V */ |
552 |
#define NV_PFIFO_DMA_CHANNEL_3_PENDING 0x00000001 /* RW--V */ |
553 |
#define NV_PFIFO_DMA_CHANNEL_4 4:4 /* RWIVF */ |
554 |
#define NV_PFIFO_DMA_CHANNEL_4_NOT_PENDING 0x00000000 /* RWI-V */ |
555 |
#define NV_PFIFO_DMA_CHANNEL_4_PENDING 0x00000001 /* RW--V */ |
556 |
#define NV_PFIFO_DMA_CHANNEL_5 5:5 /* RWIVF */ |
557 |
#define NV_PFIFO_DMA_CHANNEL_5_NOT_PENDING 0x00000000 /* RWI-V */ |
558 |
#define NV_PFIFO_DMA_CHANNEL_5_PENDING 0x00000001 /* RW--V */ |
559 |
#define NV_PFIFO_DMA_CHANNEL_6 6:6 /* RWIVF */ |
560 |
#define NV_PFIFO_DMA_CHANNEL_6_NOT_PENDING 0x00000000 /* RWI-V */ |
561 |
#define NV_PFIFO_DMA_CHANNEL_6_PENDING 0x00000001 /* RW--V */ |
562 |
#define NV_PFIFO_DMA_CHANNEL_7 7:7 /* RWIVF */ |
563 |
#define NV_PFIFO_DMA_CHANNEL_7_NOT_PENDING 0x00000000 /* RWI-V */ |
564 |
#define NV_PFIFO_DMA_CHANNEL_7_PENDING 0x00000001 /* RW--V */ |
565 |
#define NV_PFIFO_DMA_CHANNEL_8 8:8 /* RWIVF */ |
566 |
#define NV_PFIFO_DMA_CHANNEL_8_NOT_PENDING 0x00000000 /* RWI-V */ |
567 |
#define NV_PFIFO_DMA_CHANNEL_8_PENDING 0x00000001 /* RW--V */ |
568 |
#define NV_PFIFO_DMA_CHANNEL_9 9:9 /* RWIVF */ |
569 |
#define NV_PFIFO_DMA_CHANNEL_9_NOT_PENDING 0x00000000 /* RWI-V */ |
570 |
#define NV_PFIFO_DMA_CHANNEL_9_PENDING 0x00000001 /* RW--V */ |
571 |
#define NV_PFIFO_DMA_CHANNEL_10 10:10 /* RWIVF */ |
572 |
#define NV_PFIFO_DMA_CHANNEL_10_NOT_PENDING 0x00000000 /* RWI-V */ |
573 |
#define NV_PFIFO_DMA_CHANNEL_10_PENDING 0x00000001 /* RW--V */ |
574 |
#define NV_PFIFO_DMA_CHANNEL_11 11:11 /* RWIVF */ |
575 |
#define NV_PFIFO_DMA_CHANNEL_11_NOT_PENDING 0x00000000 /* RWI-V */ |
576 |
#define NV_PFIFO_DMA_CHANNEL_11_PENDING 0x00000001 /* RW--V */ |
577 |
#define NV_PFIFO_DMA_CHANNEL_12 12:12 /* RWIVF */ |
578 |
#define NV_PFIFO_DMA_CHANNEL_12_NOT_PENDING 0x00000000 /* RWI-V */ |
579 |
#define NV_PFIFO_DMA_CHANNEL_12_PENDING 0x00000001 /* RW--V */ |
580 |
#define NV_PFIFO_DMA_CHANNEL_13 13:13 /* RWIVF */ |
581 |
#define NV_PFIFO_DMA_CHANNEL_13_NOT_PENDING 0x00000000 /* RWI-V */ |
582 |
#define NV_PFIFO_DMA_CHANNEL_13_PENDING 0x00000001 /* RW--V */ |
583 |
#define NV_PFIFO_DMA_CHANNEL_14 14:14 /* RWIVF */ |
584 |
#define NV_PFIFO_DMA_CHANNEL_14_NOT_PENDING 0x00000000 /* RWI-V */ |
585 |
#define NV_PFIFO_DMA_CHANNEL_14_PENDING 0x00000001 /* RW--V */ |
586 |
#define NV_PFIFO_DMA_CHANNEL_15 15:15 /* RWIVF */ |
587 |
#define NV_PFIFO_DMA_CHANNEL_15_NOT_PENDING 0x00000000 /* RWI-V */ |
588 |
#define NV_PFIFO_DMA_CHANNEL_15_PENDING 0x00000001 /* RW--V */ |
589 |
#define NV_PFIFO_SIZE 0x0000250C /* RW-4R */ |
590 |
#define NV_PFIFO_SIZE_CHANNEL_0 0:0 /* RWIVF */ |
591 |
#define NV_PFIFO_SIZE_CHANNEL_0_124_BYTES 0x00000000 /* RWI-V */ |
592 |
#define NV_PFIFO_SIZE_CHANNEL_0_512_BYTES 0x00000001 /* RW--V */ |
593 |
#define NV_PFIFO_SIZE_CHANNEL_1 1:1 /* RWIVF */ |
594 |
#define NV_PFIFO_SIZE_CHANNEL_1_124_BYTES 0x00000000 /* RWI-V */ |
595 |
#define NV_PFIFO_SIZE_CHANNEL_1_512_BYTES 0x00000001 /* RW--V */ |
596 |
#define NV_PFIFO_SIZE_CHANNEL_2 2:2 /* RWIVF */ |
597 |
#define NV_PFIFO_SIZE_CHANNEL_2_124_BYTES 0x00000000 /* RWI-V */ |
598 |
#define NV_PFIFO_SIZE_CHANNEL_2_512_BYTES 0x00000001 /* RW--V */ |
599 |
#define NV_PFIFO_SIZE_CHANNEL_3 3:3 /* RWIVF */ |
600 |
#define NV_PFIFO_SIZE_CHANNEL_3_124_BYTES 0x00000000 /* RWI-V */ |
601 |
#define NV_PFIFO_SIZE_CHANNEL_3_512_BYTES 0x00000001 /* RW--V */ |
602 |
#define NV_PFIFO_SIZE_CHANNEL_4 4:4 /* RWIVF */ |
603 |
#define NV_PFIFO_SIZE_CHANNEL_4_124_BYTES 0x00000000 /* RWI-V */ |
604 |
#define NV_PFIFO_SIZE_CHANNEL_4_512_BYTES 0x00000001 /* RW--V */ |
605 |
#define NV_PFIFO_SIZE_CHANNEL_5 5:5 /* RWIVF */ |
606 |
#define NV_PFIFO_SIZE_CHANNEL_5_124_BYTES 0x00000000 /* RWI-V */ |
607 |
#define NV_PFIFO_SIZE_CHANNEL_5_512_BYTES 0x00000001 /* RW--V */ |
608 |
#define NV_PFIFO_SIZE_CHANNEL_6 6:6 /* RWIVF */ |
609 |
#define NV_PFIFO_SIZE_CHANNEL_6_124_BYTES 0x00000000 /* RWI-V */ |
610 |
#define NV_PFIFO_SIZE_CHANNEL_6_512_BYTES 0x00000001 /* RW--V */ |
611 |
#define NV_PFIFO_SIZE_CHANNEL_7 7:7 /* RWIVF */ |
612 |
#define NV_PFIFO_SIZE_CHANNEL_7_124_BYTES 0x00000000 /* RWI-V */ |
613 |
#define NV_PFIFO_SIZE_CHANNEL_7_512_BYTES 0x00000001 /* RW--V */ |
614 |
#define NV_PFIFO_SIZE_CHANNEL_8 8:8 /* RWIVF */ |
615 |
#define NV_PFIFO_SIZE_CHANNEL_8_124_BYTES 0x00000000 /* RWI-V */ |
616 |
#define NV_PFIFO_SIZE_CHANNEL_8_512_BYTES 0x00000001 /* RW--V */ |
617 |
#define NV_PFIFO_SIZE_CHANNEL_9 9:9 /* RWIVF */ |
618 |
#define NV_PFIFO_SIZE_CHANNEL_9_124_BYTES 0x00000000 /* RWI-V */ |
619 |
#define NV_PFIFO_SIZE_CHANNEL_9_512_BYTES 0x00000001 /* RW--V */ |
620 |
#define NV_PFIFO_SIZE_CHANNEL_10 10:10 /* RWIVF */ |
621 |
#define NV_PFIFO_SIZE_CHANNEL_10_124_BYTES 0x00000000 /* RWI-V */ |
622 |
#define NV_PFIFO_SIZE_CHANNEL_10_512_BYTES 0x00000001 /* RW--V */ |
623 |
#define NV_PFIFO_SIZE_CHANNEL_11 11:11 /* RWIVF */ |
624 |
#define NV_PFIFO_SIZE_CHANNEL_11_124_BYTES 0x00000000 /* RWI-V */ |
625 |
#define NV_PFIFO_SIZE_CHANNEL_11_512_BYTES 0x00000001 /* RW--V */ |
626 |
#define NV_PFIFO_SIZE_CHANNEL_12 12:12 /* RWIVF */ |
627 |
#define NV_PFIFO_SIZE_CHANNEL_12_124_BYTES 0x00000000 /* RWI-V */ |
628 |
#define NV_PFIFO_SIZE_CHANNEL_12_512_BYTES 0x00000001 /* RW--V */ |
629 |
#define NV_PFIFO_SIZE_CHANNEL_13 13:13 /* RWIVF */ |
630 |
#define NV_PFIFO_SIZE_CHANNEL_13_124_BYTES 0x00000000 /* RWI-V */ |
631 |
#define NV_PFIFO_SIZE_CHANNEL_13_512_BYTES 0x00000001 /* RW--V */ |
632 |
#define NV_PFIFO_SIZE_CHANNEL_14 14:14 /* RWIVF */ |
633 |
#define NV_PFIFO_SIZE_CHANNEL_14_124_BYTES 0x00000000 /* RWI-V */ |
634 |
#define NV_PFIFO_SIZE_CHANNEL_14_512_BYTES 0x00000001 /* RW--V */ |
635 |
#define NV_PFIFO_SIZE_CHANNEL_15 15:15 /* RWIVF */ |
636 |
#define NV_PFIFO_SIZE_CHANNEL_15_124_BYTES 0x00000000 /* RWI-V */ |
637 |
#define NV_PFIFO_SIZE_CHANNEL_15_512_BYTES 0x00000001 /* RW--V */ |
638 |
#define NV_PFIFO_CACHE0_PUSH0 0x00003000 /* RW-4R */ |
639 |
#define NV_PFIFO_CACHE0_PUSH0_ACCESS 0:0 /* RWIVF */ |
640 |
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
641 |
#define NV_PFIFO_CACHE0_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
642 |
#define NV_PFIFO_CACHE1_PUSH0 0x00003200 /* RW-4R */ |
643 |
#define NV_PFIFO_CACHE1_PUSH0_ACCESS 0:0 /* RWIVF */ |
644 |
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
645 |
#define NV_PFIFO_CACHE1_PUSH0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
646 |
#define NV_PFIFO_CACHE0_PUSH1 0x00003004 /* RW-4R */ |
647 |
#define NV_PFIFO_CACHE0_PUSH1_CHID 3:0 /* RWXUF */ |
648 |
#define NV_PFIFO_CACHE1_PUSH1 0x00003204 /* RW-4R */ |
649 |
#define NV_PFIFO_CACHE1_PUSH1_CHID 3:0 /* RWXUF */ |
650 |
#define NV_PFIFO_CACHE1_PUSH1_MODE 8:8 /* RWIVF */ |
651 |
#define NV_PFIFO_CACHE1_PUSH1_MODE_PIO 0x00000000 /* RWI-V */ |
652 |
#define NV_PFIFO_CACHE1_PUSH1_MODE_DMA 0x00000001 /* RW--V */ |
653 |
#define NV_PFIFO_CACHE1_DMA_PUSH 0x00003220 /* RW-4R */ |
654 |
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS 0:0 /* RWIVF */ |
655 |
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
656 |
#define NV_PFIFO_CACHE1_DMA_PUSH_ACCESS_ENABLED 0x00000001 /* RW--V */ |
657 |
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE 4:4 /* R--VF */ |
658 |
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_IDLE 0x00000000 /* R---V */ |
659 |
#define NV_PFIFO_CACHE1_DMA_PUSH_STATE_BUSY 0x00000001 /* R---V */ |
660 |
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER 8:8 /* R--VF */ |
661 |
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_NOT_EMPTY 0x00000000 /* R---V */ |
662 |
#define NV_PFIFO_CACHE1_DMA_PUSH_BUFFER_EMPTY 0x00000001 /* R---V */ |
663 |
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS 12:12 /* RWIVF */ |
664 |
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_RUNNING 0x00000000 /* RWI-V */ |
665 |
#define NV_PFIFO_CACHE1_DMA_PUSH_STATUS_SUSPENDED 0x00000001 /* RW--V */ |
666 |
#define NV_PFIFO_CACHE1_DMA_FETCH 0x00003224 /* RW-4R */ |
667 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG 7:3 /* RWIUF */ |
668 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES 0x00000000 /* RW--V */ |
669 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES 0x00000001 /* RW--V */ |
670 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES 0x00000002 /* RW--V */ |
671 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES 0x00000003 /* RW--V */ |
672 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES 0x00000004 /* RW--V */ |
673 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES 0x00000005 /* RW--V */ |
674 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES 0x00000006 /* RW--V */ |
675 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES 0x00000007 /* RW--V */ |
676 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES 0x00000008 /* RW--V */ |
677 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES 0x00000009 /* RW--V */ |
678 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES 0x0000000A /* RW--V */ |
679 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES 0x0000000B /* RW--V */ |
680 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES 0x0000000C /* RW--V */ |
681 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES 0x0000000D /* RW--V */ |
682 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES 0x0000000E /* RW--V */ |
683 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES 0x0000000F /* RWI-V */ |
684 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES 0x00000010 /* RW--V */ |
685 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES 0x00000011 /* RW--V */ |
686 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES 0x00000012 /* RW--V */ |
687 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES 0x00000013 /* RW--V */ |
688 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES 0x00000014 /* RW--V */ |
689 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES 0x00000015 /* RW--V */ |
690 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES 0x00000016 /* RW--V */ |
691 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES 0x00000017 /* RW--V */ |
692 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES 0x00000018 /* RW--V */ |
693 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES 0x00000019 /* RW--V */ |
694 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES 0x0000001A /* RW--V */ |
695 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES 0x0000001B /* RW--V */ |
696 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES 0x0000001C /* RW--V */ |
697 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES 0x0000001D /* RW--V */ |
698 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES 0x0000001E /* RW--V */ |
699 |
#define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES 0x0000001F /* RW--V */ |
700 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE 15:13 /* RWIUF */ |
701 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES 0x00000000 /* RW--V */ |
702 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES 0x00000001 /* RW--V */ |
703 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES 0x00000002 /* RW--V */ |
704 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES 0x00000003 /* RWI-V */ |
705 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES 0x00000004 /* RW--V */ |
706 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES 0x00000005 /* RW--V */ |
707 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES 0x00000006 /* RW--V */ |
708 |
#define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES 0x00000007 /* RW--V */ |
709 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS 19:16 /* RWIUF */ |
710 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0 0x00000000 /* RWI-V */ |
711 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1 0x00000001 /* RW--V */ |
712 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2 0x00000002 /* RW--V */ |
713 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3 0x00000003 /* RW--V */ |
714 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 0x00000004 /* RW--V */ |
715 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5 0x00000005 /* RW--V */ |
716 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6 0x00000006 /* RW--V */ |
717 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7 0x00000007 /* RW--V */ |
718 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 0x00000008 /* RW--V */ |
719 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9 0x00000009 /* RW--V */ |
720 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10 0x0000000A /* RW--V */ |
721 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11 0x0000000B /* RW--V */ |
722 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12 0x0000000C /* RW--V */ |
723 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13 0x0000000D /* RW--V */ |
724 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14 0x0000000E /* RW--V */ |
725 |
#define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15 0x0000000F /* RW--V */ |
726 |
#define NV_PFIFO_CACHE1_DMA_PUT 0x00003240 /* RW-4R */ |
727 |
#define NV_PFIFO_CACHE1_DMA_PUT_OFFSET 28:2 /* RWXUF */ |
728 |
#define NV_PFIFO_CACHE1_DMA_GET 0x00003244 /* RW-4R */ |
729 |
#define NV_PFIFO_CACHE1_DMA_GET_OFFSET 28:2 /* RWXUF */ |
730 |
#define NV_PFIFO_CACHE1_DMA_STATE 0x00003228 /* RW-4R */ |
731 |
#define NV_PFIFO_CACHE1_DMA_STATE_METHOD 12:2 /* RWXUF */ |
732 |
#define NV_PFIFO_CACHE1_DMA_STATE_SUBCHANNEL 15:13 /* RWXUF */ |
733 |
#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT 28:18 /* RWIUF */ |
734 |
#define NV_PFIFO_CACHE1_DMA_STATE_METHOD_COUNT_0 0x00000000 /* RWI-V */ |
735 |
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR 31:30 /* RWXUF */ |
736 |
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NONE 0x00000000 /* RW--V */ |
737 |
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_NON_CACHE 0x00000001 /* RW--V */ |
738 |
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_RESERVED_CMD 0x00000002 /* RW--V */ |
739 |
#define NV_PFIFO_CACHE1_DMA_STATE_ERROR_PROTECTION 0x00000003 /* RW--V */ |
740 |
#define NV_PFIFO_CACHE1_DMA_INSTANCE 0x0000322C /* RW-4R */ |
741 |
#define NV_PFIFO_CACHE1_DMA_INSTANCE_ADDRESS 15:0 /* RWXUF */ |
742 |
#define NV_PFIFO_CACHE1_DMA_CTL 0x00003230 /* RW-4R */ |
743 |
#define NV_PFIFO_CACHE1_DMA_CTL_ADJUST 11:2 /* RWXUF */ |
744 |
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE 12:12 /* RWXUF */ |
745 |
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RW--V */ |
746 |
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ |
747 |
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY 13:13 /* RWXUF */ |
748 |
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ |
749 |
#define NV_PFIFO_CACHE1_DMA_CTL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ |
750 |
#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE 17:16 /* RWXUF */ |
751 |
#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_PCI 0x00000002 /* RW--V */ |
752 |
#define NV_PFIFO_CACHE1_DMA_CTL_TARGET_NODE_AGP 0x00000003 /* RW--V */ |
753 |
#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO 31:31 /* RWIUF */ |
754 |
#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_INVALID 0x00000000 /* RW--V */ |
755 |
#define NV_PFIFO_CACHE1_DMA_CTL_AT_INFO_VALID 0x00000001 /* RWI-V */ |
756 |
#define NV_PFIFO_CACHE1_DMA_LIMIT 0x00003234 /* RW-4R */ |
757 |
#define NV_PFIFO_CACHE1_DMA_LIMIT_OFFSET 28:2 /* RWXUF */ |
758 |
#define NV_PFIFO_CACHE1_DMA_TLB_TAG 0x00003238 /* RW-4R */ |
759 |
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_ADDRESS 28:12 /* RWXUF */ |
760 |
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE 0:0 /* RWIUF */ |
761 |
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_INVALID 0x00000000 /* RWI-V */ |
762 |
#define NV_PFIFO_CACHE1_DMA_TLB_TAG_STATE_VALID 0x00000001 /* RW--V */ |
763 |
#define NV_PFIFO_CACHE1_DMA_TLB_PTE 0x0000323C /* RW-4R */ |
764 |
#define NV_PFIFO_CACHE1_DMA_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ |
765 |
#define NV_PFIFO_CACHE0_PULL0 0x00003050 /* RW-4R */ |
766 |
#define NV_PFIFO_CACHE0_PULL0_ACCESS 0:0 /* RWIVF */ |
767 |
#define NV_PFIFO_CACHE0_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
768 |
#define NV_PFIFO_CACHE0_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
769 |
#define NV_PFIFO_CACHE0_PULL0_HASH 4:4 /* R-XVF */ |
770 |
#define NV_PFIFO_CACHE0_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ |
771 |
#define NV_PFIFO_CACHE0_PULL0_HASH_FAILED 0x00000001 /* R---V */ |
772 |
#define NV_PFIFO_CACHE0_PULL0_DEVICE 8:8 /* R-XVF */ |
773 |
#define NV_PFIFO_CACHE0_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ |
774 |
#define NV_PFIFO_CACHE0_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ |
775 |
#define NV_PFIFO_CACHE0_PULL0_HASH_STATE 12:12 /* R-XVF */ |
776 |
#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ |
777 |
#define NV_PFIFO_CACHE0_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ |
778 |
#define NV_PFIFO_CACHE1_PULL0 0x00003250 /* RW-4R */ |
779 |
#define NV_PFIFO_CACHE1_PULL0_ACCESS 0:0 /* RWIVF */ |
780 |
#define NV_PFIFO_CACHE1_PULL0_ACCESS_DISABLED 0x00000000 /* RWI-V */ |
781 |
#define NV_PFIFO_CACHE1_PULL0_ACCESS_ENABLED 0x00000001 /* RW--V */ |
782 |
#define NV_PFIFO_CACHE1_PULL0_HASH 4:4 /* R-XVF */ |
783 |
#define NV_PFIFO_CACHE1_PULL0_HASH_SUCCEEDED 0x00000000 /* R---V */ |
784 |
#define NV_PFIFO_CACHE1_PULL0_HASH_FAILED 0x00000001 /* R---V */ |
785 |
#define NV_PFIFO_CACHE1_PULL0_DEVICE 8:8 /* R-XVF */ |
786 |
#define NV_PFIFO_CACHE1_PULL0_DEVICE_HARDWARE 0x00000000 /* R---V */ |
787 |
#define NV_PFIFO_CACHE1_PULL0_DEVICE_SOFTWARE 0x00000001 /* R---V */ |
788 |
#define NV_PFIFO_CACHE1_PULL0_HASH_STATE 12:12 /* R-XVF */ |
789 |
#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_IDLE 0x00000000 /* R---V */ |
790 |
#define NV_PFIFO_CACHE1_PULL0_HASH_STATE_BUSY 0x00000001 /* R---V */ |
791 |
#define NV_PFIFO_CACHE0_PULL1 0x00003054 /* RW-4R */ |
792 |
#define NV_PFIFO_CACHE0_PULL1_ENGINE 1:0 /* RWXUF */ |
793 |
#define NV_PFIFO_CACHE0_PULL1_ENGINE_SW 0x00000000 /* RW--V */ |
794 |
#define NV_PFIFO_CACHE0_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ |
795 |
#define NV_PFIFO_CACHE0_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ |
796 |
#define NV_PFIFO_CACHE1_PULL1 0x00003254 /* RW-4R */ |
797 |
#define NV_PFIFO_CACHE1_PULL1_ENGINE 1:0 /* RWXUF */ |
798 |
#define NV_PFIFO_CACHE1_PULL1_ENGINE_SW 0x00000000 /* RW--V */ |
799 |
#define NV_PFIFO_CACHE1_PULL1_ENGINE_GRAPHICS 0x00000001 /* RW--V */ |
800 |
#define NV_PFIFO_CACHE1_PULL1_ENGINE_DVD 0x00000002 /* RW--V */ |
801 |
#define NV_PFIFO_CACHE0_HASH 0x00003058 /* RW-4R */ |
802 |
#define NV_PFIFO_CACHE0_HASH_INSTANCE 15:0 /* RWXUF */ |
803 |
#define NV_PFIFO_CACHE0_HASH_VALID 16:16 /* RWXVF */ |
804 |
#define NV_PFIFO_CACHE1_HASH 0x00003258 /* RW-4R */ |
805 |
#define NV_PFIFO_CACHE1_HASH_INSTANCE 15:0 /* RWXUF */ |
806 |
#define NV_PFIFO_CACHE1_HASH_VALID 16:16 /* RWXVF */ |
807 |
#define NV_PFIFO_CACHE0_STATUS 0x00003014 /* R--4R */ |
808 |
#define NV_PFIFO_CACHE0_STATUS_LOW_MARK 4:4 /* R--VF */ |
809 |
#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ |
810 |
#define NV_PFIFO_CACHE0_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ |
811 |
#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK 8:8 /* R--VF */ |
812 |
#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ |
813 |
#define NV_PFIFO_CACHE0_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ |
814 |
#define NV_PFIFO_CACHE1_STATUS 0x00003214 /* R--4R */ |
815 |
#define NV_PFIFO_CACHE1_STATUS_LOW_MARK 4:4 /* R--VF */ |
816 |
#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ |
817 |
#define NV_PFIFO_CACHE1_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ |
818 |
#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK 8:8 /* R--VF */ |
819 |
#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ |
820 |
#define NV_PFIFO_CACHE1_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ |
821 |
#define NV_PFIFO_CACHE1_STATUS1 0x00003218 /* R--4R */ |
822 |
#define NV_PFIFO_CACHE1_STATUS1_RANOUT 0:0 /* R-XVF */ |
823 |
#define NV_PFIFO_CACHE1_STATUS1_RANOUT_FALSE 0x00000000 /* R---V */ |
824 |
#define NV_PFIFO_CACHE1_STATUS1_RANOUT_TRUE 0x00000001 /* R---V */ |
825 |
#define NV_PFIFO_CACHE0_PUT 0x00003010 /* RW-4R */ |
826 |
#define NV_PFIFO_CACHE0_PUT_ADDRESS 2:2 /* RWXUF */ |
827 |
#define NV_PFIFO_CACHE1_PUT 0x00003210 /* RW-4R */ |
828 |
#define NV_PFIFO_CACHE1_PUT_ADDRESS 9:2 /* RWXUF */ |
829 |
#define NV_PFIFO_CACHE0_GET 0x00003070 /* RW-4R */ |
830 |
#define NV_PFIFO_CACHE0_GET_ADDRESS 2:2 /* RWXUF */ |
831 |
#define NV_PFIFO_CACHE1_GET 0x00003270 /* RW-4R */ |
832 |
#define NV_PFIFO_CACHE1_GET_ADDRESS 9:2 /* RWXUF */ |
833 |
#define NV_PFIFO_CACHE0_ENGINE 0x00003080 /* RW-4R */ |
834 |
#define NV_PFIFO_CACHE0_ENGINE_0 1:0 /* RWXUF */ |
835 |
#define NV_PFIFO_CACHE0_ENGINE_0_SW 0x00000000 /* RW--V */ |
836 |
#define NV_PFIFO_CACHE0_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ |
837 |
#define NV_PFIFO_CACHE0_ENGINE_0_DVD 0x00000002 /* RW--V */ |
838 |
#define NV_PFIFO_CACHE0_ENGINE_1 5:4 /* RWXUF */ |
839 |
#define NV_PFIFO_CACHE0_ENGINE_1_SW 0x00000000 /* RW--V */ |
840 |
#define NV_PFIFO_CACHE0_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ |
841 |
#define NV_PFIFO_CACHE0_ENGINE_1_DVD 0x00000002 /* RW--V */ |
842 |
#define NV_PFIFO_CACHE0_ENGINE_2 9:8 /* RWXUF */ |
843 |
#define NV_PFIFO_CACHE0_ENGINE_2_SW 0x00000000 /* RW--V */ |
844 |
#define NV_PFIFO_CACHE0_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ |
845 |
#define NV_PFIFO_CACHE0_ENGINE_2_DVD 0x00000002 /* RW--V */ |
846 |
#define NV_PFIFO_CACHE0_ENGINE_3 13:12 /* RWXUF */ |
847 |
#define NV_PFIFO_CACHE0_ENGINE_3_SW 0x00000000 /* RW--V */ |
848 |
#define NV_PFIFO_CACHE0_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ |
849 |
#define NV_PFIFO_CACHE0_ENGINE_3_DVD 0x00000002 /* RW--V */ |
850 |
#define NV_PFIFO_CACHE0_ENGINE_4 17:16 /* RWXUF */ |
851 |
#define NV_PFIFO_CACHE0_ENGINE_4_SW 0x00000000 /* RW--V */ |
852 |
#define NV_PFIFO_CACHE0_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ |
853 |
#define NV_PFIFO_CACHE0_ENGINE_4_DVD 0x00000002 /* RW--V */ |
854 |
#define NV_PFIFO_CACHE0_ENGINE_5 21:20 /* RWXUF */ |
855 |
#define NV_PFIFO_CACHE0_ENGINE_5_SW 0x00000000 /* RW--V */ |
856 |
#define NV_PFIFO_CACHE0_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ |
857 |
#define NV_PFIFO_CACHE0_ENGINE_5_DVD 0x00000002 /* RW--V */ |
858 |
#define NV_PFIFO_CACHE0_ENGINE_6 25:24 /* RWXUF */ |
859 |
#define NV_PFIFO_CACHE0_ENGINE_6_SW 0x00000000 /* RW--V */ |
860 |
#define NV_PFIFO_CACHE0_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ |
861 |
#define NV_PFIFO_CACHE0_ENGINE_6_DVD 0x00000002 /* RW--V */ |
862 |
#define NV_PFIFO_CACHE0_ENGINE_7 29:28 /* RWXUF */ |
863 |
#define NV_PFIFO_CACHE0_ENGINE_7_SW 0x00000000 /* RW--V */ |
864 |
#define NV_PFIFO_CACHE0_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ |
865 |
#define NV_PFIFO_CACHE0_ENGINE_7_DVD 0x00000002 /* RW--V */ |
866 |
#define NV_PFIFO_CACHE1_ENGINE 0x00003280 /* RW-4R */ |
867 |
#define NV_PFIFO_CACHE1_ENGINE_0 1:0 /* RWXUF */ |
868 |
#define NV_PFIFO_CACHE1_ENGINE_0_SW 0x00000000 /* RW--V */ |
869 |
#define NV_PFIFO_CACHE1_ENGINE_0_GRAPHICS 0x00000001 /* RW--V */ |
870 |
#define NV_PFIFO_CACHE1_ENGINE_0_DVD 0x00000002 /* RW--V */ |
871 |
#define NV_PFIFO_CACHE1_ENGINE_1 5:4 /* RWXUF */ |
872 |
#define NV_PFIFO_CACHE1_ENGINE_1_SW 0x00000000 /* RW--V */ |
873 |
#define NV_PFIFO_CACHE1_ENGINE_1_GRAPHICS 0x00000001 /* RW--V */ |
874 |
#define NV_PFIFO_CACHE1_ENGINE_1_DVD 0x00000002 /* RW--V */ |
875 |
#define NV_PFIFO_CACHE1_ENGINE_2 9:8 /* RWXUF */ |
876 |
#define NV_PFIFO_CACHE1_ENGINE_2_SW 0x00000000 /* RW--V */ |
877 |
#define NV_PFIFO_CACHE1_ENGINE_2_GRAPHICS 0x00000001 /* RW--V */ |
878 |
#define NV_PFIFO_CACHE1_ENGINE_2_DVD 0x00000002 /* RW--V */ |
879 |
#define NV_PFIFO_CACHE1_ENGINE_3 13:12 /* RWXUF */ |
880 |
#define NV_PFIFO_CACHE1_ENGINE_3_SW 0x00000000 /* RW--V */ |
881 |
#define NV_PFIFO_CACHE1_ENGINE_3_GRAPHICS 0x00000001 /* RW--V */ |
882 |
#define NV_PFIFO_CACHE1_ENGINE_3_DVD 0x00000002 /* RW--V */ |
883 |
#define NV_PFIFO_CACHE1_ENGINE_4 17:16 /* RWXUF */ |
884 |
#define NV_PFIFO_CACHE1_ENGINE_4_SW 0x00000000 /* RW--V */ |
885 |
#define NV_PFIFO_CACHE1_ENGINE_4_GRAPHICS 0x00000001 /* RW--V */ |
886 |
#define NV_PFIFO_CACHE1_ENGINE_4_DVD 0x00000002 /* RW--V */ |
887 |
#define NV_PFIFO_CACHE1_ENGINE_5 21:20 /* RWXUF */ |
888 |
#define NV_PFIFO_CACHE1_ENGINE_5_SW 0x00000000 /* RW--V */ |
889 |
#define NV_PFIFO_CACHE1_ENGINE_5_GRAPHICS 0x00000001 /* RW--V */ |
890 |
#define NV_PFIFO_CACHE1_ENGINE_5_DVD 0x00000002 /* RW--V */ |
891 |
#define NV_PFIFO_CACHE1_ENGINE_6 25:24 /* RWXUF */ |
892 |
#define NV_PFIFO_CACHE1_ENGINE_6_SW 0x00000000 /* RW--V */ |
893 |
#define NV_PFIFO_CACHE1_ENGINE_6_GRAPHICS 0x00000001 /* RW--V */ |
894 |
#define NV_PFIFO_CACHE1_ENGINE_6_DVD 0x00000002 /* RW--V */ |
895 |
#define NV_PFIFO_CACHE1_ENGINE_7 29:28 /* RWXUF */ |
896 |
#define NV_PFIFO_CACHE1_ENGINE_7_SW 0x00000000 /* RW--V */ |
897 |
#define NV_PFIFO_CACHE1_ENGINE_7_GRAPHICS 0x00000001 /* RW--V */ |
898 |
#define NV_PFIFO_CACHE1_ENGINE_7_DVD 0x00000002 /* RW--V */ |
899 |
#define NV_PFIFO_CACHE0_METHOD(i) (0x00003100+(i)*8) /* RW-4A */ |
900 |
#define NV_PFIFO_CACHE0_METHOD__SIZE_1 1 /* */ |
901 |
#define NV_PFIFO_CACHE0_METHOD_ADDRESS 12:2 /* RWXUF */ |
902 |
#define NV_PFIFO_CACHE0_METHOD_SUBCHANNEL 15:13 /* RWXUF */ |
903 |
#define NV_PFIFO_CACHE1_METHOD(i) (0x00003800+(i)*8) /* RW-4A */ |
904 |
#define NV_PFIFO_CACHE1_METHOD__SIZE_1 128 /* */ |
905 |
#define NV_PFIFO_CACHE1_METHOD_ADDRESS 12:2 /* RWXUF */ |
906 |
#define NV_PFIFO_CACHE1_METHOD_SUBCHANNEL 15:13 /* RWXUF */ |
907 |
#define NV_PFIFO_CACHE1_METHOD_ALIAS(i) (0x00003C00+(i)*8) /* RW-4A */ |
908 |
#define NV_PFIFO_CACHE1_METHOD_ALIAS__SIZE_1 128 /* */ |
909 |
#define NV_PFIFO_CACHE0_DATA(i) (0x00003104+(i)*8) /* RW-4A */ |
910 |
#define NV_PFIFO_CACHE0_DATA__SIZE_1 1 /* */ |
911 |
#define NV_PFIFO_CACHE0_DATA_VALUE 31:0 /* RWXVF */ |
912 |
#define NV_PFIFO_CACHE1_DATA(i) (0x00003804+(i)*8) /* RW-4A */ |
913 |
#define NV_PFIFO_CACHE1_DATA__SIZE_1 128 /* */ |
914 |
#define NV_PFIFO_CACHE1_DATA_VALUE 31:0 /* RWXVF */ |
915 |
#define NV_PFIFO_CACHE1_DATA_ALIAS(i) (0x00003C04+(i)*8) /* RW-4A */ |
916 |
#define NV_PFIFO_CACHE1_DATA_ALIAS__SIZE_1 128 /* */ |
917 |
#define NV_PFIFO_DEVICE(i) (0x00002800+(i)*4) /* R--4A */ |
918 |
#define NV_PFIFO_DEVICE__SIZE_1 128 /* */ |
919 |
#define NV_PFIFO_DEVICE_CHID 3:0 /* R--UF */ |
920 |
#define NV_PFIFO_DEVICE_SWITCH 24:24 /* R--VF */ |
921 |
#define NV_PFIFO_DEVICE_SWITCH_UNAVAILABLE 0x00000000 /* R---V */ |
922 |
#define NV_PFIFO_DEVICE_SWITCH_AVAILABLE 0x00000001 /* R---V */ |
923 |
#define NV_PFIFO_RUNOUT_STATUS 0x00002400 /* R--4R */ |
924 |
#define NV_PFIFO_RUNOUT_STATUS_RANOUT 0:0 /* R--VF */ |
925 |
#define NV_PFIFO_RUNOUT_STATUS_RANOUT_FALSE 0x00000000 /* R---V */ |
926 |
#define NV_PFIFO_RUNOUT_STATUS_RANOUT_TRUE 0x00000001 /* R---V */ |
927 |
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK 4:4 /* R--VF */ |
928 |
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_NOT_EMPTY 0x00000000 /* R---V */ |
929 |
#define NV_PFIFO_RUNOUT_STATUS_LOW_MARK_EMPTY 0x00000001 /* R---V */ |
930 |
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK 8:8 /* R--VF */ |
931 |
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_NOT_FULL 0x00000000 /* R---V */ |
932 |
#define NV_PFIFO_RUNOUT_STATUS_HIGH_MARK_FULL 0x00000001 /* R---V */ |
933 |
#define NV_PFIFO_RUNOUT_PUT 0x00002410 /* RW-4R */ |
934 |
#define NV_PFIFO_RUNOUT_PUT_ADDRESS 12:3 /* RWXUF */ |
935 |
#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_0 8:3 /* RWXUF */ |
936 |
#define NV_PFIFO_RUNOUT_PUT_ADDRESS__SIZE_1 12:3 /* RWXUF */ |
937 |
#define NV_PFIFO_RUNOUT_GET 0x00002420 /* RW-4R */ |
938 |
#define NV_PFIFO_RUNOUT_GET_ADDRESS 13:3 /* RWXUF */ |
939 |
/* dev_graphics.ref */ |
940 |
#define NV_PGRAPH 0x00401FFF:0x00400000 /* RW--D */ |
941 |
#define NV_PGRAPH_DEBUG_0 0x00400080 /* RW-4R */ |
942 |
#define NV_PGRAPH_DEBUG_1 0x00400084 /* RW-4R */ |
943 |
#define NV_PGRAPH_DEBUG_2 0x00400088 /* RW-4R */ |
944 |
#define NV_PGRAPH_DEBUG_3 0x0040008C /* RW-4R */ |
945 |
#define NV_PGRAPH_INTR 0x00400100 /* RW-4R */ |
946 |
#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWIVF */ |
947 |
#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ |
948 |
#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */ |
949 |
#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--C */ |
950 |
#define NV_PGRAPH_INTR_MISSING_HW 4:4 /* RWIVF */ |
951 |
#define NV_PGRAPH_INTR_MISSING_HW_NOT_PENDING 0x00000000 /* R-I-V */ |
952 |
#define NV_PGRAPH_INTR_MISSING_HW_PENDING 0x00000001 /* R---V */ |
953 |
#define NV_PGRAPH_INTR_MISSING_HW_RESET 0x00000001 /* -W--C */ |
954 |
#define NV_PGRAPH_INTR_TLB_PRESENT_A 8:8 /* RWIVF */ |
955 |
#define NV_PGRAPH_INTR_TLB_PRESENT_A_NOT_PENDING 0x00000000 /* R-I-V */ |
956 |
#define NV_PGRAPH_INTR_TLB_PRESENT_A_PENDING 0x00000001 /* R---V */ |
957 |
#define NV_PGRAPH_INTR_TLB_PRESENT_A_RESET 0x00000001 /* -W--C */ |
958 |
#define NV_PGRAPH_INTR_TLB_PRESENT_B 9:9 /* RWIVF */ |
959 |
#define NV_PGRAPH_INTR_TLB_PRESENT_B_NOT_PENDING 0x00000000 /* R-I-V */ |
960 |
#define NV_PGRAPH_INTR_TLB_PRESENT_B_PENDING 0x00000001 /* R---V */ |
961 |
#define NV_PGRAPH_INTR_TLB_PRESENT_B_RESET 0x00000001 /* -W--C */ |
962 |
#define NV_PGRAPH_INTR_CONTEXT_SWITCH 12:12 /* RWIVF */ |
963 |
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */ |
964 |
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_PENDING 0x00000001 /* R---V */ |
965 |
#define NV_PGRAPH_INTR_CONTEXT_SWITCH_RESET 0x00000001 /* -W--C */ |
966 |
#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWIVF */ |
967 |
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ |
968 |
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */ |
969 |
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--C */ |
970 |
#define NV_PGRAPH_NSTATUS 0x00400104 /* RW-4R */ |
971 |
#define NV_PGRAPH_NSTATUS_STATE_IN_USE 11:11 /* RWIVF */ |
972 |
#define NV_PGRAPH_NSTATUS_STATE_IN_USE_NOT_PENDING 0x00000000 /* RWI-V */ |
973 |
#define NV_PGRAPH_NSTATUS_STATE_IN_USE_PENDING 0x00000001 /* RW--V */ |
974 |
#define NV_PGRAPH_NSTATUS_INVALID_STATE 12:12 /* RWIVF */ |
975 |
#define NV_PGRAPH_NSTATUS_INVALID_STATE_NOT_PENDING 0x00000000 /* RWI-V */ |
976 |
#define NV_PGRAPH_NSTATUS_INVALID_STATE_PENDING 0x00000001 /* RW--V */ |
977 |
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT 13:13 /* RWIVF */ |
978 |
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_NOT_PENDING 0x00000000 /* RWI-V */ |
979 |
#define NV_PGRAPH_NSTATUS_BAD_ARGUMENT_PENDING 0x00000001 /* RW--V */ |
980 |
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT 14:14 /* RWIVF */ |
981 |
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_NOT_PENDING 0x00000000 /* RWI-V */ |
982 |
#define NV_PGRAPH_NSTATUS_PROTECTION_FAULT_PENDING 0x00000001 /* RW--V */ |
983 |
#define NV_PGRAPH_NSOURCE 0x00400108 /* R--4R */ |
984 |
#define NV_PGRAPH_NSOURCE_NOTIFICATION 0:0 /* R-IVF */ |
985 |
#define NV_PGRAPH_NSOURCE_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ |
986 |
#define NV_PGRAPH_NSOURCE_NOTIFICATION_PENDING 0x00000001 /* R---V */ |
987 |
#define NV_PGRAPH_NSOURCE_DATA_ERROR 1:1 /* R-IVF */ |
988 |
#define NV_PGRAPH_NSOURCE_DATA_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ |
989 |
#define NV_PGRAPH_NSOURCE_DATA_ERROR_PENDING 0x00000001 /* R---V */ |
990 |
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR 2:2 /* R-IVF */ |
991 |
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ |
992 |
#define NV_PGRAPH_NSOURCE_PROTECTION_ERROR_PENDING 0x00000001 /* R---V */ |
993 |
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION 3:3 /* R-IVF */ |
994 |
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ |
995 |
#define NV_PGRAPH_NSOURCE_RANGE_EXCEPTION_PENDING 0x00000001 /* R---V */ |
996 |
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR 4:4 /* R-IVF */ |
997 |
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_NOT_PENDING 0x00000000 /* R-I-V */ |
998 |
#define NV_PGRAPH_NSOURCE_LIMIT_COLOR_PENDING 0x00000001 /* R---V */ |
999 |
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_ 5:5 /* R-IVF */ |
1000 |
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_NOT_PENDING 0x00000000 /* R-I-V */ |
1001 |
#define NV_PGRAPH_NSOURCE_LIMIT_ZETA_PENDING 0x00000001 /* R---V */ |
1002 |
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD 6:6 /* R-IVF */ |
1003 |
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_NOT_PENDING 0x00000000 /* R-I-V */ |
1004 |
#define NV_PGRAPH_NSOURCE_ILLEGAL_MTHD_PENDING 0x00000001 /* R---V */ |
1005 |
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION 7:7 /* R-IVF */ |
1006 |
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ |
1007 |
#define NV_PGRAPH_NSOURCE_DMA_R_PROTECTION_PENDING 0x00000001 /* R---V */ |
1008 |
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION 8:8 /* R-IVF */ |
1009 |
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_NOT_PENDING 0x00000000 /* R-I-V */ |
1010 |
#define NV_PGRAPH_NSOURCE_DMA_W_PROTECTION_PENDING 0x00000001 /* R---V */ |
1011 |
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION 9:9 /* R-IVF */ |
1012 |
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ |
1013 |
#define NV_PGRAPH_NSOURCE_FORMAT_EXCEPTION_PENDING 0x00000001 /* R---V */ |
1014 |
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION 10:10 /* R-IVF */ |
1015 |
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_NOT_PENDING 0x00000000 /* R-I-V */ |
1016 |
#define NV_PGRAPH_NSOURCE_PATCH_EXCEPTION_PENDING 0x00000001 /* R---V */ |
1017 |
#define NV_PGRAPH_NSOURCE_STATE_INVALID 11:11 /* R-IVF */ |
1018 |
#define NV_PGRAPH_NSOURCE_STATE_INVALID_NOT_PENDING 0x00000000 /* R-I-V */ |
1019 |
#define NV_PGRAPH_NSOURCE_STATE_INVALID_PENDING 0x00000001 /* R---V */ |
1020 |
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY 12:12 /* R-IVF */ |
1021 |
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_NOT_PENDING 0x00000000 /* R-I-V */ |
1022 |
#define NV_PGRAPH_NSOURCE_DOUBLE_NOTIFY_PENDING 0x00000001 /* R---V */ |
1023 |
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE 13:13 /* R-IVF */ |
1024 |
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_NOT_PENDING 0x00000000 /* R-I-V */ |
1025 |
#define NV_PGRAPH_NSOURCE_NOTIFY_IN_USE_PENDING 0x00000001 /* R---V */ |
1026 |
#define NV_PGRAPH_NSOURCE_METHOD_CNT 14:14 /* R-IVF */ |
1027 |
#define NV_PGRAPH_NSOURCE_METHOD_CNT_NOT_PENDING 0x00000000 /* R-I-V */ |
1028 |
#define NV_PGRAPH_NSOURCE_METHOD_CNT_PENDING 0x00000001 /* R---V */ |
1029 |
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION 15:15 /* R-IVF */ |
1030 |
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_NOT_PENDING 0x00000000 /* R-I-V */ |
1031 |
#define NV_PGRAPH_NSOURCE_BFR_NOTIFICATION_PENDING 0x00000001 /* R---V */ |
1032 |
#define NV_PGRAPH_INTR_EN 0x00400140 /* RW-4R */ |
1033 |
#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWIVF */ |
1034 |
#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWI-V */ |
1035 |
#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */ |
1036 |
#define NV_PGRAPH_INTR_EN_MISSING_HW 4:4 /* RWIVF */ |
1037 |
#define NV_PGRAPH_INTR_EN_MISSING_HW_DISABLED 0x00000000 /* RWI-V */ |
1038 |
#define NV_PGRAPH_INTR_EN_MISSING_HW_ENABLED 0x00000001 /* RW--V */ |
1039 |
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A 8:8 /* RWIVF */ |
1040 |
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_DISABLED 0x00000000 /* RWI-V */ |
1041 |
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_A_ENABLED 0x00000001 /* RW--V */ |
1042 |
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B 9:9 /* RWIVF */ |
1043 |
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_DISABLED 0x00000000 /* RWI-V */ |
1044 |
#define NV_PGRAPH_INTR_EN_TLB_PRESENT_B_ENABLED 0x00000001 /* RW--V */ |
1045 |
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH 12:12 /* RWIVF */ |
1046 |
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_DISABLED 0x00000000 /* RWI-V */ |
1047 |
#define NV_PGRAPH_INTR_EN_CONTEXT_SWITCH_ENABLED 0x00000001 /* RW--V */ |
1048 |
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWIVF */ |
1049 |
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWI-V */ |
1050 |
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */ |
1051 |
#define NV_PGRAPH_CTX_SWITCH1 0x00400160 /* RW-4R */ |
1052 |
#define NV_PGRAPH_CTX_SWITCH1_GRCLASS 7:0 /* RWXVF */ |
1053 |
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY 12:12 /* RWXUF */ |
1054 |
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_DISABLE 0x00000000 /* RW--V */ |
1055 |
#define NV_PGRAPH_CTX_SWITCH1_CHROMA_KEY_ENABLE 0x00000001 /* RW--V */ |
1056 |
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP 13:13 /* RWXUF */ |
1057 |
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_DISABLE 0x00000000 /* RW--V */ |
1058 |
#define NV_PGRAPH_CTX_SWITCH1_USER_CLIP_ENABLE 0x00000001 /* RW--V */ |
1059 |
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE 14:14 /* RWXUF */ |
1060 |
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_DISABLE 0x00000000 /* RW--V */ |
1061 |
#define NV_PGRAPH_CTX_SWITCH1_SWIZZLE_ENABLE 0x00000001 /* RW--V */ |
1062 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG 17:15 /* RWXUF */ |
1063 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_AND 0x00000000 /* RW--V */ |
1064 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_ROP_AND 0x00000001 /* RW--V */ |
1065 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_AND 0x00000002 /* RW--V */ |
1066 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY 0x00000003 /* RW--V */ |
1067 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_SRCCOPY_PRE 0x00000004 /* RW--V */ |
1068 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_CONFIG_BLEND_PRE 0x00000005 /* RW--V */ |
1069 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS 24:24 /* RWXUF */ |
1070 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_INVALID 0x00000000 /* RW--V */ |
1071 |
#define NV_PGRAPH_CTX_SWITCH1_PATCH_STATUS_VALID 0x00000001 /* RW--V */ |
1072 |
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE 25:25 /* RWXUF */ |
1073 |
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_INVALID 0x00000000 /* RW--V */ |
1074 |
#define NV_PGRAPH_CTX_SWITCH1_CONTEXT_SURFACE_VALID 0x00000001 /* RW--V */ |
1075 |
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET 31:31 /* CWIVF */ |
1076 |
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_IGNORE 0x00000000 /* CWI-V */ |
1077 |
#define NV_PGRAPH_CTX_SWITCH1_VOLATILE_RESET_ENABLED 0x00000001 /* -W--T */ |
1078 |
#define NV_PGRAPH_CTX_SWITCH2 0x00400164 /* RW-4R */ |
1079 |
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT 1:0 /* RWXUF */ |
1080 |
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_INVALID 0x00 /* RW--V */ |
1081 |
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_CGA6_M1 0x01 /* RW--V */ |
1082 |
#define NV_PGRAPH_CTX_SWITCH2_MONO_FORMAT_LE_M1 0x02 /* RW--V */ |
1083 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT 13:8 /* RWXUF */ |
1084 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_INVALID 0x00 /* RW--V */ |
1085 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y8 0x01 /* RW--V */ |
1086 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A8Y8 0x02 /* RW--V */ |
1087 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X24Y8 0x03 /* RW--V */ |
1088 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A1R5G5B5 0x06 /* RW--V */ |
1089 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X1R5G5B5 0x07 /* RW--V */ |
1090 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16A1R5G5B5 0x08 /* RW--V */ |
1091 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X17R5G5B5 0x09 /* RW--V */ |
1092 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_R5G6B5 0x0A /* RW--V */ |
1093 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16R5G6B5 0x0B /* RW--V */ |
1094 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16R5G6B5 0x0C /* RW--V */ |
1095 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A8R8G8B8 0x0D /* RW--V */ |
1096 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X8R8G8B8 0x0E /* RW--V */ |
1097 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y16 0x0F /* RW--V */ |
1098 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_A16Y16 0x10 /* RW--V */ |
1099 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_X16Y16 0x11 /* RW--V */ |
1100 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ |
1101 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ |
1102 |
#define NV_PGRAPH_CTX_SWITCH2_COLOR_FORMAT_LE_Y32 0x14 /* RW--V */ |
1103 |
#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE 31:16 /* RWXUF */ |
1104 |
#define NV_PGRAPH_CTX_SWITCH2_NOTIFY_INSTANCE_INVALID 0x0000 /* RW--V */ |
1105 |
#define NV_PGRAPH_CTX_SWITCH3 0x00400168 /* RW-4R */ |
1106 |
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0 15:0 /* RWXUF */ |
1107 |
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_0_INVALID 0x0000 /* RW--V */ |
1108 |
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1 31:16 /* RWXUF */ |
1109 |
#define NV_PGRAPH_CTX_SWITCH3_DMA_INSTANCE_1_INVALID 0x0000 /* RW--V */ |
1110 |
#define NV_PGRAPH_CTX_SWITCH4 0x0040016C /* RW-4R */ |
1111 |
#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE 15:0 /* RWXUF */ |
1112 |
#define NV_PGRAPH_CTX_SWITCH4_USER_INSTANCE_INVALID 0x0000 /* RW--V */ |
1113 |
#define NV_PGRAPH_CTX_CACHE1(i) (0x00400180+(i)*4) /* RW-4A */ |
1114 |
#define NV_PGRAPH_CTX_CACHE1__SIZE_1 8 /* */ |
1115 |
#define NV_PGRAPH_CTX_CACHE1_GRCLASS 7:0 /* RWXVF */ |
1116 |
#define NV_PGRAPH_CTX_CACHE1_CHROMA_KEY 12:12 /* RWXVF */ |
1117 |
#define NV_PGRAPH_CTX_CACHE1_USER_CLIP 13:13 /* RWXVF */ |
1118 |
#define NV_PGRAPH_CTX_CACHE1_SWIZZLE 14:14 /* RWXVF */ |
1119 |
#define NV_PGRAPH_CTX_CACHE1_PATCH_CONFIG 19:15 /* RWXVF */ |
1120 |
#define NV_PGRAPH_CTX_CACHE1_SPARE1 20:20 /* RWXVF */ |
1121 |
#define NV_PGRAPH_CTX_CACHE1_PATCH_STATUS 24:24 /* RWXVF */ |
1122 |
#define NV_PGRAPH_CTX_CACHE1_CONTEXT_SURFACE 25:25 /* RWXVF */ |
1123 |
#define NV_PGRAPH_CTX_CACHE2(i) (0x004001a0+(i)*4) /* RW-4A */ |
1124 |
#define NV_PGRAPH_CTX_CACHE2__SIZE_1 8 /* */ |
1125 |
#define NV_PGRAPH_CTX_CACHE2_MONO_FORMAT 1:0 /* RWXVF */ |
1126 |
#define NV_PGRAPH_CTX_CACHE2_COLOR_FORMAT 13:8 /* RWXVF */ |
1127 |
#define NV_PGRAPH_CTX_CACHE2_NOTIFY_INSTANCE 31:16 /* RWXVF */ |
1128 |
#define NV_PGRAPH_CTX_CACHE3(i) (0x004001c0+(i)*4) /* RW-4A */ |
1129 |
#define NV_PGRAPH_CTX_CACHE3__SIZE_1 8 /* */ |
1130 |
#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_0 15:0 /* RWXVF */ |
1131 |
#define NV_PGRAPH_CTX_CACHE3_DMA_INSTANCE_1 31:16 /* RWXVF */ |
1132 |
#define NV_PGRAPH_CTX_CACHE4(i) (0x004001e0+(i)*4) /* RW-4A */ |
1133 |
#define NV_PGRAPH_CTX_CACHE4__SIZE_1 8 /* */ |
1134 |
#define NV_PGRAPH_CTX_CACHE4_USER_INSTANCE 15:0 /* RWXVF */ |
1135 |
#define NV_PGRAPH_CTX_CONTROL 0x00400170 /* RW-4R */ |
1136 |
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME 1:0 /* RWIVF */ |
1137 |
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_33US 0x00000000 /* RWI-V */ |
1138 |
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_262US 0x00000001 /* RW--V */ |
1139 |
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_2MS 0x00000002 /* RW--V */ |
1140 |
#define NV_PGRAPH_CTX_CONTROL_MINIMUM_TIME_17MS 0x00000003 /* RW--V */ |
1141 |
#define NV_PGRAPH_CTX_CONTROL_TIME 8:8 /* RWIVF */ |
1142 |
#define NV_PGRAPH_CTX_CONTROL_TIME_EXPIRED 0x00000000 /* RWI-V */ |
1143 |
#define NV_PGRAPH_CTX_CONTROL_TIME_NOT_EXPIRED 0x00000001 /* RW--V */ |
1144 |
#define NV_PGRAPH_CTX_CONTROL_CHID 16:16 /* RWIVF */ |
1145 |
#define NV_PGRAPH_CTX_CONTROL_CHID_INVALID 0x00000000 /* RWI-V */ |
1146 |
#define NV_PGRAPH_CTX_CONTROL_CHID_VALID 0x00000001 /* RW--V */ |
1147 |
#define NV_PGRAPH_CTX_CONTROL_CHANGE 20:20 /* R--VF */ |
1148 |
#define NV_PGRAPH_CTX_CONTROL_CHANGE_UNAVAILABLE 0x00000000 /* R---V */ |
1149 |
#define NV_PGRAPH_CTX_CONTROL_CHANGE_AVAILABLE 0x00000001 /* R---V */ |
1150 |
#define NV_PGRAPH_CTX_CONTROL_SWITCHING 24:24 /* RWIVF */ |
1151 |
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_IDLE 0x00000000 /* RWI-V */ |
1152 |
#define NV_PGRAPH_CTX_CONTROL_SWITCHING_BUSY 0x00000001 /* RW--V */ |
1153 |
#define NV_PGRAPH_CTX_CONTROL_DEVICE 28:28 /* RWIVF */ |
1154 |
#define NV_PGRAPH_CTX_CONTROL_DEVICE_DISABLED 0x00000000 /* RWI-V */ |
1155 |
#define NV_PGRAPH_CTX_CONTROL_DEVICE_ENABLED 0x00000001 /* RW--V */ |
1156 |
#define NV_PGRAPH_CTX_USER 0x00400174 /* RW-4R */ |
1157 |
#define NV_PGRAPH_CTX_USER_SUBCH 15:13 /* RWIVF */ |
1158 |
#define NV_PGRAPH_CTX_USER_SUBCH_0 0x00000000 /* RWI-V */ |
1159 |
#define NV_PGRAPH_CTX_USER_CHID 27:24 /* RWIVF */ |
1160 |
#define NV_PGRAPH_CTX_USER_CHID_0 0x00000000 /* RWI-V */ |
1161 |
#define NV_PGRAPH_FIFO 0x00400720 /* RW-4R */ |
1162 |
#define NV_PGRAPH_FIFO_ACCESS 0:0 /* RWIVF */ |
1163 |
#define NV_PGRAPH_FIFO_ACCESS_DISABLED 0x00000000 /* RW--V */ |
1164 |
#define NV_PGRAPH_FIFO_ACCESS_ENABLED 0x00000001 /* RWI-V */ |
1165 |
#define NV_PGRAPH_FFINTFC_FIFO_0(i) (0x00400730+(i)*4) /* RW-4A */ |
1166 |
#define NV_PGRAPH_FFINTFC_FIFO_0__SIZE_1 4 /* */ |
1167 |
#define NV_PGRAPH_FFINTFC_FIFO_0_TAG 0:0 /* RWXVF */ |
1168 |
#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_MTHD 0x00000000 /* RW--V */ |
1169 |
#define NV_PGRAPH_FFINTFC_FIFO_0_TAG_CHSW 0x00000001 /* RW--V */ |
1170 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH 3:1 /* RWXVF */ |
1171 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_0 0x00000000 /* RW--V */ |
1172 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_1 0x00000001 /* RW--V */ |
1173 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_2 0x00000002 /* RW--V */ |
1174 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_3 0x00000003 /* RW--V */ |
1175 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_4 0x00000004 /* RW--V */ |
1176 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_5 0x00000005 /* RW--V */ |
1177 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_6 0x00000006 /* RW--V */ |
1178 |
#define NV_PGRAPH_FFINTFC_FIFO_0_SUBCH_7 0x00000007 /* RW--V */ |
1179 |
#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD 14:4 /* RWXVF */ |
1180 |
#define NV_PGRAPH_FFINTFC_FIFO_0_MTHD_CTX_SWITCH 0x00000000 /* RW--V */ |
1181 |
#define NV_PGRAPH_FFINTFC_FIFO_1(i) (0x00400740+(i)*4) /* RW-4A */ |
1182 |
#define NV_PGRAPH_FFINTFC_FIFO_1__SIZE_1 4 /* */ |
1183 |
#define NV_PGRAPH_FFINTFC_FIFO_1_ARGUMENT 31:0 /* RWXVF */ |
1184 |
#define NV_PGRAPH_FFINTFC_FIFO_PTR 0x00400750 /* RW-4R */ |
1185 |
#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE 2:0 /* RWIVF */ |
1186 |
#define NV_PGRAPH_FFINTFC_FIFO_PTR_WRITE_0 0x00000000 /* RWI-V */ |
1187 |
#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ 6:4 /* RWIVF */ |
1188 |
#define NV_PGRAPH_FFINTFC_FIFO_PTR_READ_0 0x00000000 /* RWI-V */ |
1189 |
#define NV_PGRAPH_FFINTFC_ST2 0x00400754 /* RW-4R */ |
1190 |
#define NV_PGRAPH_FFINTFC_ST2_STATUS 0:0 /* RWIVF */ |
1191 |
#define NV_PGRAPH_FFINTFC_ST2_STATUS_INVALID 0x00000000 /* RWI-V */ |
1192 |
#define NV_PGRAPH_FFINTFC_ST2_STATUS_VALID 0x00000001 /* RW--V */ |
1193 |
#define NV_PGRAPH_FFINTFC_ST2_MTHD 11:1 /* RWIVF */ |
1194 |
#define NV_PGRAPH_FFINTFC_ST2_MTHD_CTX_SWITCH 0x00000000 /* RWI-V */ |
1195 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH 14:12 /* RWIVF */ |
1196 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_0 0x00000000 /* RWI-V */ |
1197 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_1 0x00000001 /* RW--V */ |
1198 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_2 0x00000002 /* RW--V */ |
1199 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_3 0x00000003 /* RW--V */ |
1200 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_4 0x00000004 /* RW--V */ |
1201 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_5 0x00000005 /* RW--V */ |
1202 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_6 0x00000006 /* RW--V */ |
1203 |
#define NV_PGRAPH_FFINTFC_ST2_SUBCH_7 0x00000007 /* RW--V */ |
1204 |
#define NV_PGRAPH_FFINTFC_ST2_CHID 18:15 /* RWIVF */ |
1205 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_0 0x00000000 /* RWI-V */ |
1206 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_1 0x00000001 /* RW--V */ |
1207 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_2 0x00000002 /* RW--V */ |
1208 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_3 0x00000003 /* RW--V */ |
1209 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_4 0x00000004 /* RW--V */ |
1210 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_5 0x00000005 /* RW--V */ |
1211 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_6 0x00000006 /* RW--V */ |
1212 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_7 0x00000007 /* RW--V */ |
1213 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_8 0x00000008 /* RW--V */ |
1214 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_9 0x00000009 /* RW--V */ |
1215 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_10 0x0000000A /* RW--V */ |
1216 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_11 0x0000000B /* RW--V */ |
1217 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_12 0x0000000C /* RW--V */ |
1218 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_13 0x0000000D /* RW--V */ |
1219 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_14 0x0000000E /* RW--V */ |
1220 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_15 0x0000000F /* RW--V */ |
1221 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS 19:19 /* RWIVF */ |
1222 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_INVALID 0x00000000 /* RWI-V */ |
1223 |
#define NV_PGRAPH_FFINTFC_ST2_CHID_STATUS_VALID 0x00000001 /* RW--V */ |
1224 |
#define NV_PGRAPH_FFINTFC_ST2_D 0x00400758 /* RW-4R */ |
1225 |
#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT 31:0 /* RWIVF */ |
1226 |
#define NV_PGRAPH_FFINTFC_ST2_D_ARGUMENT_0 0x00000000 /* RWI-V */ |
1227 |
#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */ |
1228 |
#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */ |
1229 |
#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */ |
1230 |
#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */ |
1231 |
#define NV_PGRAPH_STATUS_XY_LOGIC 4:4 /* R-IVF */ |
1232 |
#define NV_PGRAPH_STATUS_XY_LOGIC_IDLE 0x00000000 /* R-I-V */ |
1233 |
#define NV_PGRAPH_STATUS_XY_LOGIC_BUSY 0x00000001 /* R---V */ |
1234 |
#define NV_PGRAPH_STATUS_FE 5:5 /* R-IVF */ |
1235 |
#define NV_PGRAPH_STATUS_FE_IDLE 0x00000000 /* R-I-V */ |
1236 |
#define NV_PGRAPH_STATUS_FE_BUSY 0x00000001 /* R---V */ |
1237 |
#define NV_PGRAPH_STATUS_RASTERIZER 6:6 /* R-IVF */ |
1238 |
#define NV_PGRAPH_STATUS_RASTERIZER_IDLE 0x00000000 /* R-I-V */ |
1239 |
#define NV_PGRAPH_STATUS_RASTERIZER_BUSY 0x00000001 /* R---V */ |
1240 |
#define NV_PGRAPH_STATUS_PORT_NOTIFY 8:8 /* R-IVF */ |
1241 |
#define NV_PGRAPH_STATUS_PORT_NOTIFY_IDLE 0x00000000 /* R-I-V */ |
1242 |
#define NV_PGRAPH_STATUS_PORT_NOTIFY_BUSY 0x00000001 /* R---V */ |
1243 |
#define NV_PGRAPH_STATUS_PORT_REGISTER 12:12 /* R-IVF */ |
1244 |
#define NV_PGRAPH_STATUS_PORT_REGISTER_IDLE 0x00000000 /* R-I-V */ |
1245 |
#define NV_PGRAPH_STATUS_PORT_REGISTER_BUSY 0x00000001 /* R---V */ |
1246 |
#define NV_PGRAPH_STATUS_PORT_DMA 16:16 /* R-IVF */ |
1247 |
#define NV_PGRAPH_STATUS_PORT_DMA_IDLE 0x00000000 /* R-I-V */ |
1248 |
#define NV_PGRAPH_STATUS_PORT_DMA_BUSY 0x00000001 /* R---V */ |
1249 |
#define NV_PGRAPH_STATUS_DMA_ENGINE 17:17 /* R-IVF */ |
1250 |
#define NV_PGRAPH_STATUS_DMA_ENGINE_IDLE 0x00000000 /* R-I-V */ |
1251 |
#define NV_PGRAPH_STATUS_DMA_ENGINE_BUSY 0x00000001 /* R---V */ |
1252 |
#define NV_PGRAPH_STATUS_DMA_NOTIFY 20:20 /* R-IVF */ |
1253 |
#define NV_PGRAPH_STATUS_DMA_NOTIFY_IDLE 0x00000000 /* R-I-V */ |
1254 |
#define NV_PGRAPH_STATUS_DMA_NOTIFY_BUSY 0x00000001 /* R---V */ |
1255 |
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY 21:21 /* R-IVF */ |
1256 |
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_IDLE 0x00000000 /* R-I-V */ |
1257 |
#define NV_PGRAPH_STATUS_DMA_BUFFER_NOTIFY_BUSY 0x00000001 /* R---V */ |
1258 |
#define NV_PGRAPH_STATUS_D3D 24:24 /* R-IVF */ |
1259 |
#define NV_PGRAPH_STATUS_D3D_IDLE 0x00000000 /* R-I-V */ |
1260 |
#define NV_PGRAPH_STATUS_D3D_BUSY 0x00000001 /* R---V */ |
1261 |
#define NV_PGRAPH_STATUS_CACHE 25:25 /* R-IVF */ |
1262 |
#define NV_PGRAPH_STATUS_CACHE_IDLE 0x00000000 /* R-I-V */ |
1263 |
#define NV_PGRAPH_STATUS_CACHE_BUSY 0x00000001 /* R---V */ |
1264 |
#define NV_PGRAPH_STATUS_LIGHTING 26:26 /* R-IVF */ |
1265 |
#define NV_PGRAPH_STATUS_LIGHTING_IDLE 0x00000000 /* R-I-V */ |
1266 |
#define NV_PGRAPH_STATUS_LIGHTING_BUSY 0x00000001 /* R---V */ |
1267 |
#define NV_PGRAPH_STATUS_PREROP 27:27 /* R-IVF */ |
1268 |
#define NV_PGRAPH_STATUS_PREROP_IDLE 0x00000000 /* R-I-V */ |
1269 |
#define NV_PGRAPH_STATUS_PREROP_BUSY 0x00000001 /* R---V */ |
1270 |
#define NV_PGRAPH_STATUS_ROP 28:28 /* R-IVF */ |
1271 |
#define NV_PGRAPH_STATUS_ROP_IDLE 0x00000000 /* R-I-V */ |
1272 |
#define NV_PGRAPH_STATUS_ROP_BUSY 0x00000001 /* R---V */ |
1273 |
#define NV_PGRAPH_STATUS_PORT_USER 29:29 /* R-IVF */ |
1274 |
#define NV_PGRAPH_STATUS_PORT_USER_IDLE 0x00000000 /* R-I-V */ |
1275 |
#define NV_PGRAPH_STATUS_PORT_USER_BUSY 0x00000001 /* R---V */ |
1276 |
#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */ |
1277 |
#define NV_PGRAPH_TRAPPED_ADDR_MTHD 12:2 /* R-XUF */ |
1278 |
#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 15:13 /* R-XUF */ |
1279 |
#define NV_PGRAPH_TRAPPED_ADDR_CHID 27:24 /* R-XUF */ |
1280 |
#define NV_PGRAPH_TRAPPED_DATA 0x00400708 /* R--4R */ |
1281 |
#define NV_PGRAPH_TRAPPED_DATA_VALUE 31:0 /* R-XVF */ |
1282 |
#define NV_PGRAPH_SURFACE 0x0040070C /* RW-4R */ |
1283 |
#define NV_PGRAPH_SURFACE_TYPE 1:0 /* RWIVF */ |
1284 |
#define NV_PGRAPH_SURFACE_TYPE_INVALID 0x00000000 /* RWI-V */ |
1285 |
#define NV_PGRAPH_SURFACE_TYPE_NON_SWIZZLE 0x00000001 /* RW--V */ |
1286 |
#define NV_PGRAPH_SURFACE_TYPE_SWIZZLE 0x00000002 /* RW--V */ |
1287 |
#define NV_PGRAPH_NOTIFY 0x00400714 /* RW-4R */ |
1288 |
#define NV_PGRAPH_NOTIFY_BUFFER_REQ 0:0 /* RWIVF */ |
1289 |
#define NV_PGRAPH_NOTIFY_BUFFER_REQ_NOT_PENDING 0x00000000 /* RWI-V */ |
1290 |
#define NV_PGRAPH_NOTIFY_BUFFER_REQ_PENDING 0x00000001 /* RW--V */ |
1291 |
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE 8:8 /* RWIVF */ |
1292 |
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ |
1293 |
#define NV_PGRAPH_NOTIFY_BUFFER_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ |
1294 |
#define NV_PGRAPH_NOTIFY_REQ 16:16 /* RWIVF */ |
1295 |
#define NV_PGRAPH_NOTIFY_REQ_NOT_PENDING 0x00000000 /* RWI-V */ |
1296 |
#define NV_PGRAPH_NOTIFY_REQ_PENDING 0x00000001 /* RW--V */ |
1297 |
#define NV_PGRAPH_NOTIFY_STYLE 20:20 /* RWIVF */ |
1298 |
#define NV_PGRAPH_NOTIFY_STYLE_WRITE_ONLY 0x00000000 /* RWI-V */ |
1299 |
#define NV_PGRAPH_NOTIFY_STYLE_WRITE_THEN_AWAKEN 0x00000001 /* RW--V */ |
1300 |
#define NV_PGRAPH_BOFFSET(i) (0x00400640+(i)*4) /* RW-4A */ |
1301 |
#define NV_PGRAPH_BOFFSET__SIZE_1 6 /* */ |
1302 |
#define NV_PGRAPH_BOFFSET_LINADRS 23:0 /* RWIUF */ |
1303 |
#define NV_PGRAPH_BOFFSET_LINADRS_0 0x00000000 /* RWI-V */ |
1304 |
#define NV_PGRAPH_BOFFSET0 0x00400640 /* RW-4R */ |
1305 |
#define NV_PGRAPH_BOFFSET0__ALIAS_1 NV_PGRAPH_BOFFSET(0) /* */ |
1306 |
#define NV_PGRAPH_BOFFSET0_LINADRS 23:0 /* RWIUF */ |
1307 |
#define NV_PGRAPH_BOFFSET0_LINADRS_0 0x00000000 /* RWI-V */ |
1308 |
#define NV_PGRAPH_BOFFSET1 0x00400644 /* RW-4R */ |
1309 |
#define NV_PGRAPH_BOFFSET1__ALIAS_1 NV_PGRAPH_BOFFSET(1) /* */ |
1310 |
#define NV_PGRAPH_BOFFSET1_LINADRS 23:0 /* RWIUF */ |
1311 |
#define NV_PGRAPH_BOFFSET1_LINADRS_0 0x00000000 /* RWI-V */ |
1312 |
#define NV_PGRAPH_BOFFSET2 0x00400648 /* RW-4R */ |
1313 |
#define NV_PGRAPH_BOFFSET2__ALIAS_1 NV_PGRAPH_BOFFSET(2) /* */ |
1314 |
#define NV_PGRAPH_BOFFSET2_LINADRS 23:0 /* RWIUF */ |
1315 |
#define NV_PGRAPH_BOFFSET2_LINADRS_0 0x00000000 /* RWI-V */ |
1316 |
#define NV_PGRAPH_BOFFSET3 0x0040064C /* RW-4R */ |
1317 |
#define NV_PGRAPH_BOFFSET3__ALIAS_1 NV_PGRAPH_BOFFSET(3) /* */ |
1318 |
#define NV_PGRAPH_BOFFSET3_LINADRS 23:0 /* RWIUF */ |
1319 |
#define NV_PGRAPH_BOFFSET3_LINADRS_0 0x00000000 /* RWI-V */ |
1320 |
#define NV_PGRAPH_BOFFSET4 0x00400650 /* RW-4R */ |
1321 |
#define NV_PGRAPH_BOFFSET4__ALIAS_1 NV_PGRAPH_BOFFSET(4) /* */ |
1322 |
#define NV_PGRAPH_BOFFSET4_LINADRS 23:0 /* RWIUF */ |
1323 |
#define NV_PGRAPH_BOFFSET4_LINADRS_0 0x00000000 /* RWI-V */ |
1324 |
#define NV_PGRAPH_BOFFSET5 0x00400654 /* RW-4R */ |
1325 |
#define NV_PGRAPH_BOFFSET5__ALIAS_1 NV_PGRAPH_BOFFSET(5) /* */ |
1326 |
#define NV_PGRAPH_BOFFSET5_LINADRS 23:0 /* RWIUF */ |
1327 |
#define NV_PGRAPH_BOFFSET5_LINADRS_0 0x00000000 /* RWI-V */ |
1328 |
#define NV_PGRAPH_BBASE(i) (0x00400658+(i)*4) /* RW-4A */ |
1329 |
#define NV_PGRAPH_BBASE__SIZE_1 6 /* */ |
1330 |
#define NV_PGRAPH_BBASE_LINADRS 23:0 /* RWIUF */ |
1331 |
#define NV_PGRAPH_BBASE_LINADRS_0 0x00000000 /* RWI-V */ |
1332 |
#define NV_PGRAPH_BBASE0 0x00400658 /* RW-4R */ |
1333 |
#define NV_PGRAPH_BBASE0__ALIAS_1 NV_PGRAPH_BBASE(0) /* */ |
1334 |
#define NV_PGRAPH_BBASE0_LINADRS 23:0 /* RWIUF */ |
1335 |
#define NV_PGRAPH_BBASE0_LINADRS_0 0x00000000 /* RWI-V */ |
1336 |
#define NV_PGRAPH_BBASE1 0x0040065c /* RW-4R */ |
1337 |
#define NV_PGRAPH_BBASE1__ALIAS_1 NV_PGRAPH_BBASE(1) /* */ |
1338 |
#define NV_PGRAPH_BBASE1_LINADRS 23:0 /* RWIUF */ |
1339 |
#define NV_PGRAPH_BBASE1_LINADRS_0 0x00000000 /* RWI-V */ |
1340 |
#define NV_PGRAPH_BBASE2 0x00400660 /* RW-4R */ |
1341 |
#define NV_PGRAPH_BBASE2__ALIAS_1 NV_PGRAPH_BBASE(2) /* */ |
1342 |
#define NV_PGRAPH_BBASE2_LINADRS 23:0 /* RWIUF */ |
1343 |
#define NV_PGRAPH_BBASE2_LINADRS_0 0x00000000 /* RWI-V */ |
1344 |
#define NV_PGRAPH_BBASE3 0x00400664 /* RW-4R */ |
1345 |
#define NV_PGRAPH_BBASE3__ALIAS_1 NV_PGRAPH_BBASE(3) /* */ |
1346 |
#define NV_PGRAPH_BBASE3_LINADRS 23:0 /* RWIUF */ |
1347 |
#define NV_PGRAPH_BBASE3_LINADRS_0 0x00000000 /* RWI-V */ |
1348 |
#define NV_PGRAPH_BBASE4 0x00400668 /* RW-4R */ |
1349 |
#define NV_PGRAPH_BBASE4__ALIAS_1 NV_PGRAPH_BBASE(4) /* */ |
1350 |
#define NV_PGRAPH_BBASE4_LINADRS 23:0 /* RWIUF */ |
1351 |
#define NV_PGRAPH_BBASE4_LINADRS_0 0x00000000 /* RWI-V */ |
1352 |
#define NV_PGRAPH_BBASE5 0x0040066C /* RW-4R */ |
1353 |
#define NV_PGRAPH_BBASE5__ALIAS_1 NV_PGRAPH_BBASE(5) /* */ |
1354 |
#define NV_PGRAPH_BBASE5_LINADRS 23:0 /* RWIUF */ |
1355 |
#define NV_PGRAPH_BBASE5_LINADRS_0 0x00000000 /* RWI-V */ |
1356 |
#define NV_PGRAPH_BPITCH(i) (0x00400670+(i)*4) /* RW-4A */ |
1357 |
#define NV_PGRAPH_BPITCH__SIZE_1 5 /* */ |
1358 |
#define NV_PGRAPH_BPITCH_VALUE 12:0 /* RWIUF */ |
1359 |
#define NV_PGRAPH_BPITCH_VALUE_0 0x00000000 /* RWI-V */ |
1360 |
#define NV_PGRAPH_BPITCH0 0x00400670 /* RW-4R */ |
1361 |
#define NV_PGRAPH_BPITCH0__ALIAS_1 NV_PGRAPH_BPITCH(0) /* */ |
1362 |
#define NV_PGRAPH_BPITCH0_VALUE 12:0 /* RWIUF */ |
1363 |
#define NV_PGRAPH_BPITCH0_VALUE_0 0x00000000 /* RWI-V */ |
1364 |
#define NV_PGRAPH_BPITCH1 0x00400674 /* RW-4R */ |
1365 |
#define NV_PGRAPH_BPITCH1__ALIAS_1 NV_PGRAPH_BPITCH(1) /* */ |
1366 |
#define NV_PGRAPH_BPITCH1_VALUE 12:0 /* RWIUF */ |
1367 |
#define NV_PGRAPH_BPITCH1_VALUE_0 0x00000000 /* RWI-V */ |
1368 |
#define NV_PGRAPH_BPITCH2 0x00400678 /* RW-4R */ |
1369 |
#define NV_PGRAPH_BPITCH2__ALIAS_1 NV_PGRAPH_BPITCH(2) /* */ |
1370 |
#define NV_PGRAPH_BPITCH2_VALUE 12:0 /* RWIUF */ |
1371 |
#define NV_PGRAPH_BPITCH2_VALUE_0 0x00000000 /* RWI-V */ |
1372 |
#define NV_PGRAPH_BPITCH3 0x0040067C /* RW-4R */ |
1373 |
#define NV_PGRAPH_BPITCH3__ALIAS_1 NV_PGRAPH_BPITCH(3) /* */ |
1374 |
#define NV_PGRAPH_BPITCH3_VALUE 12:0 /* RWIUF */ |
1375 |
#define NV_PGRAPH_BPITCH3_VALUE_0 0x00000000 /* RWI-V */ |
1376 |
#define NV_PGRAPH_BPITCH4 0x00400680 /* RW-4R */ |
1377 |
#define NV_PGRAPH_BPITCH4__ALIAS_1 NV_PGRAPH_BPITCH(4) /* */ |
1378 |
#define NV_PGRAPH_BPITCH4_VALUE 12:0 /* RWIUF */ |
1379 |
#define NV_PGRAPH_BPITCH4_VALUE_0 0x00000000 /* RWI-V */ |
1380 |
#define NV_PGRAPH_BLIMIT(i) (0x00400684+(i)*4) /* RW-4A */ |
1381 |
#define NV_PGRAPH_BLIMIT__SIZE_1 6 /* */ |
1382 |
#define NV_PGRAPH_BLIMIT_VALUE 23:0 /* RWXUF */ |
1383 |
#define NV_PGRAPH_BLIMIT_TYPE 31:31 /* RWIVF */ |
1384 |
#define NV_PGRAPH_BLIMIT_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1385 |
#define NV_PGRAPH_BLIMIT_TYPE_NULL 0x00000001 /* RWI-V */ |
1386 |
#define NV_PGRAPH_BLIMIT0 0x00400684 /* RW-4R */ |
1387 |
#define NV_PGRAPH_BLIMIT0__ALIAS_1 NV_PGRAPH_BLIMIT(0) /* */ |
1388 |
#define NV_PGRAPH_BLIMIT0_VALUE 23:0 /* RWXUF */ |
1389 |
#define NV_PGRAPH_BLIMIT0_TYPE 31:31 /* RWIVF */ |
1390 |
#define NV_PGRAPH_BLIMIT0_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1391 |
#define NV_PGRAPH_BLIMIT0_TYPE_NULL 0x00000001 /* RWI-V */ |
1392 |
#define NV_PGRAPH_BLIMIT1 0x00400688 /* RW-4R */ |
1393 |
#define NV_PGRAPH_BLIMIT1__ALIAS_1 NV_PGRAPH_BLIMIT(1) /* */ |
1394 |
#define NV_PGRAPH_BLIMIT1_VALUE 23:0 /* RWXUF */ |
1395 |
#define NV_PGRAPH_BLIMIT1_TYPE 31:31 /* RWIVF */ |
1396 |
#define NV_PGRAPH_BLIMIT1_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1397 |
#define NV_PGRAPH_BLIMIT1_TYPE_NULL 0x00000001 /* RWI-V */ |
1398 |
#define NV_PGRAPH_BLIMIT2 0x0040068c /* RW-4R */ |
1399 |
#define NV_PGRAPH_BLIMIT2__ALIAS_1 NV_PGRAPH_BLIMIT(2) /* */ |
1400 |
#define NV_PGRAPH_BLIMIT2_VALUE 23:0 /* RWXUF */ |
1401 |
#define NV_PGRAPH_BLIMIT2_TYPE 31:31 /* RWIVF */ |
1402 |
#define NV_PGRAPH_BLIMIT2_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1403 |
#define NV_PGRAPH_BLIMIT2_TYPE_NULL 0x00000001 /* RWI-V */ |
1404 |
#define NV_PGRAPH_BLIMIT3 0x00400690 /* RW-4R */ |
1405 |
#define NV_PGRAPH_BLIMIT3__ALIAS_1 NV_PGRAPH_BLIMIT(3) /* */ |
1406 |
#define NV_PGRAPH_BLIMIT3_VALUE 23:0 /* RWXUF */ |
1407 |
#define NV_PGRAPH_BLIMIT3_TYPE 31:31 /* RWIVF */ |
1408 |
#define NV_PGRAPH_BLIMIT3_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1409 |
#define NV_PGRAPH_BLIMIT3_TYPE_NULL 0x00000001 /* RWI-V */ |
1410 |
#define NV_PGRAPH_BLIMIT4 0x00400694 /* RW-4R */ |
1411 |
#define NV_PGRAPH_BLIMIT4__ALIAS_1 NV_PGRAPH_BLIMIT(4) /* */ |
1412 |
#define NV_PGRAPH_BLIMIT4_VALUE 23:0 /* RWXUF */ |
1413 |
#define NV_PGRAPH_BLIMIT4_TYPE 31:31 /* RWIVF */ |
1414 |
#define NV_PGRAPH_BLIMIT4_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1415 |
#define NV_PGRAPH_BLIMIT4_TYPE_NULL 0x00000001 /* RWI-V */ |
1416 |
#define NV_PGRAPH_BLIMIT5 0x00400698 /* RW-4R */ |
1417 |
#define NV_PGRAPH_BLIMIT5__ALIAS_1 NV_PGRAPH_BLIMIT(5) /* */ |
1418 |
#define NV_PGRAPH_BLIMIT5_VALUE 23:0 /* RWXUF */ |
1419 |
#define NV_PGRAPH_BLIMIT5_TYPE 31:31 /* RWIVF */ |
1420 |
#define NV_PGRAPH_BLIMIT5_TYPE_IN_MEMORY 0x00000000 /* RW--V */ |
1421 |
#define NV_PGRAPH_BLIMIT5_TYPE_NULL 0x00000001 /* RWI-V */ |
1422 |
#define NV_PGRAPH_BSWIZZLE2 0x0040069c /* RW-4R */ |
1423 |
#define NV_PGRAPH_BSWIZZLE2_WIDTH 19:16 /* RWIUF */ |
1424 |
#define NV_PGRAPH_BSWIZZLE2_WIDTH_0 0x00000000 /* RWI-V */ |
1425 |
#define NV_PGRAPH_BSWIZZLE2_HEIGHT 27:24 /* RWIUF */ |
1426 |
#define NV_PGRAPH_BSWIZZLE2_HEIGHT_0 0x00000000 /* RWI-V */ |
1427 |
#define NV_PGRAPH_BSWIZZLE5 0x004006a0 /* RW-4R */ |
1428 |
#define NV_PGRAPH_BSWIZZLE5_WIDTH 19:16 /* RWIUF */ |
1429 |
#define NV_PGRAPH_BSWIZZLE5_WIDTH_0 0x00000000 /* RWI-V */ |
1430 |
#define NV_PGRAPH_BSWIZZLE5_HEIGHT 27:24 /* RWIUF */ |
1431 |
#define NV_PGRAPH_BSWIZZLE5_HEIGHT_0 0x00000000 /* RWI-V */ |
1432 |
#define NV_PGRAPH_BPIXEL 0x00400724 /* RW-4R */ |
1433 |
#define NV_PGRAPH_BPIXEL_DEPTH0 3:0 /* RWIVF */ |
1434 |
#define NV_PGRAPH_BPIXEL_DEPTH0_INVALID 0x00000000 /* RWI-V */ |
1435 |
#define NV_PGRAPH_BPIXEL_DEPTH0_Y8 0x00000001 /* RW--V */ |
1436 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1437 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1438 |
#define NV_PGRAPH_BPIXEL_DEPTH0_A1R5G5B5 0x00000004 /* RW--V */ |
1439 |
#define NV_PGRAPH_BPIXEL_DEPTH0_R5G6B5 0x00000005 /* RW--V */ |
1440 |
#define NV_PGRAPH_BPIXEL_DEPTH0_Y16 0x00000006 /* RW--V */ |
1441 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1442 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1443 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1444 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1445 |
#define NV_PGRAPH_BPIXEL_DEPTH0_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1446 |
#define NV_PGRAPH_BPIXEL_DEPTH0_A8R8G8B8 0x0000000c /* RW--V */ |
1447 |
#define NV_PGRAPH_BPIXEL_DEPTH0_Y32 0x0000000d /* RW--V */ |
1448 |
#define NV_PGRAPH_BPIXEL_DEPTH0_V8YB8U8YA8 0x0000000e /* RW--V */ |
1449 |
#define NV_PGRAPH_BPIXEL_DEPTH0_YB8V8YA8U8 0x0000000f /* RW--V */ |
1450 |
#define NV_PGRAPH_BPIXEL_DEPTH1 7:4 /* RWIVF */ |
1451 |
#define NV_PGRAPH_BPIXEL_DEPTH1_INVALID 0x00000000 /* RWI-V */ |
1452 |
#define NV_PGRAPH_BPIXEL_DEPTH1_Y8 0x00000001 /* RW--V */ |
1453 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1454 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1455 |
#define NV_PGRAPH_BPIXEL_DEPTH1_A1R5G5B5 0x00000004 /* RW--V */ |
1456 |
#define NV_PGRAPH_BPIXEL_DEPTH1_R5G6B5 0x00000005 /* RW--V */ |
1457 |
#define NV_PGRAPH_BPIXEL_DEPTH1_Y16 0x00000006 /* RW--V */ |
1458 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1459 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1460 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1461 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1462 |
#define NV_PGRAPH_BPIXEL_DEPTH1_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1463 |
#define NV_PGRAPH_BPIXEL_DEPTH1_A8R8G8B8 0x0000000c /* RW--V */ |
1464 |
#define NV_PGRAPH_BPIXEL_DEPTH1_Y32 0x0000000d /* RW--V */ |
1465 |
#define NV_PGRAPH_BPIXEL_DEPTH1_V8YB8U8YA8 0x0000000e /* RW--V */ |
1466 |
#define NV_PGRAPH_BPIXEL_DEPTH1_YB8V8YA8U8 0x0000000f /* RW--V */ |
1467 |
#define NV_PGRAPH_BPIXEL_DEPTH2 11:8 /* RWIVF */ |
1468 |
#define NV_PGRAPH_BPIXEL_DEPTH2_INVALID 0x00000000 /* RWI-V */ |
1469 |
#define NV_PGRAPH_BPIXEL_DEPTH2_Y8 0x00000001 /* RW--V */ |
1470 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1471 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1472 |
#define NV_PGRAPH_BPIXEL_DEPTH2_A1R5G5B5 0x00000004 /* RW--V */ |
1473 |
#define NV_PGRAPH_BPIXEL_DEPTH2_R5G6B5 0x00000005 /* RW--V */ |
1474 |
#define NV_PGRAPH_BPIXEL_DEPTH2_Y16 0x00000006 /* RW--V */ |
1475 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1476 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1477 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1478 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1479 |
#define NV_PGRAPH_BPIXEL_DEPTH2_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1480 |
#define NV_PGRAPH_BPIXEL_DEPTH2_A8R8G8B8 0x0000000c /* RW--V */ |
1481 |
#define NV_PGRAPH_BPIXEL_DEPTH2_Y32 0x0000000d /* RW--V */ |
1482 |
#define NV_PGRAPH_BPIXEL_DEPTH2_V8YB8U8YA8 0x0000000e /* RW--V */ |
1483 |
#define NV_PGRAPH_BPIXEL_DEPTH2_YB8V8YA8U8 0x0000000f /* RW--V */ |
1484 |
#define NV_PGRAPH_BPIXEL_DEPTH3 15:12 /* RWIVF */ |
1485 |
#define NV_PGRAPH_BPIXEL_DEPTH3_INVALID 0x00000000 /* RWI-V */ |
1486 |
#define NV_PGRAPH_BPIXEL_DEPTH3_Y8 0x00000001 /* RW--V */ |
1487 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1488 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1489 |
#define NV_PGRAPH_BPIXEL_DEPTH3_A1R5G5B5 0x00000004 /* RW--V */ |
1490 |
#define NV_PGRAPH_BPIXEL_DEPTH3_R5G6B5 0x00000005 /* RW--V */ |
1491 |
#define NV_PGRAPH_BPIXEL_DEPTH3_Y16 0x00000006 /* RW--V */ |
1492 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1493 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1494 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1495 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1496 |
#define NV_PGRAPH_BPIXEL_DEPTH3_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1497 |
#define NV_PGRAPH_BPIXEL_DEPTH3_A8R8G8B8 0x0000000c /* RW--V */ |
1498 |
#define NV_PGRAPH_BPIXEL_DEPTH3_Y32 0x0000000d /* RW--V */ |
1499 |
#define NV_PGRAPH_BPIXEL_DEPTH3_V8YB8U8YA8 0x0000000e /* RW--V */ |
1500 |
#define NV_PGRAPH_BPIXEL_DEPTH3_YB8V8YA8U8 0x0000000f /* RW--V */ |
1501 |
#define NV_PGRAPH_BPIXEL_DEPTH4 19:16 /* RWIVF */ |
1502 |
#define NV_PGRAPH_BPIXEL_DEPTH4_INVALID 0x00000000 /* RWI-V */ |
1503 |
#define NV_PGRAPH_BPIXEL_DEPTH4_Y8 0x00000001 /* RW--V */ |
1504 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1505 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1506 |
#define NV_PGRAPH_BPIXEL_DEPTH4_A1R5G5B5 0x00000004 /* RW--V */ |
1507 |
#define NV_PGRAPH_BPIXEL_DEPTH4_R5G6B5 0x00000005 /* RW--V */ |
1508 |
#define NV_PGRAPH_BPIXEL_DEPTH4_Y16 0x00000006 /* RW--V */ |
1509 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1510 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1511 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1512 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1513 |
#define NV_PGRAPH_BPIXEL_DEPTH4_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1514 |
#define NV_PGRAPH_BPIXEL_DEPTH4_A8R8G8B8 0x0000000c /* RW--V */ |
1515 |
#define NV_PGRAPH_BPIXEL_DEPTH4_Y32 0x0000000d /* RW--V */ |
1516 |
#define NV_PGRAPH_BPIXEL_DEPTH4_V8YB8U8YA8 0x0000000e /* RW--V */ |
1517 |
#define NV_PGRAPH_BPIXEL_DEPTH4_YB8V8YA8U8 0x0000000f /* RW--V */ |
1518 |
#define NV_PGRAPH_BPIXEL_DEPTH5 23:20 /* RWIVF */ |
1519 |
#define NV_PGRAPH_BPIXEL_DEPTH5_INVALID 0x00000000 /* RWI-V */ |
1520 |
#define NV_PGRAPH_BPIXEL_DEPTH5_Y8 0x00000001 /* RW--V */ |
1521 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1522 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1523 |
#define NV_PGRAPH_BPIXEL_DEPTH5_A1R5G5B5 0x00000004 /* RW--V */ |
1524 |
#define NV_PGRAPH_BPIXEL_DEPTH5_R5G6B5 0x00000005 /* RW--V */ |
1525 |
#define NV_PGRAPH_BPIXEL_DEPTH5_Y16 0x00000006 /* RW--V */ |
1526 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1527 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1528 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1529 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1530 |
#define NV_PGRAPH_BPIXEL_DEPTH5_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1531 |
#define NV_PGRAPH_BPIXEL_DEPTH5_A8R8G8B8 0x0000000c /* RW--V */ |
1532 |
#define NV_PGRAPH_BPIXEL_DEPTH5_Y32 0x0000000d /* RW--V */ |
1533 |
#define NV_PGRAPH_BPIXEL_DEPTH5_V8YB8U8YA8 0x0000000e /* RW--V */ |
1534 |
#define NV_PGRAPH_BPIXEL_DEPTH5_YB8V8YA8U8 0x0000000f /* RW--V */ |
1535 |
#define NV_PGRAPH_LIMIT_VIOL_PIX 0x00400610 /* RW-4R */ |
1536 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS 23:0 /* RWIVF */ |
1537 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_ADRS_0 0x00000000 /* RWI-V */ |
1538 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT 29:29 /* RWIVF */ |
1539 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_NO_VIOL 0x00000000 /* RWI-V */ |
1540 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_BLIT_VIOL 0x00000001 /* RW--V */ |
1541 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT 30:30 /* RWIVF */ |
1542 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ |
1543 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_LIMIT_VIOL 0x00000001 /* RW--V */ |
1544 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW 31:31 /* RWIVF */ |
1545 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ |
1546 |
#define NV_PGRAPH_LIMIT_VIOL_PIX_OVRFLW_VIOL 0x00000001 /* RW--V */ |
1547 |
#define NV_PGRAPH_LIMIT_VIOL_Z 0x00400614 /* RW-4R */ |
1548 |
#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS 23:0 /* RWIVF */ |
1549 |
#define NV_PGRAPH_LIMIT_VIOL_Z_ADRS_0 0x00000000 /* RWI-V */ |
1550 |
#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT 30:30 /* RWIVF */ |
1551 |
#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_NO_VIOL 0x00000000 /* RWI-V */ |
1552 |
#define NV_PGRAPH_LIMIT_VIOL_Z_LIMIT_VIOL 0x00000001 /* RW--V */ |
1553 |
#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW 31:31 /* RWIVF */ |
1554 |
#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_NO_VIOL 0x00000000 /* RWI-V */ |
1555 |
#define NV_PGRAPH_LIMIT_VIOL_Z_OVRFLW_VIOL 0x00000001 /* RW--V */ |
1556 |
#define NV_PGRAPH_STATE 0x00400710 /* RW-4R */ |
1557 |
#define NV_PGRAPH_STATE_BUFFER_0 0:0 /* RWIVF */ |
1558 |
#define NV_PGRAPH_STATE_BUFFER_0_INVALID 0x00000000 /* RWI-V */ |
1559 |
#define NV_PGRAPH_STATE_BUFFER_0_VALID 0x00000001 /* RW--V */ |
1560 |
#define NV_PGRAPH_STATE_BUFFER_1 1:1 /* RWIVF */ |
1561 |
#define NV_PGRAPH_STATE_BUFFER_1_INVALID 0x00000000 /* RWI-V */ |
1562 |
#define NV_PGRAPH_STATE_BUFFER_1_VALID 0x00000001 /* RW--V */ |
1563 |
#define NV_PGRAPH_STATE_BUFFER_2 2:2 /* RWIVF */ |
1564 |
#define NV_PGRAPH_STATE_BUFFER_2_INVALID 0x00000000 /* RWI-V */ |
1565 |
#define NV_PGRAPH_STATE_BUFFER_2_VALID 0x00000001 /* RW--V */ |
1566 |
#define NV_PGRAPH_STATE_BUFFER_3 3:3 /* RWIVF */ |
1567 |
#define NV_PGRAPH_STATE_BUFFER_3_INVALID 0x00000000 /* RWI-V */ |
1568 |
#define NV_PGRAPH_STATE_BUFFER_3_VALID 0x00000001 /* RW--V */ |
1569 |
#define NV_PGRAPH_STATE_BUFFER_4 4:4 /* RWIVF */ |
1570 |
#define NV_PGRAPH_STATE_BUFFER_4_INVALID 0x00000000 /* RWI-V */ |
1571 |
#define NV_PGRAPH_STATE_BUFFER_4_VALID 0x00000001 /* RW--V */ |
1572 |
#define NV_PGRAPH_STATE_BUFFER_5 5:5 /* RWIVF */ |
1573 |
#define NV_PGRAPH_STATE_BUFFER_5_INVALID 0x00000000 /* RWI-V */ |
1574 |
#define NV_PGRAPH_STATE_BUFFER_5_VALID 0x00000001 /* RW--V */ |
1575 |
#define NV_PGRAPH_STATE_PITCH_0 8:8 /* RWIVF */ |
1576 |
#define NV_PGRAPH_STATE_PITCH_0_INVALID 0x00000000 /* RWI-V */ |
1577 |
#define NV_PGRAPH_STATE_PITCH_0_VALID 0x00000001 /* RW--V */ |
1578 |
#define NV_PGRAPH_STATE_PITCH_1 9:9 /* RWIVF */ |
1579 |
#define NV_PGRAPH_STATE_PITCH_1_INVALID 0x00000000 /* RWI-V */ |
1580 |
#define NV_PGRAPH_STATE_PITCH_1_VALID 0x00000001 /* RW--V */ |
1581 |
#define NV_PGRAPH_STATE_PITCH_2 10:10 /* RWIVF */ |
1582 |
#define NV_PGRAPH_STATE_PITCH_2_INVALID 0x00000000 /* RWI-V */ |
1583 |
#define NV_PGRAPH_STATE_PITCH_2_VALID 0x00000001 /* RW--V */ |
1584 |
#define NV_PGRAPH_STATE_PITCH_3 11:11 /* RWIVF */ |
1585 |
#define NV_PGRAPH_STATE_PITCH_3_INVALID 0x00000000 /* RWI-V */ |
1586 |
#define NV_PGRAPH_STATE_PITCH_3_VALID 0x00000001 /* RW--V */ |
1587 |
#define NV_PGRAPH_STATE_PITCH_4 12:12 /* RWIVF */ |
1588 |
#define NV_PGRAPH_STATE_PITCH_4_INVALID 0x00000000 /* RWI-V */ |
1589 |
#define NV_PGRAPH_STATE_PITCH_4_VALID 0x00000001 /* RW--V */ |
1590 |
#define NV_PGRAPH_STATE_CHROMA_COLOR 16:16 /* RWIVF */ |
1591 |
#define NV_PGRAPH_STATE_CHROMA_COLOR_INVALID 0x00000000 /* RWI-V */ |
1592 |
#define NV_PGRAPH_STATE_CHROMA_COLOR_VALID 0x00000001 /* RW--V */ |
1593 |
#define NV_PGRAPH_STATE_CHROMA_COLORFMT 17:17 /* RWIVF */ |
1594 |
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_INVALID 0x00000000 /* RWI-V */ |
1595 |
#define NV_PGRAPH_STATE_CHROMA_COLORFMT_VALID 0x00000001 /* RW--V */ |
1596 |
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT 20:20 /* RWIVF */ |
1597 |
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_INVALID 0x00000000 /* RWI-V */ |
1598 |
#define NV_PGRAPH_STATE_CPATTERN_COLORFMT_VALID 0x00000001 /* RW--V */ |
1599 |
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT 21:21 /* RWIVF */ |
1600 |
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_INVALID 0x00000000 /* RWI-V */ |
1601 |
#define NV_PGRAPH_STATE_CPATTERN_MONOFMT_VALID 0x00000001 /* RW--V */ |
1602 |
#define NV_PGRAPH_STATE_CPATTERN_SELECT 22:22 /* RWIVF */ |
1603 |
#define NV_PGRAPH_STATE_CPATTERN_SELECT_INVALID 0x00000000 /* RWI-V */ |
1604 |
#define NV_PGRAPH_STATE_CPATTERN_SELECT_VALID 0x00000001 /* RW--V */ |
1605 |
#define NV_PGRAPH_STATE_PATTERN_COLOR0 24:24 /* RWIVF */ |
1606 |
#define NV_PGRAPH_STATE_PATTERN_COLOR0_INVALID 0x00000000 /* RWI-V */ |
1607 |
#define NV_PGRAPH_STATE_PATTERN_COLOR0_VALID 0x00000001 /* RW--V */ |
1608 |
#define NV_PGRAPH_STATE_PATTERN_COLOR1 25:25 /* RWIVF */ |
1609 |
#define NV_PGRAPH_STATE_PATTERN_COLOR1_INVALID 0x00000000 /* RWI-V */ |
1610 |
#define NV_PGRAPH_STATE_PATTERN_COLOR1_VALID 0x00000001 /* RW--V */ |
1611 |
#define NV_PGRAPH_STATE_PATTERN_PATT0 26:26 /* RWIVF */ |
1612 |
#define NV_PGRAPH_STATE_PATTERN_PATT0_INVALID 0x00000000 /* RWI-V */ |
1613 |
#define NV_PGRAPH_STATE_PATTERN_PATT0_VALID 0x00000001 /* RW--V */ |
1614 |
#define NV_PGRAPH_STATE_PATTERN_PATT1 27:27 /* RWIVF */ |
1615 |
#define NV_PGRAPH_STATE_PATTERN_PATT1_INVALID 0x00000000 /* RWI-V */ |
1616 |
#define NV_PGRAPH_STATE_PATTERN_PATT1_VALID 0x00000001 /* RW--V */ |
1617 |
#define NV_PGRAPH_CACHE_INDEX 0x00400728 /* RW-4R */ |
1618 |
#define NV_PGRAPH_CACHE_INDEX_BANK 2:2 /* RWXVF */ |
1619 |
#define NV_PGRAPH_CACHE_INDEX_BANK_10 0x00000000 /* RW--V */ |
1620 |
#define NV_PGRAPH_CACHE_INDEX_BANK_32 0x00000001 /* RW--V */ |
1621 |
#define NV_PGRAPH_CACHE_INDEX_ADRS 12:3 /* RWXVF */ |
1622 |
#define NV_PGRAPH_CACHE_INDEX_ADRS_0 0x00000000 /* RW--V */ |
1623 |
#define NV_PGRAPH_CACHE_INDEX_ADRS_1024 0x00000400 /* RW--V */ |
1624 |
#define NV_PGRAPH_CACHE_INDEX_OP 14:13 /* RWXVF */ |
1625 |
#define NV_PGRAPH_CACHE_INDEX_OP_WR_CACHE 0x00000000 /* RW--V */ |
1626 |
#define NV_PGRAPH_CACHE_INDEX_OP_RD_CACHE 0x00000001 /* RW--V */ |
1627 |
#define NV_PGRAPH_CACHE_INDEX_OP_RD_INDEX 0x00000002 /* RW--V */ |
1628 |
#define NV_PGRAPH_CACHE_RAM 0x0040072c /* RW-4R */ |
1629 |
#define NV_PGRAPH_CACHE_RAM_VALUE 31:0 /* RWXVF */ |
1630 |
#define NV_PGRAPH_DMA_PITCH 0x00400760 /* RW-4R */ |
1631 |
#define NV_PGRAPH_DMA_PITCH_S0 15:0 /* RWXSF */ |
1632 |
#define NV_PGRAPH_DMA_PITCH_S1 31:16 /* RWXSF */ |
1633 |
#define NV_PGRAPH_DVD_COLORFMT 0x00400764 /* RW-4R */ |
1634 |
#define NV_PGRAPH_DVD_COLORFMT_IMAGE 5:0 /* RWNVF */ |
1635 |
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_INVALID 0x00 /* RWN-V */ |
1636 |
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_V8YB8U8YA8 0x12 /* RW--V */ |
1637 |
#define NV_PGRAPH_DVD_COLORFMT_IMAGE_FORMAT_LE_YB8V8YA8U8 0x13 /* RW--V */ |
1638 |
#define NV_PGRAPH_DVD_COLORFMT_OVLY 9:8 /* RWNVF */ |
1639 |
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_INVALID 0x00 /* RWN-V */ |
1640 |
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A8Y8U8V8 0x01 /* RW--V */ |
1641 |
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_LE_A4V6YB6A4U6YA6 0x02 /* RW--V */ |
1642 |
#define NV_PGRAPH_DVD_COLORFMT_OVLY_FORMAT_TRANSPARENT 0x03 /* RW--V */ |
1643 |
#define NV_PGRAPH_SCALED_FORMAT 0x00400768 /* RW-4R */ |
1644 |
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN 17:16 /* RWIVF */ |
1645 |
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_INVALID 0x00000000 /* RWI-V */ |
1646 |
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CENTER 0x00000001 /* RW--V */ |
1647 |
#define NV_PGRAPH_SCALED_FORMAT_ORIGIN_CORNER 0x00000002 /* RW--V */ |
1648 |
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR 24:24 /* RWIVF */ |
1649 |
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_ZOH 0x00000000 /* RWI-V */ |
1650 |
#define NV_PGRAPH_SCALED_FORMAT_INTERPOLATOR_FOH 0x00000001 /* RW--V */ |
1651 |
#define NV_PGRAPH_PATT_COLOR0 0x00400800 /* RW-4R */ |
1652 |
#define NV_PGRAPH_PATT_COLOR0_VALUE 31:0 /* RWXUF */ |
1653 |
#define NV_PGRAPH_PATT_COLOR1 0x00400804 /* RW-4R */ |
1654 |
#define NV_PGRAPH_PATT_COLOR1_VALUE 31:0 /* RWXUF */ |
1655 |
#define NV_PGRAPH_PATT_COLORRAM(i) (0x00400900+(i)*4) /* R--4A */ |
1656 |
#define NV_PGRAPH_PATT_COLORRAM__SIZE_1 64 /* */ |
1657 |
#define NV_PGRAPH_PATT_COLORRAM_VALUE 23:0 /* R--UF */ |
1658 |
#define NV_PGRAPH_PATTERN(i) (0x00400808+(i)*4) /* RW-4A */ |
1659 |
#define NV_PGRAPH_PATTERN__SIZE_1 2 /* */ |
1660 |
#define NV_PGRAPH_PATTERN_BITMAP 31:0 /* RWXVF */ |
1661 |
#define NV_PGRAPH_PATTERN_SHAPE 0x00400810 /* RW-4R */ |
1662 |
#define NV_PGRAPH_PATTERN_SHAPE_VALUE 1:0 /* RWXVF */ |
1663 |
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_8X_8Y 0x00000000 /* RW--V */ |
1664 |
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_64X_1Y 0x00000001 /* RW--V */ |
1665 |
#define NV_PGRAPH_PATTERN_SHAPE_VALUE_1X_64Y 0x00000002 /* RW--V */ |
1666 |
#define NV_PGRAPH_PATTERN_SHAPE_SELECT 4:4 /* RWXVF */ |
1667 |
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_2COLOR 0x00000000 /* RW--V */ |
1668 |
#define NV_PGRAPH_PATTERN_SHAPE_SELECT_FULLCOLOR 0x00000001 /* RW--V */ |
1669 |
#define NV_PGRAPH_MONO_COLOR0 0x00400600 /* RW-4R */ |
1670 |
#define NV_PGRAPH_MONO_COLOR0_VALUE 31:0 /* RWXUF */ |
1671 |
#define NV_PGRAPH_ROP3 0x00400604 /* RW-4R */ |
1672 |
#define NV_PGRAPH_ROP3_VALUE 7:0 /* RWXVF */ |
1673 |
#define NV_PGRAPH_CHROMA 0x00400814 /* RW-4R */ |
1674 |
#define NV_PGRAPH_CHROMA_VALUE 31:0 /* RWXUF */ |
1675 |
#define NV_PGRAPH_BETA_AND 0x00400608 /* RW-4R */ |
1676 |
#define NV_PGRAPH_BETA_AND_VALUE_FRACTION 30:23 /* RWXUF */ |
1677 |
#define NV_PGRAPH_BETA_PREMULT 0x0040060c /* RW-4R */ |
1678 |
#define NV_PGRAPH_BETA_PREMULT_VALUE 31:0 /* RWXUF */ |
1679 |
#define NV_PGRAPH_CONTROL0 0x00400818 /* RW-4R */ |
1680 |
#define NV_PGRAPH_CONTROL1 0x0040081c /* RW-4R */ |
1681 |
#define NV_PGRAPH_CONTROL2 0x00400820 /* RW-4R */ |
1682 |
#define NV_PGRAPH_BLEND 0x00400824 /* RW-4R */ |
1683 |
#define NV_PGRAPH_DPRAM_INDEX 0x00400828 /* RW-4R */ |
1684 |
#define NV_PGRAPH_DPRAM_INDEX_ADRS 6:0 /* RWIVF */ |
1685 |
#define NV_PGRAPH_DPRAM_INDEX_ADRS_0 0x00000000 /* RWI-V */ |
1686 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT 10:8 /* RWIVF */ |
1687 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_0 0x00000000 /* RWI-V */ |
1688 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ADRS_1 0x00000001 /* RW--V */ |
1689 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_0 0x00000002 /* RW--V */ |
1690 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_DATA_1 0x00000003 /* RW--V */ |
1691 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_0 0x00000004 /* RW--V */ |
1692 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_WE_1 0x00000005 /* RW--V */ |
1693 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_0 0x00000006 /* RW--V */ |
1694 |
#define NV_PGRAPH_DPRAM_INDEX_SELECT_ALPHA_1 0x00000007 /* RW--V */ |
1695 |
#define NV_PGRAPH_DPRAM_DATA 0x0040082c /* RW-4R */ |
1696 |
#define NV_PGRAPH_DPRAM_DATA_VALUE 31:0 /* RWXVF */ |
1697 |
#define NV_PGRAPH_DPRAM_ADRS_0 0x0040082c /* RW-4R */ |
1698 |
#define NV_PGRAPH_DPRAM_ADRS_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1699 |
#define NV_PGRAPH_DPRAM_ADRS_0_VALUE 19:0 /* RWXVF */ |
1700 |
#define NV_PGRAPH_DPRAM_ADRS_1 0x0040082c /* RW-4R */ |
1701 |
#define NV_PGRAPH_DPRAM_ADRS_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1702 |
#define NV_PGRAPH_DPRAM_ADRS_1_VALUE 19:0 /* RWXVF */ |
1703 |
#define NV_PGRAPH_DPRAM_DATA_0 0x0040082c /* RW-4R */ |
1704 |
#define NV_PGRAPH_DPRAM_DATA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1705 |
#define NV_PGRAPH_DPRAM_DATA_0_VALUE 31:0 /* RWXVF */ |
1706 |
#define NV_PGRAPH_DPRAM_DATA_1 0x0040082c /* RW-4R */ |
1707 |
#define NV_PGRAPH_DPRAM_DATA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1708 |
#define NV_PGRAPH_DPRAM_DATA_1_VALUE 31:0 /* RWXVF */ |
1709 |
#define NV_PGRAPH_DPRAM_WE_0 0x0040082c /* RW-4R */ |
1710 |
#define NV_PGRAPH_DPRAM_WE_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1711 |
#define NV_PGRAPH_DPRAM_WE_0_VALUE 23:0 /* RWXVF */ |
1712 |
#define NV_PGRAPH_DPRAM_WE_1 0x0040082c /* RW-4R */ |
1713 |
#define NV_PGRAPH_DPRAM_WE_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1714 |
#define NV_PGRAPH_DPRAM_WE_1_VALUE 23:0 /* RWXVF */ |
1715 |
#define NV_PGRAPH_DPRAM_ALPHA_0 0x0040082c /* RW-4R */ |
1716 |
#define NV_PGRAPH_DPRAM_ALPHA_0__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1717 |
#define NV_PGRAPH_DPRAM_ALPHA_0_VALUE 31:0 /* RWXVF */ |
1718 |
#define NV_PGRAPH_DPRAM_ALPHA_1 0x0040082c /* RW-4R */ |
1719 |
#define NV_PGRAPH_DPRAM_ALPHA_1__ALIAS_1 NV_PGRAPH_DPRAM_DATA /* */ |
1720 |
#define NV_PGRAPH_DPRAM_ALPHA_1_VALUE 31:0 /* RWXVF */ |
1721 |
#define NV_PGRAPH_STORED_FMT 0x00400830 /* RW-4R */ |
1722 |
#define NV_PGRAPH_STORED_FMT_MONO0 5:0 /* RWXVF */ |
1723 |
#define NV_PGRAPH_STORED_FMT_PATT0 13:8 /* RWXVF */ |
1724 |
#define NV_PGRAPH_STORED_FMT_PATT1 21:16 /* RWXVF */ |
1725 |
#define NV_PGRAPH_STORED_FMT_CHROMA 29:24 /* RWXVF */ |
1726 |
#define NV_PGRAPH_FORMATS 0x00400618 /* RW-4R */ |
1727 |
#define NV_PGRAPH_FORMATS_ROP 2:0 /* R-XVF */ |
1728 |
#define NV_PGRAPH_FORMATS_ROP_Y8 0x00000000 /* -W--V */ |
1729 |
#define NV_PGRAPH_FORMATS_ROP_RGB15 0x00000001 /* -W--V */ |
1730 |
#define NV_PGRAPH_FORMATS_ROP_RGB16 0x00000002 /* -W--V */ |
1731 |
#define NV_PGRAPH_FORMATS_ROP_Y16 0x00000003 /* -W--V */ |
1732 |
#define NV_PGRAPH_FORMATS_ROP_INVALID 0x00000004 /* -W--V */ |
1733 |
#define NV_PGRAPH_FORMATS_ROP_RGB24 0x00000005 /* -W--V */ |
1734 |
#define NV_PGRAPH_FORMATS_ROP_RGB30 0x00000006 /* -W--V */ |
1735 |
#define NV_PGRAPH_FORMATS_ROP_Y32 0x00000007 /* -W--V */ |
1736 |
#define NV_PGRAPH_FORMATS_SRC 9:4 /* R-XVF */ |
1737 |
#define NV_PGRAPH_FORMATS_SRC_INVALID 0x00000000 /* RW--V */ |
1738 |
#define NV_PGRAPH_FORMATS_SRC_LE_Y8 0x00000001 /* RW--V */ |
1739 |
#define NV_PGRAPH_FORMATS_SRC_LE_X16A8Y8 0x00000002 /* RW--V */ |
1740 |
#define NV_PGRAPH_FORMATS_SRC_LE_X24Y8 0x00000003 /* RW--V */ |
1741 |
#define NV_PGRAPH_FORMATS_SRC_LE_A1R5G5B5 0x00000006 /* RW--V */ |
1742 |
#define NV_PGRAPH_FORMATS_SRC_LE_X1R5G5B5 0x00000007 /* RW--V */ |
1743 |
#define NV_PGRAPH_FORMATS_SRC_LE_X16A1R5G5B5 0x00000008 /* RW--V */ |
1744 |
#define NV_PGRAPH_FORMATS_SRC_LE_X17R5G5B5 0x00000009 /* RW--V */ |
1745 |
#define NV_PGRAPH_FORMATS_SRC_LE_R5G6B5 0x0000000A /* RW--V */ |
1746 |
#define NV_PGRAPH_FORMATS_SRC_LE_A16R5G6B5 0x0000000B /* RW--V */ |
1747 |
#define NV_PGRAPH_FORMATS_SRC_LE_X16R5G6B5 0x0000000C /* RW--V */ |
1748 |
#define NV_PGRAPH_FORMATS_SRC_LE_A8R8G8B8 0x0000000D /* RW--V */ |
1749 |
#define NV_PGRAPH_FORMATS_SRC_LE_X8R8G8B8 0x0000000E /* RW--V */ |
1750 |
#define NV_PGRAPH_FORMATS_SRC_LE_Y16 0x0000000F /* RW--V */ |
1751 |
#define NV_PGRAPH_FORMATS_SRC_LE_A16Y16 0x00000010 /* RW--V */ |
1752 |
#define NV_PGRAPH_FORMATS_SRC_LE_X16Y16 0x00000011 /* RW--V */ |
1753 |
#define NV_PGRAPH_FORMATS_SRC_LE_V8YB8U8YA8 0x00000012 /* RW--V */ |
1754 |
#define NV_PGRAPH_FORMATS_SRC_LE_YB8V8YA8U8 0x00000013 /* RW--V */ |
1755 |
#define NV_PGRAPH_FORMATS_SRC_LE_Y32 0x00000014 /* RW--V */ |
1756 |
#define NV_PGRAPH_FORMATS_FB 15:12 /* R-XVF */ |
1757 |
#define NV_PGRAPH_FORMATS_FB_INVALID 0x00000000 /* RWI-V */ |
1758 |
#define NV_PGRAPH_FORMATS_FB_Y8 0x00000001 /* RW--V */ |
1759 |
#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_Z1R5G5B5 0x00000002 /* RW--V */ |
1760 |
#define NV_PGRAPH_FORMATS_FB_X1R5G5B5_O1R5G5B5 0x00000003 /* RW--V */ |
1761 |
#define NV_PGRAPH_FORMATS_FB_A1R5G5B5 0x00000004 /* RW--V */ |
1762 |
#define NV_PGRAPH_FORMATS_FB_R5G6B5 0x00000005 /* RW--V */ |
1763 |
#define NV_PGRAPH_FORMATS_FB_Y16 0x00000006 /* RW--V */ |
1764 |
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_Z8R8G8B8 0x00000007 /* RW--V */ |
1765 |
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O1Z7R8G8B8 0x00000008 /* RW--V */ |
1766 |
#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_Z1A7R8G8B8 0x00000009 /* RW--V */ |
1767 |
#define NV_PGRAPH_FORMATS_FB_X1A7R8G8B8_O1A7R8G8B8 0x0000000a /* RW--V */ |
1768 |
#define NV_PGRAPH_FORMATS_FB_X8R8G8B8_O8R8G8B8 0x0000000b /* RW--V */ |
1769 |
#define NV_PGRAPH_FORMATS_FB_A8R8G8B8 0x0000000c /* RW--V */ |
1770 |
#define NV_PGRAPH_FORMATS_FB_Y32 0x0000000d /* RW--V */ |
1771 |
#define NV_PGRAPH_FORMATS_FB_V8YB8U8YA8 0x0000000e /* RW--V */ |
1772 |
#define NV_PGRAPH_FORMATS_FB_YB8V8YA8U8 0x0000000f /* RW--V */ |
1773 |
#define NV_PGRAPH_ABS_X_RAM(i) (0x00400400+(i)*4) /* RW-4A */ |
1774 |
#define NV_PGRAPH_ABS_X_RAM__SIZE_1 32 /* */ |
1775 |
#define NV_PGRAPH_ABS_X_RAM_VALUE 31:0 /* RWXUF */ |
1776 |
#define NV_PGRAPH_X_RAM_BPORT(i) (0x00400c00+(i)*4) /* R--4A */ |
1777 |
#define NV_PGRAPH_X_RAM_BPORT__SIZE_1 32 /* */ |
1778 |
#define NV_PGRAPH_X_RAM_BPORT_VALUE 31:0 /* R--UF */ |
1779 |
#define NV_PGRAPH_ABS_Y_RAM(i) (0x00400480+(i)*4) /* RW-4A */ |
1780 |
#define NV_PGRAPH_ABS_Y_RAM__SIZE_1 32 /* */ |
1781 |
#define NV_PGRAPH_ABS_Y_RAM_VALUE 31:0 /* RWXUF */ |
1782 |
#define NV_PGRAPH_Y_RAM_BPORT(i) (0x00400c80+(i)*4) /* R--4A */ |
1783 |
#define NV_PGRAPH_Y_RAM_BPORT__SIZE_1 32 /* */ |
1784 |
#define NV_PGRAPH_Y_RAM_BPORT_VALUE 31:0 /* R--UF */ |
1785 |
#define NV_PGRAPH_XY_LOGIC_MISC0 0x00400514 /* RW-4R */ |
1786 |
#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER 17:0 /* RWBUF */ |
1787 |
#define NV_PGRAPH_XY_LOGIC_MISC0_COUNTER_0 0x00000000 /* RWB-V */ |
1788 |
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION 20:20 /* RWVVF */ |
1789 |
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_NONZERO 0x00000000 /* RWV-V */ |
1790 |
#define NV_PGRAPH_XY_LOGIC_MISC0_DIMENSION_ZERO 0x00000001 /* RW--V */ |
1791 |
#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX 31:28 /* RWBUF */ |
1792 |
#define NV_PGRAPH_XY_LOGIC_MISC0_INDEX_0 0x00000000 /* RWB-V */ |
1793 |
#define NV_PGRAPH_XY_LOGIC_MISC1 0x00400518 /* RW-4R */ |
1794 |
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL 0:0 /* RWNVF */ |
1795 |
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_NEEDED 0x00000000 /* RWN-V */ |
1796 |
#define NV_PGRAPH_XY_LOGIC_MISC1_INITIAL_DONE 0x00000001 /* RW--V */ |
1797 |
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX 4:4 /* RWIVF */ |
1798 |
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ |
1799 |
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPX_NULL 0x00000001 /* RW--V */ |
1800 |
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY 5:5 /* RWIVF */ |
1801 |
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ |
1802 |
#define NV_PGRAPH_XY_LOGIC_MISC1_XTRACLIPY_NULL 0x00000001 /* RW--V */ |
1803 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX 12:12 /* RWIVF */ |
1804 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_UUMAX 0x00000000 /* RWI-V */ |
1805 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ |
1806 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX 16:16 /* RWIVF */ |
1807 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_UUMAX 0x00000000 /* RWI-V */ |
1808 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ |
1809 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA 20:20 /* RWIVF */ |
1810 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ |
1811 |
#define NV_PGRAPH_XY_LOGIC_MISC1_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ |
1812 |
#define NV_PGRAPH_XY_LOGIC_MISC2 0x0040051C /* RW-4R */ |
1813 |
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF 0:0 /* RWIVF */ |
1814 |
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_DISABLE 0x00000000 /* RWI-V */ |
1815 |
#define NV_PGRAPH_XY_LOGIC_MISC2_HANDOFF_ENABLE 0x00000001 /* RW--V */ |
1816 |
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX 4:4 /* RWIVF */ |
1817 |
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NOTNULL 0x00000000 /* RWI-V */ |
1818 |
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPX_NULL 0x00000001 /* RW--V */ |
1819 |
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY 5:5 /* RWIVF */ |
1820 |
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NOTNULL 0x00000000 /* RWI-V */ |
1821 |
#define NV_PGRAPH_XY_LOGIC_MISC2_XTRACLIPY_NULL 0x00000001 /* RW--V */ |
1822 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX 12:12 /* RWIVF */ |
1823 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_UCMAX 0x00000000 /* RWI-V */ |
1824 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XIMAX_IMAGEMAX 0x00000001 /* RW--V */ |
1825 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX 16:16 /* RWIVF */ |
1826 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_UCMAX 0x00000000 /* RWI-V */ |
1827 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_YIMAX_IMAGEMAX 0x00000001 /* RW--V */ |
1828 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA 20:20 /* RWIVF */ |
1829 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_CLIPMAX 0x00000000 /* RWI-V */ |
1830 |
#define NV_PGRAPH_XY_LOGIC_MISC2_SEL_XXTRA_IMAGEMAX 0x00000001 /* RW--V */ |
1831 |
#define NV_PGRAPH_XY_LOGIC_MISC3 0x00400520 /* RW-4R */ |
1832 |
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0 0:0 /* RWXVF */ |
1833 |
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_NULL 0x00000000 /* RW--V */ |
1834 |
#define NV_PGRAPH_XY_LOGIC_MISC3_WDIMY_EQ_0_TRUE 0x00000001 /* RW--V */ |
1835 |
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY 4:4 /* RWXVF */ |
1836 |
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_NULL 0x00000000 /* RW--V */ |
1837 |
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WDIMY_TRUE 0x00000001 /* RW--V */ |
1838 |
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX 8:8 /* RWIVF */ |
1839 |
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_NULL 0x00000000 /* RWI-V */ |
1840 |
#define NV_PGRAPH_XY_LOGIC_MISC3_RELOAD_WX_TRUE 0x00000001 /* RW--V */ |
1841 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG 12:12 /* RWIVF */ |
1842 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_NULL 0x00000000 /* RWI-V */ |
1843 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_ALG_TRUE 0x00000001 /* RW--V */ |
1844 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX 22:16 /* RWXUF */ |
1845 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_DIMX_0 0x00000000 /* RW--V */ |
1846 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX 30:24 /* RWXUF */ |
1847 |
#define NV_PGRAPH_XY_LOGIC_MISC3_TEXT_WDIMX_0 0x00000000 /* RW--V */ |
1848 |
#define NV_PGRAPH_X_MISC 0x00400500 /* RW-4R */ |
1849 |
#define NV_PGRAPH_X_MISC_BIT33_0 0:0 /* RWNVF */ |
1850 |
#define NV_PGRAPH_X_MISC_BIT33_0_0 0x00000000 /* RWN-V */ |
1851 |
#define NV_PGRAPH_X_MISC_BIT33_1 1:1 /* RWNVF */ |
1852 |
#define NV_PGRAPH_X_MISC_BIT33_1_0 0x00000000 /* RWN-V */ |
1853 |
#define NV_PGRAPH_X_MISC_BIT33_2 2:2 /* RWNVF */ |
1854 |
#define NV_PGRAPH_X_MISC_BIT33_2_0 0x00000000 /* RWN-V */ |
1855 |
#define NV_PGRAPH_X_MISC_BIT33_3 3:3 /* RWNVF */ |
1856 |
#define NV_PGRAPH_X_MISC_BIT33_3_0 0x00000000 /* RWN-V */ |
1857 |
#define NV_PGRAPH_X_MISC_RANGE_0 4:4 /* RWNVF */ |
1858 |
#define NV_PGRAPH_X_MISC_RANGE_0_0 0x00000000 /* RWN-V */ |
1859 |
#define NV_PGRAPH_X_MISC_RANGE_1 5:5 /* RWNVF */ |
1860 |
#define NV_PGRAPH_X_MISC_RANGE_1_0 0x00000000 /* RWN-V */ |
1861 |
#define NV_PGRAPH_X_MISC_RANGE_2 6:6 /* RWNVF */ |
1862 |
#define NV_PGRAPH_X_MISC_RANGE_2_0 0x00000000 /* RWN-V */ |
1863 |
#define NV_PGRAPH_X_MISC_RANGE_3 7:7 /* RWNVF */ |
1864 |
#define NV_PGRAPH_X_MISC_RANGE_3_0 0x00000000 /* RWN-V */ |
1865 |
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ |
1866 |
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ |
1867 |
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ |
1868 |
#define NV_PGRAPH_X_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ |
1869 |
#define NV_PGRAPH_Y_MISC 0x00400504 /* RW-4R */ |
1870 |
#define NV_PGRAPH_Y_MISC_BIT33_0 0:0 /* RWNVF */ |
1871 |
#define NV_PGRAPH_Y_MISC_BIT33_0_0 0x00000000 /* RWN-V */ |
1872 |
#define NV_PGRAPH_Y_MISC_BIT33_1 1:1 /* RWNVF */ |
1873 |
#define NV_PGRAPH_Y_MISC_BIT33_1_0 0x00000000 /* RWN-V */ |
1874 |
#define NV_PGRAPH_Y_MISC_BIT33_2 2:2 /* RWNVF */ |
1875 |
#define NV_PGRAPH_Y_MISC_BIT33_2_0 0x00000000 /* RWN-V */ |
1876 |
#define NV_PGRAPH_Y_MISC_BIT33_3 3:3 /* RWNVF */ |
1877 |
#define NV_PGRAPH_Y_MISC_BIT33_3_0 0x00000000 /* RWN-V */ |
1878 |
#define NV_PGRAPH_Y_MISC_RANGE_0 4:4 /* RWNVF */ |
1879 |
#define NV_PGRAPH_Y_MISC_RANGE_0_0 0x00000000 /* RWN-V */ |
1880 |
#define NV_PGRAPH_Y_MISC_RANGE_1 5:5 /* RWNVF */ |
1881 |
#define NV_PGRAPH_Y_MISC_RANGE_1_0 0x00000000 /* RWN-V */ |
1882 |
#define NV_PGRAPH_Y_MISC_RANGE_2 6:6 /* RWNVF */ |
1883 |
#define NV_PGRAPH_Y_MISC_RANGE_2_0 0x00000000 /* RWN-V */ |
1884 |
#define NV_PGRAPH_Y_MISC_RANGE_3 7:7 /* RWNVF */ |
1885 |
#define NV_PGRAPH_Y_MISC_RANGE_3_0 0x00000000 /* RWN-V */ |
1886 |
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT 29:28 /* RWXVF */ |
1887 |
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_EQ_0 0x00000000 /* RW--V */ |
1888 |
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_LT_0 0x00000001 /* RW--V */ |
1889 |
#define NV_PGRAPH_Y_MISC_ADDER_OUTPUT_GT_0 0x00000002 /* RW--V */ |
1890 |
#define NV_PGRAPH_ABS_UCLIP_XMIN 0x0040053C /* RW-4R */ |
1891 |
#define NV_PGRAPH_ABS_UCLIP_XMIN_VALUE 15:0 /* RWXSF */ |
1892 |
#define NV_PGRAPH_ABS_UCLIP_XMAX 0x00400544 /* RW-4R */ |
1893 |
#define NV_PGRAPH_ABS_UCLIP_XMAX_VALUE 17:0 /* RWXSF */ |
1894 |
#define NV_PGRAPH_ABS_UCLIP_YMIN 0x00400540 /* RW-4R */ |
1895 |
#define NV_PGRAPH_ABS_UCLIP_YMIN_VALUE 15:0 /* RWXSF */ |
1896 |
#define NV_PGRAPH_ABS_UCLIP_YMAX 0x00400548 /* RW-4R */ |
1897 |
#define NV_PGRAPH_ABS_UCLIP_YMAX_VALUE 17:0 /* RWXSF */ |
1898 |
#define NV_PGRAPH_ABS_UCLIPA_XMIN 0x00400560 /* RW-4R */ |
1899 |
#define NV_PGRAPH_ABS_UCLIPA_XMIN_VALUE 15:0 /* RWXSF */ |
1900 |
#define NV_PGRAPH_ABS_UCLIPA_XMAX 0x00400568 /* RW-4R */ |
1901 |
#define NV_PGRAPH_ABS_UCLIPA_XMAX_VALUE 17:0 /* RWXSF */ |
1902 |
#define NV_PGRAPH_ABS_UCLIPA_YMIN 0x00400564 /* RW-4R */ |
1903 |
#define NV_PGRAPH_ABS_UCLIPA_YMIN_VALUE 15:0 /* RWXSF */ |
1904 |
#define NV_PGRAPH_ABS_UCLIPA_YMAX 0x0040056C /* RW-4R */ |
1905 |
#define NV_PGRAPH_ABS_UCLIPA_YMAX_VALUE 17:0 /* RWXSF */ |
1906 |
#define NV_PGRAPH_SOURCE_COLOR 0x0040050C /* RW-4R */ |
1907 |
#define NV_PGRAPH_SOURCE_COLOR_VALUE 31:0 /* RWNVF */ |
1908 |
#define NV_PGRAPH_SOURCE_COLOR_VALUE_0 0x00000000 /* RWN-V */ |
1909 |
#define NV_PGRAPH_VALID1 0x00400508 /* RW-4R */ |
1910 |
#define NV_PGRAPH_VALID1_VLD 22:0 /* RWNVF */ |
1911 |
#define NV_PGRAPH_VALID1_VLD_0 0x00000000 /* RWN-V */ |
1912 |
#define NV_PGRAPH_VALID1_CLIP_MIN 28:28 /* RWIVF */ |
1913 |
#define NV_PGRAPH_VALID1_CLIP_MIN_NO_ERROR 0x00000000 /* RWI-V */ |
1914 |
#define NV_PGRAPH_VALID1_CLIP_MIN_ONLY 0x00000001 /* RW--V */ |
1915 |
#define NV_PGRAPH_VALID1_CLIPA_MIN 29:29 /* RWIVF */ |
1916 |
#define NV_PGRAPH_VALID1_CLIPA_MIN_NO_ERROR 0x00000000 /* RWI-V */ |
1917 |
#define NV_PGRAPH_VALID1_CLIPA_MIN_ONLY 0x00000001 /* RW--V */ |
1918 |
#define NV_PGRAPH_VALID1_CLIP_MAX 30:30 /* RWIVF */ |
1919 |
#define NV_PGRAPH_VALID1_CLIP_MAX_NO_ERROR 0x00000000 /* RWI-V */ |
1920 |
#define NV_PGRAPH_VALID1_CLIP_MAX_ONLY 0x00000001 /* RW--V */ |
1921 |
#define NV_PGRAPH_VALID1_CLIPA_MAX 31:31 /* RWIVF */ |
1922 |
#define NV_PGRAPH_VALID1_CLIPA_MAX_NO_ERROR 0x00000000 /* RWI-V */ |
1923 |
#define NV_PGRAPH_VALID1_CLIPA_MAX_ONLY 0x00000001 /* RW--V */ |
1924 |
#define NV_PGRAPH_VALID2 0x00400578 /* RW-4R */ |
1925 |
#define NV_PGRAPH_VALID2_VLD2 28:0 /* RWNVF */ |
1926 |
#define NV_PGRAPH_VALID2_VLD2_0 0x00000000 /* RWN-V */ |
1927 |
#define NV_PGRAPH_ABS_ICLIP_XMAX 0x00400534 /* RW-4R */ |
1928 |
#define NV_PGRAPH_ABS_ICLIP_XMAX_VALUE 17:0 /* RWXSF */ |
1929 |
#define NV_PGRAPH_ABS_ICLIP_YMAX 0x00400538 /* RW-4R */ |
1930 |
#define NV_PGRAPH_ABS_ICLIP_YMAX_VALUE 17:0 /* RWXSF */ |
1931 |
#define NV_PGRAPH_CLIPX_0 0x00400524 /* RW-4R */ |
1932 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN 1:0 /* RWNVF */ |
1933 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ |
1934 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ |
1935 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ |
1936 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX 3:2 /* RWNVF */ |
1937 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ |
1938 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ |
1939 |
#define NV_PGRAPH_CLIPX_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ |
1940 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN 5:4 /* RWNVF */ |
1941 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ |
1942 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ |
1943 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ |
1944 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX 7:6 /* RWNVF */ |
1945 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ |
1946 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ |
1947 |
#define NV_PGRAPH_CLIPX_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ |
1948 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN 9:8 /* RWNVF */ |
1949 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ |
1950 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ |
1951 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ |
1952 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX 11:10 /* RWNVF */ |
1953 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ |
1954 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ |
1955 |
#define NV_PGRAPH_CLIPX_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ |
1956 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN 13:12 /* RWNVF */ |
1957 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ |
1958 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ |
1959 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ |
1960 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX 15:14 /* RWNVF */ |
1961 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ |
1962 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ |
1963 |
#define NV_PGRAPH_CLIPX_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ |
1964 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN 17:16 /* RWNVF */ |
1965 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ |
1966 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ |
1967 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ |
1968 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX 19:18 /* RWNVF */ |
1969 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ |
1970 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ |
1971 |
#define NV_PGRAPH_CLIPX_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ |
1972 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN 21:20 /* RWNVF */ |
1973 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ |
1974 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ |
1975 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ |
1976 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX 23:22 /* RWNVF */ |
1977 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ |
1978 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ |
1979 |
#define NV_PGRAPH_CLIPX_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ |
1980 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN 25:24 /* RWNVF */ |
1981 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ |
1982 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ |
1983 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ |
1984 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX 27:26 /* RWNVF */ |
1985 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ |
1986 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ |
1987 |
#define NV_PGRAPH_CLIPX_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ |
1988 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN 29:28 /* RWNVF */ |
1989 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ |
1990 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ |
1991 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ |
1992 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX 31:30 /* RWNVF */ |
1993 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ |
1994 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ |
1995 |
#define NV_PGRAPH_CLIPX_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ |
1996 |
#define NV_PGRAPH_CLIPX_1 0x00400528 /* RW-4R */ |
1997 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN 1:0 /* RWNVF */ |
1998 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ |
1999 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ |
2000 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ |
2001 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX 3:2 /* RWNVF */ |
2002 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ |
2003 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ |
2004 |
#define NV_PGRAPH_CLIPX_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ |
2005 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN 5:4 /* RWNVF */ |
2006 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ |
2007 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ |
2008 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ |
2009 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX 7:6 /* RWNVF */ |
2010 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ |
2011 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ |
2012 |
#define NV_PGRAPH_CLIPX_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ |
2013 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN 9:8 /* RWNVF */ |
2014 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ |
2015 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ |
2016 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ |
2017 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX 11:10 /* RWNVF */ |
2018 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ |
2019 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ |
2020 |
#define NV_PGRAPH_CLIPX_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ |
2021 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN 13:12 /* RWNVF */ |
2022 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ |
2023 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ |
2024 |
#define NV_PGRAPH_CLIPX_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ |
2025 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX 15:14 /* RWNVF */ |
2026 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ |
2027 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ |
2028 |
#define NV_PGRAPH_CLIPX_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ |
2029 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN 17:16 /* RWNVF */ |
2030 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ |
2031 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ |
2032 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ |
2033 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX 19:18 /* RWNVF */ |
2034 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ |
2035 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ |
2036 |
#define NV_PGRAPH_CLIPX_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ |
2037 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN 21:20 /* RWNVF */ |
2038 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ |
2039 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ |
2040 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ |
2041 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX 23:22 /* RWNVF */ |
2042 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ |
2043 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ |
2044 |
#define NV_PGRAPH_CLIPX_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ |
2045 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN 25:24 /* RWNVF */ |
2046 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ |
2047 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ |
2048 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ |
2049 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX 27:26 /* RWNVF */ |
2050 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ |
2051 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ |
2052 |
#define NV_PGRAPH_CLIPX_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ |
2053 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN 29:28 /* RWNVF */ |
2054 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ |
2055 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ |
2056 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ |
2057 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX 31:30 /* RWNVF */ |
2058 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ |
2059 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ |
2060 |
#define NV_PGRAPH_CLIPX_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ |
2061 |
#define NV_PGRAPH_CLIPY_0 0x0040052c /* RW-4R */ |
2062 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN 1:0 /* RWNVF */ |
2063 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_GT 0x00000000 /* RW--V */ |
2064 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_LT 0x00000001 /* RWN-V */ |
2065 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MIN_EQ 0x00000002 /* RW--V */ |
2066 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX 3:2 /* RWNVF */ |
2067 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_LT 0x00000000 /* RW--V */ |
2068 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_GT 0x00000001 /* RWN-V */ |
2069 |
#define NV_PGRAPH_CLIPY_0_CLIP0_MAX_EQ 0x00000002 /* RW--V */ |
2070 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN 5:4 /* RWNVF */ |
2071 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_GT 0x00000000 /* RW--V */ |
2072 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_LT 0x00000001 /* RWN-V */ |
2073 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MIN_EQ 0x00000002 /* RW--V */ |
2074 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX 7:6 /* RWNVF */ |
2075 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_LT 0x00000000 /* RW--V */ |
2076 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_GT 0x00000001 /* RWN-V */ |
2077 |
#define NV_PGRAPH_CLIPY_0_CLIP1_MAX_EQ 0x00000002 /* RW--V */ |
2078 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN 9:8 /* RWNVF */ |
2079 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_GT 0x00000000 /* RW--V */ |
2080 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_LT 0x00000001 /* RWN-V */ |
2081 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MIN_EQ 0x00000002 /* RW--V */ |
2082 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX 11:10 /* RWNVF */ |
2083 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_LT 0x00000000 /* RW--V */ |
2084 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_GT 0x00000001 /* RWN-V */ |
2085 |
#define NV_PGRAPH_CLIPY_0_CLIP2_MAX_EQ 0x00000002 /* RW--V */ |
2086 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN 13:12 /* RWNVF */ |
2087 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_GT 0x00000000 /* RW--V */ |
2088 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_LT 0x00000001 /* RWN-V */ |
2089 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MIN_EQ 0x00000002 /* RW--V */ |
2090 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX 15:14 /* RWNVF */ |
2091 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_LT 0x00000000 /* RW--V */ |
2092 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_GT 0x00000001 /* RWN-V */ |
2093 |
#define NV_PGRAPH_CLIPY_0_CLIP3_MAX_EQ 0x00000002 /* RW--V */ |
2094 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN 17:16 /* RWNVF */ |
2095 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_GT 0x00000000 /* RW--V */ |
2096 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_LT 0x00000001 /* RWN-V */ |
2097 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MIN_EQ 0x00000002 /* RW--V */ |
2098 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX 19:18 /* RWNVF */ |
2099 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_LT 0x00000000 /* RW--V */ |
2100 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_GT 0x00000001 /* RWN-V */ |
2101 |
#define NV_PGRAPH_CLIPY_0_CLIP4_MAX_EQ 0x00000002 /* RW--V */ |
2102 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN 21:20 /* RWNVF */ |
2103 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_GT 0x00000000 /* RW--V */ |
2104 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_LT 0x00000001 /* RWN-V */ |
2105 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MIN_EQ 0x00000002 /* RW--V */ |
2106 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX 23:22 /* RWNVF */ |
2107 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_LT 0x00000000 /* RW--V */ |
2108 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_GT 0x00000001 /* RWN-V */ |
2109 |
#define NV_PGRAPH_CLIPY_0_CLIP5_MAX_EQ 0x00000002 /* RW--V */ |
2110 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN 25:24 /* RWNVF */ |
2111 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_GT 0x00000000 /* RW--V */ |
2112 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_LT 0x00000001 /* RWN-V */ |
2113 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MIN_EQ 0x00000002 /* RW--V */ |
2114 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX 27:26 /* RWNVF */ |
2115 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_LT 0x00000000 /* RW--V */ |
2116 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_GT 0x00000001 /* RWN-V */ |
2117 |
#define NV_PGRAPH_CLIPY_0_CLIP6_MAX_EQ 0x00000002 /* RW--V */ |
2118 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN 29:28 /* RWNVF */ |
2119 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_GT 0x00000000 /* RW--V */ |
2120 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_LT 0x00000001 /* RWN-V */ |
2121 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MIN_EQ 0x00000002 /* RW--V */ |
2122 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX 31:30 /* RWNVF */ |
2123 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_LT 0x00000000 /* RW--V */ |
2124 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_GT 0x00000001 /* RWN-V */ |
2125 |
#define NV_PGRAPH_CLIPY_0_CLIP7_MAX_EQ 0x00000002 /* RW--V */ |
2126 |
#define NV_PGRAPH_CLIPY_1 0x00400530 /* RW-4R */ |
2127 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN 1:0 /* RWNVF */ |
2128 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_GT 0x00000000 /* RW--V */ |
2129 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_LT 0x00000001 /* RWN-V */ |
2130 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MIN_EQ 0x00000002 /* RW--V */ |
2131 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX 3:2 /* RWNVF */ |
2132 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_LT 0x00000000 /* RW--V */ |
2133 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_GT 0x00000001 /* RWN-V */ |
2134 |
#define NV_PGRAPH_CLIPY_1_CLIP8_MAX_EQ 0x00000002 /* RW--V */ |
2135 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN 5:4 /* RWNVF */ |
2136 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_GT 0x00000000 /* RW--V */ |
2137 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_LT 0x00000001 /* RWN-V */ |
2138 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MIN_EQ 0x00000002 /* RW--V */ |
2139 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX 7:6 /* RWNVF */ |
2140 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_LT 0x00000000 /* RW--V */ |
2141 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_GT 0x00000001 /* RWN-V */ |
2142 |
#define NV_PGRAPH_CLIPY_1_CLIP9_MAX_EQ 0x00000002 /* RW--V */ |
2143 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN 9:8 /* RWNVF */ |
2144 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_GT 0x00000000 /* RW--V */ |
2145 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_LT 0x00000001 /* RWN-V */ |
2146 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MIN_EQ 0x00000002 /* RW--V */ |
2147 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX 11:10 /* RWNVF */ |
2148 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_LT 0x00000000 /* RW--V */ |
2149 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_GT 0x00000001 /* RWN-V */ |
2150 |
#define NV_PGRAPH_CLIPY_1_CLIP10_MAX_EQ 0x00000002 /* RW--V */ |
2151 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN 13:12 /* RWNVF */ |
2152 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_GT 0x00000000 /* RW--V */ |
2153 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MIN_LT 0x00000001 /* RWN-V */ |
2154 |
#define NV_PGRAPH_CLIPY_1_CLIP11MIN_EQ 0x00000002 /* RW--V */ |
2155 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX 15:14 /* RWNVF */ |
2156 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_LT 0x00000000 /* RW--V */ |
2157 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_GT 0x00000001 /* RWN-V */ |
2158 |
#define NV_PGRAPH_CLIPY_1_CLIP11_MAX_EQ 0x00000002 /* RW--V */ |
2159 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN 17:16 /* RWNVF */ |
2160 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_GT 0x00000000 /* RW--V */ |
2161 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_LT 0x00000001 /* RWN-V */ |
2162 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MIN_EQ 0x00000002 /* RW--V */ |
2163 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX 19:18 /* RWNVF */ |
2164 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_LT 0x00000000 /* RW--V */ |
2165 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_GT 0x00000001 /* RWN-V */ |
2166 |
#define NV_PGRAPH_CLIPY_1_CLIP12_MAX_EQ 0x00000002 /* RW--V */ |
2167 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN 21:20 /* RWNVF */ |
2168 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_GT 0x00000000 /* RW--V */ |
2169 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_LT 0x00000001 /* RWN-V */ |
2170 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MIN_EQ 0x00000002 /* RW--V */ |
2171 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX 23:22 /* RWNVF */ |
2172 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_LT 0x00000000 /* RW--V */ |
2173 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_GT 0x00000001 /* RWN-V */ |
2174 |
#define NV_PGRAPH_CLIPY_1_CLIP13_MAX_EQ 0x00000002 /* RW--V */ |
2175 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN 25:24 /* RWNVF */ |
2176 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_GT 0x00000000 /* RW--V */ |
2177 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_LT 0x00000001 /* RWN-V */ |
2178 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MIN_EQ 0x00000002 /* RW--V */ |
2179 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX 27:26 /* RWNVF */ |
2180 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_LT 0x00000000 /* RW--V */ |
2181 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_GT 0x00000001 /* RWN-V */ |
2182 |
#define NV_PGRAPH_CLIPY_1_CLIP14_MAX_EQ 0x00000002 /* RW--V */ |
2183 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN 29:28 /* RWNVF */ |
2184 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_GT 0x00000000 /* RW--V */ |
2185 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_LT 0x00000001 /* RWN-V */ |
2186 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MIN_EQ 0x00000002 /* RW--V */ |
2187 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX 31:30 /* RWNVF */ |
2188 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_LT 0x00000000 /* RW--V */ |
2189 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_GT 0x00000001 /* RWN-V */ |
2190 |
#define NV_PGRAPH_CLIPY_1_CLIP15_MAX_EQ 0x00000002 /* RW--V */ |
2191 |
#define NV_PGRAPH_MISC24_0 0x00400510 /* RW-4R */ |
2192 |
#define NV_PGRAPH_MISC24_0_VALUE 23:0 /* RWXUF */ |
2193 |
#define NV_PGRAPH_MISC24_1 0x00400570 /* RW-4R */ |
2194 |
#define NV_PGRAPH_MISC24_1_VALUE 23:0 /* RWXUF */ |
2195 |
#define NV_PGRAPH_MISC24_2 0x00400574 /* RW-4R */ |
2196 |
#define NV_PGRAPH_MISC24_2_VALUE 23:0 /* RWXUF */ |
2197 |
#define NV_PGRAPH_PASSTHRU_0 0x0040057C /* RW-4R */ |
2198 |
#define NV_PGRAPH_PASSTHRU_0_VALUE 31:0 /* RWXUF */ |
2199 |
#define NV_PGRAPH_PASSTHRU_1 0x00400580 /* RW-4R */ |
2200 |
#define NV_PGRAPH_PASSTHRU_1_VALUE 31:0 /* RWXUF */ |
2201 |
#define NV_PGRAPH_PASSTHRU_2 0x00400584 /* RW-4R */ |
2202 |
#define NV_PGRAPH_PASSTHRU_2_VALUE 31:0 /* RWXUF */ |
2203 |
#define NV_PGRAPH_U_RAM(i) (0x00400d00+(i)*4) /* RW-4A */ |
2204 |
#define NV_PGRAPH_U_RAM__SIZE_1 16 /* */ |
2205 |
#define NV_PGRAPH_U_RAM_VALUE 31:6 /* RWXFF */ |
2206 |
#define NV_PGRAPH_V_RAM(i) (0x00400d40+(i)*4) /* RW-4A */ |
2207 |
#define NV_PGRAPH_V_RAM__SIZE_1 16 /* */ |
2208 |
#define NV_PGRAPH_V_RAM_VALUE 31:6 /* RWXFF */ |
2209 |
#define NV_PGRAPH_M_RAM(i) (0x00400d80+(i)*4) /* RW-4A */ |
2210 |
#define NV_PGRAPH_M_RAM__SIZE_1 16 /* */ |
2211 |
#define NV_PGRAPH_M_RAM_VALUE 31:6 /* RWXFF */ |
2212 |
#define NV_PGRAPH_DMA_START_0 0x00401000 /* RW-4R */ |
2213 |
#define NV_PGRAPH_DMA_START_0_VALUE 31:0 /* RWXUF */ |
2214 |
#define NV_PGRAPH_DMA_START_1 0x00401004 /* RW-4R */ |
2215 |
#define NV_PGRAPH_DMA_START_1_VALUE 31:0 /* RWXUF */ |
2216 |
#define NV_PGRAPH_DMA_LENGTH 0x00401008 /* RW-4R */ |
2217 |
#define NV_PGRAPH_DMA_LENGTH_VALUE 21:0 /* RWXUF */ |
2218 |
#define NV_PGRAPH_DMA_MISC 0x0040100C /* RW-4R */ |
2219 |
#define NV_PGRAPH_DMA_MISC_COUNT 15:0 /* RWXUF */ |
2220 |
#define NV_PGRAPH_DMA_MISC_FMT_SRC 18:16 /* RWXVF */ |
2221 |
#define NV_PGRAPH_DMA_MISC_FMT_DST 22:20 /* RWXVF */ |
2222 |
#define NV_PGRAPH_DMA_DATA_0 0x00401020 /* RW-4R */ |
2223 |
#define NV_PGRAPH_DMA_DATA_0_VALUE 31:0 /* RWXUF */ |
2224 |
#define NV_PGRAPH_DMA_DATA_1 0x00401024 /* RW-4R */ |
2225 |
#define NV_PGRAPH_DMA_DATA_1_VALUE 31:0 /* RWXUF */ |
2226 |
#define NV_PGRAPH_DMA_RM 0x00401030 /* RW-4R */ |
2227 |
#define NV_PGRAPH_DMA_RM_ASSIST_A 0:0 /* RWIVF */ |
2228 |
#define NV_PGRAPH_DMA_RM_ASSIST_A_NOT_PENDING 0x00000000 /* R-I-V */ |
2229 |
#define NV_PGRAPH_DMA_RM_ASSIST_A_PENDING 0x00000001 /* R---V */ |
2230 |
#define NV_PGRAPH_DMA_RM_ASSIST_A_RESET 0x00000001 /* -W--C */ |
2231 |
#define NV_PGRAPH_DMA_RM_ASSIST_B 1:1 /* RWIVF */ |
2232 |
#define NV_PGRAPH_DMA_RM_ASSIST_B_NOT_PENDING 0x00000000 /* R-I-V */ |
2233 |
#define NV_PGRAPH_DMA_RM_ASSIST_B_PENDING 0x00000001 /* R---V */ |
2234 |
#define NV_PGRAPH_DMA_RM_ASSIST_B_RESET 0x00000001 /* -W--C */ |
2235 |
#define NV_PGRAPH_DMA_RM_WRITE_REQ 4:4 /* CWIVF */ |
2236 |
#define NV_PGRAPH_DMA_RM_WRITE_REQ_NOT_PENDING 0x00000000 /* CWI-V */ |
2237 |
#define NV_PGRAPH_DMA_RM_WRITE_REQ_PENDING 0x00000001 /* -W--T */ |
2238 |
#define NV_PGRAPH_DMA_A_XLATE_INST 0x00401040 /* RW-4R */ |
2239 |
#define NV_PGRAPH_DMA_A_XLATE_INST_VALUE 15:0 /* RWXUF */ |
2240 |
#define NV_PGRAPH_DMA_A_CONTROL 0x00401044 /* RW-4R */ |
2241 |
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ |
2242 |
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ |
2243 |
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ |
2244 |
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ |
2245 |
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ |
2246 |
#define NV_PGRAPH_DMA_A_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ |
2247 |
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE 17:16 /* RWXUF */ |
2248 |
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ |
2249 |
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ |
2250 |
#define NV_PGRAPH_DMA_A_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ |
2251 |
#define NV_PGRAPH_DMA_A_CONTROL_ADJUST 31:20 /* RWXUF */ |
2252 |
#define NV_PGRAPH_DMA_A_LIMIT 0x00401048 /* RW-4R */ |
2253 |
#define NV_PGRAPH_DMA_A_LIMIT_OFFSET 31:0 /* RWXUF */ |
2254 |
#define NV_PGRAPH_DMA_A_TLB_PTE 0x0040104C /* RW-4R */ |
2255 |
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS 1:1 /* RWXVF */ |
2256 |
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ |
2257 |
#define NV_PGRAPH_DMA_A_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ |
2258 |
#define NV_PGRAPH_DMA_A_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ |
2259 |
#define NV_PGRAPH_DMA_A_TLB_TAG 0x00401050 /* RW-4R */ |
2260 |
#define NV_PGRAPH_DMA_A_TLB_TAG_ADDRESS 31:12 /* RWXUF */ |
2261 |
#define NV_PGRAPH_DMA_A_ADJ_OFFSET 0x00401054 /* RW-4R */ |
2262 |
#define NV_PGRAPH_DMA_A_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ |
2263 |
#define NV_PGRAPH_DMA_A_OFFSET 0x00401058 /* RW-4R */ |
2264 |
#define NV_PGRAPH_DMA_A_OFFSET_VALUE 31:0 /* RWXUF */ |
2265 |
#define NV_PGRAPH_DMA_A_SIZE 0x0040105C /* RW-4R */ |
2266 |
#define NV_PGRAPH_DMA_A_SIZE_VALUE 24:0 /* RWXUF */ |
2267 |
#define NV_PGRAPH_DMA_A_Y_SIZE 0x00401060 /* RW-4R */ |
2268 |
#define NV_PGRAPH_DMA_A_Y_SIZE_VALUE 10:0 /* RWXUF */ |
2269 |
#define NV_PGRAPH_DMA_B_XLATE_INST 0x00401080 /* RW-4R */ |
2270 |
#define NV_PGRAPH_DMA_B_XLATE_INST_VALUE 15:0 /* RWXUF */ |
2271 |
#define NV_PGRAPH_DMA_B_CONTROL 0x00401084 /* RW-4R */ |
2272 |
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE 12:12 /* RWIVF */ |
2273 |
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_NOT_PRESENT 0x00000000 /* RWI-V */ |
2274 |
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_TABLE_PRESENT 0x00000001 /* RW--V */ |
2275 |
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY 13:13 /* RWXVF */ |
2276 |
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_NOT_LINEAR 0x00000000 /* RW--V */ |
2277 |
#define NV_PGRAPH_DMA_B_CONTROL_PAGE_ENTRY_LINEAR 0x00000001 /* RW--V */ |
2278 |
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE 17:16 /* RWXUF */ |
2279 |
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_NVM 0x00000000 /* RW--V */ |
2280 |
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_PCI 0x00000002 /* RW--V */ |
2281 |
#define NV_PGRAPH_DMA_B_CONTROL_TARGET_NODE_AGP 0x00000003 /* RW--V */ |
2282 |
#define NV_PGRAPH_DMA_B_CONTROL_ADJUST 31:20 /* RWXUF */ |
2283 |
#define NV_PGRAPH_DMA_B_LIMIT 0x00401088 /* RW-4R */ |
2284 |
#define NV_PGRAPH_DMA_B_LIMIT_OFFSET 31:0 /* RWXUF */ |
2285 |
#define NV_PGRAPH_DMA_B_TLB_PTE 0x0040108C /* RW-4R */ |
2286 |
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS 1:1 /* RWXVF */ |
2287 |
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_ONLY 0x00000000 /* RW--V */ |
2288 |
#define NV_PGRAPH_DMA_B_TLB_PTE_ACCESS_READ_WRITE 0x00000001 /* RW--V */ |
2289 |
#define NV_PGRAPH_DMA_B_TLB_PTE_FRAME_ADDRESS 31:12 /* RWXUF */ |
2290 |
#define NV_PGRAPH_DMA_B_TLB_TAG 0x00401090 /* RW-4R */ |
2291 |
#define NV_PGRAPH_DMA_B_TLB_TAG_ADDRESS 31:12 /* RWXUF */ |
2292 |
#define NV_PGRAPH_DMA_B_ADJ_OFFSET 0x00401094 /* RW-4R */ |
2293 |
#define NV_PGRAPH_DMA_B_ADJ_OFFSET_VALUE 31:0 /* RWXUF */ |
2294 |
#define NV_PGRAPH_DMA_B_OFFSET 0x00401098 /* RW-4R */ |
2295 |
#define NV_PGRAPH_DMA_B_OFFSET_VALUE 31:0 /* RWXUF */ |
2296 |
#define NV_PGRAPH_DMA_B_SIZE 0x0040109C /* RW-4R */ |
2297 |
#define NV_PGRAPH_DMA_B_SIZE_VALUE 24:0 /* RWXUF */ |
2298 |
#define NV_PGRAPH_DMA_B_Y_SIZE 0x004010A0 /* RW-4R */ |
2299 |
#define NV_PGRAPH_DMA_B_Y_SIZE_VALUE 10:0 /* RWXUF */ |
2300 |
|
2301 |
/* Framebuffer registers */ |
2302 |
#define NV_PFB 0x00100FFF:0x00100000 /* RW--D */ |
2303 |
#define NV_PFB_BOOT_0 0x00100000 /* RW-4R */ |
2304 |
#define NV_PFB_BOOT_0_RAM_AMOUNT 1:0 /* RW-VF */ |
2305 |
#define NV_PFB_BOOT_0_RAM_AMOUNT_32MB 0x00000000 /* RW--V */ |
2306 |
#define NV_PFB_BOOT_0_RAM_AMOUNT_4MB 0x00000001 /* RW--V */ |
2307 |
#define NV_PFB_BOOT_0_RAM_AMOUNT_8MB 0x00000002 /* RW--V */ |
2308 |
#define NV_PFB_BOOT_0_RAM_AMOUNT_16MB 0x00000003 /* RW--V */ |
2309 |
#define NV_PFB_BOOT_0_RAM_WIDTH_128 2:2 /* RW-VF */ |
2310 |
#define NV_PFB_BOOT_0_RAM_WIDTH_128_OFF 0x00000000 /* RW--V */ |
2311 |
#define NV_PFB_BOOT_0_RAM_WIDTH_128_ON 0x00000001 /* RW--V */ |
2312 |
#define NV_PFB_BOOT_0_RAM_TYPE 4:3 /* RW-VF */ |
2313 |
#define NV_PFB_BOOT_0_RAM_TYPE_256K 0x00000000 /* RW--V */ |
2314 |
#define NV_PFB_BOOT_0_RAM_TYPE_512K_2BANK 0x00000001 /* RW--V */ |
2315 |
#define NV_PFB_BOOT_0_RAM_TYPE_512K_4BANK 0x00000002 /* RW--V */ |
2316 |
#define NV_PFB_BOOT_0_RAM_TYPE_1024K_2BANK 0x00000003 /* RW--V */ |
2317 |
#define NV_PFB_CONFIG_0 0x00100200 /* RW-4R */ |
2318 |
#define NV_PFB_CONFIG_0_TYPE 14:0 /* RWIVF */ |
2319 |
#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_8BPP 0x00000120 /* RW--V */ |
2320 |
#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_16BPP 0x00000220 /* RW--V */ |
2321 |
#define NV_PFB_CONFIG_0_TYPE_OLD1024_FIXED_32BPP 0x00000320 /* RW--V */ |
2322 |
#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_8BPP 0x00004120 /* RW--V */ |
2323 |
#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_16BPP 0x00004220 /* RW--V */ |
2324 |
#define NV_PFB_CONFIG_0_TYPE_OLD1024_VAR_32BPP 0x00004320 /* RW--V */ |
2325 |
#define NV_PFB_CONFIG_0_TYPE_TETRIS 0x00002000 /* RW--V */ |
2326 |
#define NV_PFB_CONFIG_0_TYPE_NOTILING 0x00001114 /* RWI-V */ |
2327 |
#define NV_PFB_CONFIG_0_TETRIS_MODE 17:15 /* RWI-F */ |
2328 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_PASS 0x00000000 /* RWI-V */ |
2329 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_1 0x00000001 /* RW--V */ |
2330 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_2 0x00000002 /* RW--V */ |
2331 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_3 0x00000003 /* RW--V */ |
2332 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_4 0x00000004 /* RW--V */ |
2333 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_5 0x00000005 /* RW--V */ |
2334 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_6 0x00000006 /* RW--V */ |
2335 |
#define NV_PFB_CONFIG_0_TETRIS_MODE_7 0x00000007 /* RW--V */ |
2336 |
#define NV_PFB_CONFIG_0_TETRIS_SHIFT 19:18 /* RWI-F */ |
2337 |
#define NV_PFB_CONFIG_0_TETRIS_SHIFT_0 0x00000000 /* RWI-V */ |
2338 |
#define NV_PFB_CONFIG_0_TETRIS_SHIFT_1 0x00000001 /* RW--V */ |
2339 |
#define NV_PFB_CONFIG_0_TETRIS_SHIFT_2 0x00000002 /* RW--V */ |
2340 |
#define NV_PFB_CONFIG_0_BANK_SWAP 22:20 /* RWI-F */ |
2341 |
#define NV_PFB_CONFIG_0_BANK_SWAP_OFF 0x00000000 /* RWI-V */ |
2342 |
#define NV_PFB_CONFIG_0_BANK_SWAP_1M 0x00000001 /* RW--V */ |
2343 |
#define NV_PFB_CONFIG_0_BANK_SWAP_2M 0x00000005 /* RW--V */ |
2344 |
#define NV_PFB_CONFIG_0_BANK_SWAP_4M 0x00000007 /* RW--V */ |
2345 |
#define NV_PFB_CONFIG_0_UNUSED 23:23 /* RW-VF */ |
2346 |
#define NV_PFB_CONFIG_0_SCRAMBLE_EN 29:29 /* RWIVF */ |
2347 |
#define NV_PFB_CONFIG_0_SCRAMBLE_EN_INIT 0x00000000 /* RW--V */ |
2348 |
#define NV_PFB_CONFIG_0_SCRAMBLE_ACTIVE 0x00000001 /* RW--V */ |
2349 |
#define NV_PFB_CONFIG_0_PRAMIN_WR 28:28 /* RWIVF */ |
2350 |
#define NV_PFB_CONFIG_0_PRAMIN_WR_INIT 0x00000000 /* RW--V */ |
2351 |
#define NV_PFB_CONFIG_0_PRAMIN_WR_DISABLED 0x00000001 /* RW--V */ |
2352 |
#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK 27:24 /* RWIVF */ |
2353 |
#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_INIT 0x00000000 /* RWI-V */ |
2354 |
#define NV_PFB_CONFIG_0_PRAMIN_WR_MASK_CLEAR 0x0000000f /* RWI-V */ |
2355 |
#define NV_PFB_CONFIG_1 0x00100204 /* RW-4R */ |
2356 |
#define NV_PFB_RTL 0x00100300 /* RW-4R */ |
2357 |
#define NV_PFB_RTL_H 0:0 /* RWIUF */ |
2358 |
#define NV_PFB_RTL_H_DEFAULT 0x00000000 /* RWI-V */ |
2359 |
#define NV_PFB_RTL_MC 1:1 /* RWIUF */ |
2360 |
#define NV_PFB_RTL_MC_DEFAULT 0x00000000 /* RWI-V */ |
2361 |
#define NV_PFB_RTL_V 2:2 /* RWIUF */ |
2362 |
#define NV_PFB_RTL_V_DEFAULT 0x00000000 /* RWI-V */ |
2363 |
#define NV_PFB_RTL_G 3:3 /* RWIUF */ |
2364 |
#define NV_PFB_RTL_G_DEFAULT 0x00000000 /* RWI-V */ |
2365 |
#define NV_PFB_RTL_GB 4:4 /* RWIUF */ |
2366 |
#define NV_PFB_RTL_GB_DEFAULT 0x00000000 /* RWI-V */ |
2367 |
#define NV_PFB_CONFIG_0_RESOLUTION 5:0 /* RWIVF */ |
2368 |
#define NV_PFB_CONFIG_0_RESOLUTION_320_PIXELS 0x0000000a /* RW--V */ |
2369 |
#define NV_PFB_CONFIG_0_RESOLUTION_400_PIXELS 0x0000000d /* RW--V */ |
2370 |
#define NV_PFB_CONFIG_0_RESOLUTION_480_PIXELS 0x0000000f /* RW--V */ |
2371 |
#define NV_PFB_CONFIG_0_RESOLUTION_512_PIXELS 0x00000010 /* RW--V */ |
2372 |
#define NV_PFB_CONFIG_0_RESOLUTION_640_PIXELS 0x00000014 /* RW--V */ |
2373 |
#define NV_PFB_CONFIG_0_RESOLUTION_800_PIXELS 0x00000019 /* RW--V */ |
2374 |
#define NV_PFB_CONFIG_0_RESOLUTION_960_PIXELS 0x0000001e /* RW--V */ |
2375 |
#define NV_PFB_CONFIG_0_RESOLUTION_1024_PIXELS 0x00000020 /* RW--V */ |
2376 |
#define NV_PFB_CONFIG_0_RESOLUTION_1152_PIXELS 0x00000024 /* RW--V */ |
2377 |
#define NV_PFB_CONFIG_0_RESOLUTION_1280_PIXELS 0x00000028 /* RW--V */ |
2378 |
#define NV_PFB_CONFIG_0_RESOLUTION_1600_PIXELS 0x00000032 /* RW--V */ |
2379 |
#define NV_PFB_CONFIG_0_RESOLUTION_DEFAULT 0x00000014 /* RWI-V */ |
2380 |
#define NV_PFB_CONFIG_0_PIXEL_DEPTH 9:8 /* RWIVF */ |
2381 |
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_8_BITS 0x00000001 /* RW--V */ |
2382 |
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_16_BITS 0x00000002 /* RW--V */ |
2383 |
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_32_BITS 0x00000003 /* RW--V */ |
2384 |
#define NV_PFB_CONFIG_0_PIXEL_DEPTH_DEFAULT 0x00000001 /* RWI-V */ |
2385 |
#define NV_PFB_CONFIG_0_TILING 12:12 /* RWIVF */ |
2386 |
#define NV_PFB_CONFIG_0_TILING_ENABLED 0x00000000 /* RW--V */ |
2387 |
#define NV_PFB_CONFIG_0_TILING_DISABLED 0x00000001 /* RWI-V */ |
2388 |
#define NV_PFB_CONFIG_1_SGRAM100 3:3 /* RWIVF */ |
2389 |
#define NV_PFB_CONFIG_1_SGRAM100_ENABLED 0x00000000 /* RWI-V */ |
2390 |
#define NV_PFB_CONFIG_1_SGRAM100_DISABLED 0x00000001 /* RW--V */ |
2391 |
#define NV_PFB_DEBUG_0_CKE_ALWAYSON 29:29 /* RWIVF */ |
2392 |
#define NV_PFB_DEBUG_0_CKE_ALWAYSON_OFF 0x00000000 /* RW--V */ |
2393 |
#define NV_PFB_DEBUG_0_CKE_ALWAYSON_ON 0x00000001 /* RWI-V */ |
2394 |
|
2395 |
#define NV_PEXTDEV 0x00101FFF:0x00101000 /* RW--D */ |
2396 |
#define NV_PEXTDEV_BOOT_0 0x00101000 /* R--4R */ |
2397 |
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED 0:0 /* R-XVF */ |
2398 |
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_33MHZ 0x00000000 /* R---V */ |
2399 |
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_SPEED_66MHZ 0x00000001 /* R---V */ |
2400 |
#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR 1:1 /* R-XVF */ |
2401 |
#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_NO_BIOS 0x00000000 /* R---V */ |
2402 |
#define NV_PEXTDEV_BOOT_0_STRAP_SUB_VENDOR_BIOS 0x00000001 /* R---V */ |
2403 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE 3:2 /* R-XVF */ |
2404 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_256K 0x00000000 /* R---V */ |
2405 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_2BANK 0x00000001 /* R---V */ |
2406 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_SGRAM_512K_4BANK 0x00000002 /* R---V */ |
2407 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_TYPE_1024K_2BANK 0x00000003 /* R---V */ |
2408 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH 4:4 /* R-XVF */ |
2409 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_64 0x00000000 /* R---V */ |
2410 |
#define NV_PEXTDEV_BOOT_0_STRAP_RAM_WIDTH_128 0x00000001 /* R---V */ |
2411 |
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE 5:5 /* R-XVF */ |
2412 |
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_PCI 0x00000000 /* R---V */ |
2413 |
#define NV_PEXTDEV_BOOT_0_STRAP_BUS_TYPE_AGP 0x00000001 /* R---V */ |
2414 |
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL 6:6 /* R-XVF */ |
2415 |
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_13500K 0x00000000 /* R---V */ |
2416 |
#define NV_PEXTDEV_BOOT_0_STRAP_CRYSTAL_14318180 0x00000001 /* R---V */ |
2417 |
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE 8:7 /* R-XVF */ |
2418 |
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_SECAM 0x00000000 /* R---V */ |
2419 |
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_NTSC 0x00000001 /* R---V */ |
2420 |
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_PAL 0x00000002 /* R---V */ |
2421 |
#define NV_PEXTDEV_BOOT_0_STRAP_TVMODE_DISABLED 0x00000003 /* R---V */ |
2422 |
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE 11:11 /* RWIVF */ |
2423 |
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_DISABLED 0x00000000 /* RWI-V */ |
2424 |
#define NV_PEXTDEV_BOOT_0_STRAP_OVERWRITE_ENABLED 0x00000001 /* RW--V */ |
2425 |
|
2426 |
/* Extras */ |
2427 |
#define NV_PRAMIN 0x007FFFFF:0x00700000 /* RW--M */ |
2428 |
/*#define NV_PRAMIN 0x00FFFFFF:0x00C00000*/ |
2429 |
#define NV_PNVM 0x01FFFFFF:0x01000000 /* RW--M */ |
2430 |
/*#define NV_PNVM 0x00BFFFFF:0x00800000*/ |
2431 |
#define NV_CHAN0 0x0080ffff:0x00800000 |
2432 |
|
2433 |
/* FIFO subchannels */ |
2434 |
#define NV_UROP 0x43 |
2435 |
#define NV_UCHROMA 0x57 |
2436 |
#define NV_UCLIP 0x19 |
2437 |
#define NV_UPATT 0x18 |
2438 |
#define NV_ULIN 0x5C |
2439 |
#define NV_UTRI 0x5D |
2440 |
#define NV_URECT 0x5E |
2441 |
#define NV_UBLIT 0x5F |
2442 |
#define NV_UGLYPH 0x4B |
2443 |
|
2444 |
#endif /*__NV4REF_H__*/ |
2445 |
|