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Gentoo's Bugzilla – Attachment 303109 Details for
Bug 401669
sys-kernel/hardened-sources-2.6.32-r89: Compilation broken on ia64
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vmlinux.lds of linux-2.6.32-hardened-r91 with 64kb pages
linux-2.6.32-hardened-r91.vmlinux.lds (text/plain), 26.93 KB, created by
Dennis Schridde
on 2012-02-25 01:11:29 UTC
(
hide
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Description:
vmlinux.lds of linux-2.6.32-hardened-r91 with 64kb pages
Filename:
MIME Type:
Creator:
Dennis Schridde
Created:
2012-02-25 01:11:29 UTC
Size:
26.93 KB
patch
obsolete
>/* > * Automatically generated C config: don't edit > * Linux kernel version: 2.6.32-hardened-r91 > * Sat Feb 25 01:29:02 2012 > */ >/* > * Copyright (C) 1998-2000 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/* Bytes per L1 (data) cache line. */ >/* > * Copyright (C) 1998-2004 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > * Stephane Eranian <eranian@hpl.hp.com> > * Copyright (C) 2003 Intel Co > * Suresh Siddha <suresh.b.siddha@intel.com> > * Fenghua Yu <fenghua.yu@intel.com> > * Arun Sharma <arun.sharma@intel.com> > * > * 12/07/98 S. Eranian added pt_regs & switch_stack > * 12/21/98 D. Mosberger updated to match latest code > * 6/17/99 D. Mosberger added second unat member to "struct switch_stack" > * > */ >/* > * When a user process is blocked, its state looks as follows: > * > * +----------------------+ ------- IA64_STK_OFFSET > * | | ^ > * | struct pt_regs | | > * | | | > * +----------------------+ | > * | | | > * | memory stack | | > * | (growing downwards) | | > * //.....................// | > * | > * //.....................// | > * | | | > * +----------------------+ | > * | struct switch_stack | | > * | | | > * +----------------------+ | > * | | | > * //.....................// | > * | > * //.....................// | > * | | | > * | register stack | | > * | (growing upwards) | | > * | | | > * +----------------------+ | --- IA64_RBS_OFFSET > * | struct thread_info | | ^ > * +----------------------+ | | > * | | | | > * | struct task_struct | | | > * current -> | | | | > * +----------------------+ ------- > * > * Note that ar.ec is not saved explicitly in pt_reg or switch_stack. > * This is because ar.ec is saved as part of ar.pfs. > */ >/* > * Copyright (C) 1998, 1999, 2002, 2003 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/* > * This file is never included by application software unless explicitly > * requested (e.g., via linux/types.h) in which case the application is > * Linux specific so (user-) name space pollution is not a major issue. > * However, for interoperability, libraries still need to be careful to > * avoid naming clashes. > * > * Based on <asm-alpha/types.h>. > * > * Modified 1998-2000, 2002 > * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co > */ >/* > * asm-generic/int-ll64.h > * > * Integer declarations for architectures which use "long long" > * for 64-bit types. > */ >/* > * There seems to be no way of detecting this automatically from user > * space, so 64 bit architectures should override this in their > * bitsperlong.h. In particular, an architecture that supports > * both 32 and 64 bit user space must not rely on CONFIG_64BIT > * to decide it, but rather check a compiler provided macro. > */ >/* > * FIXME: The check currently breaks x86-64 build, so it's > * temporarily disabled. Please fix x86-64 and reenable > */ >/* floating point status register: */ >/* floating-point status field controls: */ >/* floating-point status field flags: */ >/* floating-point rounding control: */ >/* This default value is the same as HP-UX uses. Don't change it > without a very good reason. */ >/* > * DO NOT MODIFY. > * > * This file was generated by Kbuild > * > */ >/* > * Base-2 logarithm of number of pages to allocate per task structure > * (including register backing store and memory stack): > */ >/* indices to application-registers array in pt_all_user_regs */ >/* > * The numbers chosen here are somewhat arbitrary but absolutely MUST > * not overlap with any of the number assigned in <linux/ptrace.h>. > */ >/* > * System defines. Note that this is included both from .c and .S > * files, so it does only defines, not any C code. This is based > * on information published in the Processor Abstraction Layer > * and the System Abstraction Layer manual. > * > * Copyright (C) 1998-2003 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> > * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> > */ >/* > * Copyright (C) 2001-2002 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/* > * This file defines the kernel register usage convention used by Linux/ia64. > */ >/* > * Kernel registers: > */ >/* > * Translation registers: > */ >/* Processor status register bits: */ >/* The following are not affected by save_flags()/restore_flags(): */ >/* A mask of PSR bits that we generally don't want to inherit across a clone2() or an > execve(). Only list flags here that need to be cleared/set for BOTH clone2() and > execve(). */ >/* The following are not affected by save_flags()/restore_flags(): */ >/* User mask bits: */ >/* Default Control Register */ >/* Interrupt Status Register */ > > > > > > > >/* ISR code field for non-access instructions */ >/* > * Pagetable related stuff. > * > * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/* > * Compiler-dependent intrinsics. > * > * Copyright (C) 2002-2003 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/****************************************************************************** > * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp> > * VA Linux Systems Japan K.K. > * > * This program is free software; you can redistribute it and/or modify > * it under the terms of the GNU General Public License as published by > * the Free Software Foundation; either version 2 of the License, or > * (at your option) any later version. > * > * This program is distributed in the hope that it will be useful, > * but WITHOUT ANY WARRANTY; without even the implied warranty of > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > * GNU General Public License for more details. > * > * You should have received a copy of the GNU General Public License > * along with this program; if not, write to the Free Software > * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA > * > */ >/* fallback for native case */ >/* these routines utilize privilege-sensitive or performance-sensitive > * privileged instructions so the code must be replaced with > * paravirtualized versions */ >/* > * The top three bits of an IA64 address are its Region Number. > * Different regions are assigned to different purposes. > */ >/* > * PAGE_SHIFT determines the actual kernel page size. > */ > /* > * .. while these make it easier on the compiler > */ >/* > * Processor Abstraction Layer definitions. > * > * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0 > * chapter 11 IA-64 Processor Abstraction Layer > * > * Copyright (C) 1998-2001 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > * Stephane Eranian <eranian@hpl.hp.com> > * Copyright (C) 1999 VA Linux Systems > * Copyright (C) 1999 Walt Drummond <drummond@valinux.com> > * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com> > * Copyright (C) 2008 Silicon Graphics, Inc. (SGI) > * > * 99/10/01 davidm Make sure we pass zero for reserved parameters. > * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6. > * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info > * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added > * 00/05/25 eranian Support for stack calls, and static physical calls > * 00/06/18 eranian Support for stacked physical calls > * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's > * Manual Rev 2.2 (Jan 2006) > */ >/* > * Note that some of these calls use a static-register only calling > * convention which has nothing to do with the regular calling > * convention. > */ >/* > * Copyright (C) 2002-2003 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/* > * 0xa000000000000000+2*PERCPU_PAGE_SIZE > * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page) > */ >/* > * This file contains the functions and defines necessary to modify and use > * the IA-64 page table tree. > * > * This hopefully works with any (fixed) IA-64 page-size, as defined > * in <asm/page.h>. > * > * Copyright (C) 1998-2005 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > */ >/* const.h: Macros for dealing with constants. */ >/* Some constant macros are used in both assembler and > * C code. Therefore we cannot annotate them always with > * 'UL' and other type specifiers unilaterally. We > * use the following macros to deal with this. > * > * Similarly, _AT() will cast an expression with a type in C, but > * leave it unchanged in asm. > */ >/* > * Based on <asm-i386/mman.h>. > * > * Modified 1998-2000, 2002 > * David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co > */ >/* > Author: Michael S. Tsirkin <mst@mellanox.co.il>, Mellanox Technologies Ltd. > Based on: asm-xxx/mman.h >*/ >/* common parameters: try to keep these consistent across architectures */ >/* compatibility flags */ >/* > * Copyright (C) 1998-2004 Hewlett-Packard Co > * David Mosberger-Tang <davidm@hpl.hp.com> > * Stephane Eranian <eranian@hpl.hp.com> > * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com> > * Copyright (C) 1999 Don Dugger <don.dugger@intel.com> > * > * 11/24/98 S.Eranian added ia64_set_iva() > * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API > * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support > */ >/* > * Constants for the user stack size > */ >/* The absolute hard limit for stack size is 1/2 of the mappable space in the region */ >/* Make a default stack size of 2GiB */ >/* > * TASK_SIZE really is a mis-named. It really is the maximum user > * space address (plus one). On IA-64, there are five regions of 2TB > * each (assuming 8KB page size), for a total of 8TB of user virtual > * address space. > */ >/* > * This decides where the kernel will search for a free chunk of vm > * space during mmap's. > */ >/* > * This shift should be large enough to be able to represent 1000000000/itc_freq with good > * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits > * (this will give enough slack to represent 10 seconds worth of time as a scaled number). > */ >/* > * First, define the various bits in a PTE. Note that the PTE format > * matches the VHPT short format, the firt doubleword of the VHPD long > * format, and the first doubleword of the TLB insertion format. > */ >/* Valid only for a PTE with the present bit cleared: */ >/* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */ >/* > * How many pointers will a page table level hold expressed in shift > */ >/* > * Definitions for fourth level: > */ >/* > * Definitions for third level: > * > * PMD_SHIFT determines the size of the area a third-level page table > * can map. > */ >/* > * Definitions for first level: > * > * PGDIR_SHIFT determines what a first-level page table entry can map. > */ >/* > * All the normal masks have the "page accessed" bits on, as any time > * they are used, the page is accessed. They are cleared only by the > * page-out routines. > */ >/* > * Identity-mapped regions use a large page size. We'll call such large pages > * "granules". If you can think of a better name that's unambiguous, let me > * know... > */ >/* > * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL): > */ >/* > * No page table caches to initialise > */ >/* These tell get_user_pages() that the first gate page is accessible from user-level. */ >/* > * Helper macros to support writing architecture specific > * linker scripts. > * > * A minimal linker scripts has following content: > * [This is a sample, architectures may have special requiriements] > * > * OUTPUT_FORMAT(...) > * OUTPUT_ARCH(...) > * ENTRY(...) > * SECTIONS > * { > * . = START; > * __init_begin = .; > * HEAD_TEXT_SECTION > * INIT_TEXT_SECTION(PAGE_SIZE) > * INIT_DATA_SECTION(...) > * PERCPU(PAGE_SIZE) > * __init_end = .; > * > * _stext = .; > * TEXT_SECTION = 0 > * _etext = .; > * > * _sdata = .; > * RO_DATA_SECTION(PAGE_SIZE) > * RW_DATA_SECTION(...) > * _edata = .; > * > * EXCEPTION_TABLE(...) > * NOTES > * > * BSS_SECTION(0, 0, 0) > * _end = .; > * > * STABS_DEBUG > * DWARF_DEBUG > * > * DISCARDS // must be the last > * } > * > * [__init_begin, __init_end] is the init section that may be freed after init > * [_stext, _etext] is the text section > * [_sdata, _edata] is the data section > * > * Some of the included output section have their own set of constants. > * Examples are: [__initramfs_start, __initramfs_end] for initramfs and > * [__nosave_begin, __nosave_end] for the nosave data > */ >/* Align . to a 8 byte boundary equals to maximum function alignment. */ >/* The actual configuration determine if the init/exit sections > * are handled as text/data or they can be discarded (which > * often happens at runtime) > */ >/* .data section */ >/* > * Data section helpers > */ >/* > * Read only Data > */ >/* RODATA & RO_DATA provided for backward compatibility. > * All archs are supposed to use RO_DATA() */ >/* .text section. Map to function alignment to avoid address changes > * during second ld run in second ld pass when generating System.map */ >/* sched.text is aling to function alignment to secure we have same > * address even at second ld pass when generating System.map */ >/* spinlock.text is aling to function alignment to secure we have same > * address even at second ld pass when generating System.map */ >/* Section used for early init (in .S files) */ > > > > > > > >/* > * Exception table > */ >/* > * Init task > */ >/* init and exit section handling */ >/* > * bss (Block Started by Symbol) - uninitialized data > * zeroed during startup > */ >/* > * DWARF debug sections. > * Symbols in the DWARF debugging sections are relative to > * the beginning of the section so we begin them at 0. > */ > /* Stabs debugging sections. */ >/* > * Default discarded sections. > * > * Some archs want to discard exit text/data at runtime rather than > * link time due to cross-section references such as alt instructions, > * bug table, eh_frame, etc. DISCARDS must be the last of output > * section definitions so that such archs put those in earlier section > * definitions. > */ >/** > * PERCPU_VADDR - define output section for percpu area > * @vaddr: explicit base address (optional) > * @phdr: destination PHDR (optional) > * > * Macro which expands to output section for percpu area. If @vaddr > * is not blank, it specifies explicit base address and all percpu > * symbols will be offset from the given address. If blank, @vaddr > * always equals @laddr + LOAD_OFFSET. > * > * @phdr defines the output PHDR to use if not blank. Be warned that > * output PHDR is sticky. If @phdr is specified, the next output > * section in the linker script will go there too. @phdr should have > * a leading colon. > * > * Note that this macros defines per_cpu_load as an absolute symbol. > * If there is no need to put the percpu section at a predetermined > * address, use PERCPU(). > */ >/** > * PERCPU - define output section for percpu area, simple version > * @align: required alignment > * > * Align to @align and outputs output section for percpu area. This > * macro doesn't maniuplate @vaddr or @phdr and __per_cpu_load and > * __per_cpu_start will be identical. > * > * This macro is equivalent to ALIGN(align); PERCPU_VADDR( , ) except > * that __per_cpu_load is defined as a relative symbol against > * .data.percpu which is required for relocatable x86_32 > * configuration. > */ >/* > * Definition of the high level *_SECTION macros > * They will fit only a subset of the architectures > */ >/* > * Writeable data. > * All sections are combined in a single .data section. > * The sections following CONSTRUCTORS are arranged so their > * typical alignment matches. > * A cacheline is typical/always less than a PAGE_SIZE so > * the sections that has this restriction (or similar) > * is located before the ones requiring PAGE_SIZE alignment. > * NOSAVE_DATA starts and ends with a PAGE_SIZE alignment which > * matches the requirment of PAGE_ALIGNED_DATA. > * > * use 0 as page_align if page_aligned data is not used */ >OUTPUT_FORMAT("elf64-ia64-little") >OUTPUT_ARCH(ia64) >ENTRY(phys_start) >jiffies = jiffies_64; >PHDRS { > code PT_LOAD; > percpu PT_LOAD; > data PT_LOAD; > note PT_NOTE; > unwind 0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */ >} >SECTIONS >{ > /* unwind exit sections must be discarded before the rest of the > sections get included. */ > /DISCARD/ : { > *(.IA_64.unwind.exit.text) > *(.IA_64.unwind_info.exit.text) > *(.comment) > *(.note) > } > v = (7<<(61)); /* this symbol is here to make debugging easier... */ > phys_start = _start - (((5<<(61))+0x100000000) - (1 << 26)); > code : { } :code > . = ((5<<(61))+0x100000000); > _text = .; > _stext = .; > .text : AT(ADDR(.text) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start_ivt_text = .; *(.text.ivt) __end_ivt_text = .; > . = ALIGN(8); *(.text.hot) *(.text) *(.ref.text) *(.devinit.text) *(.devexit.text) *(.cpuinit.text) *(.cpuexit.text) *(.text.unlikely) > . = ALIGN(8); __sched_text_start = .; *(.sched.text) __sched_text_end = .; > . = ALIGN(8); __lock_text_start = .; *(.spinlock.text) __lock_text_end = .; > . = ALIGN(8); __kprobes_text_start = .; *(.kprobes.text) __kprobes_text_end = .; > *(.gnu.linkonce.t*) > } > .text2 : AT(ADDR(.text2) - (((5<<(61))+0x100000000) - (1 << 26))) > { *(.text2) } > .text.lock : AT(ADDR(.text.lock) - (((5<<(61))+0x100000000) - (1 << 26))) > { *(.text.lock) } > _etext = .; > /* Read-only data */ > .notes : AT(ADDR(.notes) - (((5<<(61))+0x100000000) - (1 << 26))) { __start_notes = .; *(.note.*) __stop_notes = .; } :code :note /* put .notes in text and mark in PT_NOTE */ > code_continues : {} :code /* switch back to regular program... */ > . = ALIGN(16); __ex_table : AT(ADDR(__ex_table) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___ex_table = .; *(__ex_table) __stop___ex_table = .; } > /* MCA table */ > . = ALIGN(16); > __mca_table : AT(ADDR(__mca_table) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start___mca_table = .; > *(__mca_table) > __stop___mca_table = .; > } > .data.patch.phys_stack_reg : AT(ADDR(.data.patch.phys_stack_reg) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start___phys_stack_reg_patchlist = .; > *(.data.patch.phys_stack_reg) > __end___phys_stack_reg_patchlist = .; > } > /* Global data */ > _data = .; > /* Unwind info & table: */ > . = ALIGN(8); > .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - (((5<<(61))+0x100000000) - (1 << 26))) > { *(.IA_64.unwind_info*) } > .IA_64.unwind : AT(ADDR(.IA_64.unwind) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start_unwind = .; > *(.IA_64.unwind*) > __end_unwind = .; > } :code :unwind > code_continues2 : {} : code > . = ALIGN((4096)); .rodata : AT(ADDR(.rodata) - (((5<<(61))+0x100000000) - (1 << 26))) { __start_rodata = .; *(.rodata) *(.rodata.*) *(.data.read_only) *(__vermagic) *(__markers_strings) *(__tracepoints_strings) } .rodata1 : AT(ADDR(.rodata1) - (((5<<(61))+0x100000000) - (1 << 26))) { *(.rodata1) } .pci_fixup : AT(ADDR(.pci_fixup) - (((5<<(61))+0x100000000) - (1 << 26))) { __start_pci_fixups_early = .; *(.pci_fixup_early) __end_pci_fixups_early = .; __start_pci_fixups_header = .; *(.pci_fixup_header) __end_pci_fixups_header = .; __start_pci_fixups_final = .; *(.pci_fixup_final) __end_pci_fixups_final = .; __start_pci_fixups_enable = .; *(.pci_fixup_enable) __end_pci_fixups_enable = .; __start_pci_fixups_resume = .; *(.pci_fixup_resume) __end_pci_fixups_resume = .; __start_pci_fixups_resume_early = .; *(.pci_fixup_resume_early) __end_pci_fixups_resume_early = .; __start_pci_fixups_suspend = .; *(.pci_fixup_suspend) __end_pci_fixups_suspend = .; } .builtin_fw : AT(ADDR(.builtin_fw) - (((5<<(61))+0x100000000) - (1 << 26))) { __start_builtin_fw = .; *(.builtin_fw) __end_builtin_fw = .; } .rio_route : AT(ADDR(.rio_route) - (((5<<(61))+0x100000000) - (1 << 26))) { __start_rio_route_ops = .; *(.rio_route_ops) __end_rio_route_ops = .; } __ksymtab : AT(ADDR(__ksymtab) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___ksymtab = .; *(__ksymtab) __stop___ksymtab = .; } __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___ksymtab_gpl = .; *(__ksymtab_gpl) __stop___ksymtab_gpl = .; } __ksymtab_unused : AT(ADDR(__ksymtab_unused) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___ksymtab_unused = .; *(__ksymtab_unused) __stop___ksymtab_unused = .; } __ksymtab_unused_gpl : AT(ADDR(__ksymtab_unused_gpl) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___ksymtab_unused_gpl = .; *(__ksymtab_unused_gpl) __stop___ksymtab_unused_gpl = .; } __ksymtab_gpl_future : AT(ADDR(__ksymtab_gpl_future) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___ksymtab_gpl_future = .; *(__ksymtab_gpl_future) __stop___ksymtab_gpl_future = .; } __kcrctab : AT(ADDR(__kcrctab) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___kcrctab = .; *(__kcrctab) __stop___kcrctab = .; } __kcrctab_gpl : AT(ADDR(__kcrctab_gpl) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___kcrctab_gpl = .; *(__kcrctab_gpl) __stop___kcrctab_gpl = .; } __kcrctab_unused : AT(ADDR(__kcrctab_unused) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___kcrctab_unused = .; *(__kcrctab_unused) __stop___kcrctab_unused = .; } __kcrctab_unused_gpl : AT(ADDR(__kcrctab_unused_gpl) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___kcrctab_unused_gpl = .; *(__kcrctab_unused_gpl) __stop___kcrctab_unused_gpl = .; } __kcrctab_gpl_future : AT(ADDR(__kcrctab_gpl_future) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___kcrctab_gpl_future = .; *(__kcrctab_gpl_future) __stop___kcrctab_gpl_future = .; } __ksymtab_strings : AT(ADDR(__ksymtab_strings) - (((5<<(61))+0x100000000) - (1 << 26))) { *(__ksymtab_strings) } __init_rodata : AT(ADDR(__init_rodata) - (((5<<(61))+0x100000000) - (1 << 26))) { *(.ref.rodata) *(.devinit.rodata) *(.devexit.rodata) *(.cpuinit.rodata) *(.cpuexit.rodata) } __param : AT(ADDR(__param) - (((5<<(61))+0x100000000) - (1 << 26))) { __start___param = .; *(__param) __stop___param = .; . = ALIGN((4096)); __end_rodata = .; } . = ALIGN((4096)); > .opd : AT(ADDR(.opd) - (((5<<(61))+0x100000000) - (1 << 26))) > { *(.opd) } > /* Initialization code and data: */ > . = ALIGN((1 << 16)); > __init_begin = .; > . = ALIGN((1 << 16)); .init.text : AT(ADDR(.init.text) - (((5<<(61))+0x100000000) - (1 << 26))) { _sinittext = .; *(.init.text) *(.meminit.text) _einittext = .; } > .init.data : AT(ADDR(.init.data) - (((5<<(61))+0x100000000) - (1 << 26))) { *(.init.data) *(.meminit.data) . = ALIGN(8); __ctors_start = .; *(.ctors) __ctors_end = .; *(.init.rodata) *(.meminit.rodata) . = ALIGN(16); __setup_start = .; *(.init.setup) __setup_end = .; __initcall_start = .; *(.initcallearly.init) __early_initcall_end = .; *(.initcall0.init) *(.initcall0s.init) *(.initcall1.init) *(.initcall1s.init) *(.initcall2.init) *(.initcall2s.init) *(.initcall3.init) *(.initcall3s.init) *(.initcall4.init) *(.initcall4s.init) *(.initcall5.init) *(.initcall5s.init) *(.initcallrootfs.init) *(.initcall6.init) *(.initcall6s.init) *(.initcall7.init) *(.initcall7s.init) __initcall_end = .; __con_initcall_start = .; *(.con_initcall.init) __con_initcall_end = .; __security_initcall_start = .; *(.security_initcall.init) __security_initcall_end = .; . = ALIGN((1 << 16)); __initramfs_start = .; *(.init.ramfs) __initramfs_end = .; } > .data.patch.vtop : AT(ADDR(.data.patch.vtop) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start___vtop_patchlist = .; > *(.data.patch.vtop) > __end___vtop_patchlist = .; > } > .data.patch.rse : AT(ADDR(.data.patch.rse) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start___rse_patchlist = .; > *(.data.patch.rse) > __end___rse_patchlist = .; > } > .data.patch.mckinley_e9 : AT(ADDR(.data.patch.mckinley_e9) - (((5<<(61))+0x100000000) - (1 << 26))) > { > __start___mckinley_e9_bundles = .; > *(.data.patch.mckinley_e9) > __end___mckinley_e9_bundles = .; > } > . = ALIGN((1 << 16)); > __init_end = .; > .data.page_aligned : AT(ADDR(.data.page_aligned) - (((5<<(61))+0x100000000) - (1 << 26))) > { > . = ALIGN((1 << 16)); *(.data.page_aligned) > . = ALIGN((1 << 16)); > __start_gate_section = .; > *(.data.gate) > __stop_gate_section = .; > } > . = ALIGN((1 << 16)); /* make sure the gate page doesn't expose > * kernel data > */ > /* Per-cpu data: */ > . = ALIGN((1 << 16)); > per_cpu_load = .; .data.percpu (-(1 << 16)) : AT(per_cpu_load - (((5<<(61))+0x100000000) - (1 << 26))) { __per_cpu_load = . + per_cpu_load; __per_cpu_start = .; *(.data.percpu.first) *(.data.percpu) . = ALIGN((1 << 16)); *(.data.percpu.page_aligned) *(.data.percpu.shared_aligned) __per_cpu_end = .; } :percpu . = per_cpu_load + SIZEOF(.data.percpu); > __phys_per_cpu_start = per_cpu_load; > . = __phys_per_cpu_start + (1 << 16); /* ensure percpu data fits > * into percpu page size > */ > data : { } :data > .data : AT(ADDR(.data) - (((5<<(61))+0x100000000) - (1 << 26))) > { > . = ALIGN((1 << 16)); > __cpu0_per_cpu = .; > . = . + (1 << 16); /* cpu0 per-cpu space */ > . = ALIGN((1 << 16)); *(.data.init_task) > . = ALIGN((1 << 7)); *(.data.cacheline_aligned) > . = ALIGN((1 << 7)); *(.data.read_mostly) > *(.data) *(.ref.data) *(.devinit.data) *(.devexit.data) *(.cpuinit.data) *(.cpuexit.data) . = ALIGN(8); __start___markers = .; *(__markers) __stop___markers = .; . = ALIGN(32); __start___tracepoints = .; *(__tracepoints) __stop___tracepoints = .; . = ALIGN(8); __start___verbose = .; *(__verbose) __stop___verbose = .; > *(.data1) > *(.gnu.linkonce.d*) > CONSTRUCTORS > } > . = ALIGN(16); /* gp must be 16-byte aligned for exc. table */ > .got : AT(ADDR(.got) - (((5<<(61))+0x100000000) - (1 << 26))) > { *(.got.plt) *(.got) } > __gp = ADDR(.got) + 0x200000; > /* We want the small data sections together, so single-instruction offsets > can access them all, and initialized data all before uninitialized, so > we can shorten the on-disk segment size. */ > .sdata : AT(ADDR(.sdata) - (((5<<(61))+0x100000000) - (1 << 26))) > { *(.sdata) *(.sdata1) *(.srdata) } > _edata = .; > . = ALIGN(0); __bss_start = .; . = ALIGN(0); .sbss : AT(ADDR(.sbss) - (((5<<(61))+0x100000000) - (1 << 26))) { *(.sbss) *(.scommon) } . = ALIGN(0); .bss : AT(ADDR(.bss) - (((5<<(61))+0x100000000) - (1 << 26))) { *(.bss.page_aligned) *(.dynbss) *(.bss) *(COMMON) } . = ALIGN(0); __bss_stop = .; > _end = .; > code : { } :code > .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) } .stab.exclstr 0 : { *(.stab.exclstr) } .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } > .debug 0 : { *(.debug) } .line 0 : { *(.line) } .debug_srcinfo 0 : { *(.debug_srcinfo) } .debug_sfnames 0 : { *(.debug_sfnames) } .debug_aranges 0 : { *(.debug_aranges) } .debug_pubnames 0 : { *(.debug_pubnames) } .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } .debug_abbrev 0 : { *(.debug_abbrev) } .debug_line 0 : { *(.debug_line) } .debug_frame 0 : { *(.debug_frame) } .debug_str 0 : { *(.debug_str) } .debug_loc 0 : { *(.debug_loc) } .debug_macinfo 0 : { *(.debug_macinfo) } .debug_weaknames 0 : { *(.debug_weaknames) } .debug_funcnames 0 : { *(.debug_funcnames) } .debug_typenames 0 : { *(.debug_typenames) } .debug_varnames 0 : { *(.debug_varnames) } > /* Default discards */ > /DISCARD/ : { *(.exit.text) *(.memexit.text) *(.exit.data) *(.memexit.data) *(.memexit.rodata) *(.exitcall.exit) *(.discard) } >}
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