Attachment #272251 for bug #360427

Lines 132-137 Link Here

(-)a/ipc/chromium/src/base/atomicops.h (+2 lines)
132	#include "base/atomicops_internals_x86_gcc.h"	132	#include "base/atomicops_internals_x86_gcc.h"
133	#elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY)	133	#elif defined(COMPILER_GCC) && defined(ARCH_CPU_ARM_FAMILY)
134	#include "base/atomicops_internals_arm_gcc.h"	134	#include "base/atomicops_internals_arm_gcc.h"
		135	#elif defined(COMPILER_GCC) && defined(ARCH_CPU_PPC)
		136	#include "base/atomicops_internals_ppc_gcc.h"
135	#else	137	#else
136	#include "base/atomicops_internals_mutex.h"	138	#include "base/atomicops_internals_mutex.h"
137	#endif	139	#endif




// Copyright (c) 2010 JJDaNiMoTh <jjdanimoth@gmail.com>. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.

// This file is an internal atomic implementation, use base/atomicops.h instead.

#ifndef BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_
#define BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_
#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")

#define PPC_ACQUIRE_BARRIER     "\nisync\n"
#define PPC_RELEASE_BARRIER     "\nlwsync\n"

namespace base {
namespace subtle {

// 32-bit low-level operations on any platform.

/*
 * Compare and exchange - if *ptr == old, set it to new,
 * and return the old value of *p.
 */
inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
                                         Atomic32 old_value,
                                         Atomic32 new_value) {
	Atomic32 prev;

	__asm__ __volatile__ (
	"1: lwarx   %0,0,%2\n"
	"cmpw    0,%0,%3\n"
	"bne-    2f\n"
	"stwcx.  %4,0,%2\n"
	"bne-    1b\n"
	"2:\n"
	: "=&r" (prev), "+m" (*ptr)
	: "r" (ptr), "r" (old_value), "r" (new_value)
	: "cc", "memory");

	return prev;
}

/*
* Atomic exchange
*
* Changes the memory location '*ptr' to be new_value and returns
* the previous value stored there.
*/
inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
                                         Atomic32 new_value) {
        Atomic32 prev;

        __asm__ __volatile__(
"1:     lwarx   %0,0,%2 \n"
"       stwcx.  %3,0,%2 \n\
        bne-    1b"
        : "=&r" (prev), "+m" (*ptr)
        : "r" (ptr), "r" (new_value)
        : "cc", "memory");

        return prev;
}

inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
                                          Atomic32 increment) {
        Atomic32 temp;

        __asm__ __volatile__(
"1:     lwarx   %0,0,%2\n\
        add     %0,%1,%0\n"
"       stwcx.  %0,0,%2 \n\
        bne-    1b"
        : "=&r" (temp)
        : "r" (increment), "r" (ptr)
        : "cc", "memory");

        return temp;
}

inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
                                        Atomic32 increment) {
        Atomic32 temp;

        __asm__ __volatile__(
	PPC_RELEASE_BARRIER
"1:     lwarx   %0,0,%2\n\
        add     %0,%1,%0\n"
"       stwcx.  %0,0,%2 \n\
        bne-    1b"
        PPC_ACQUIRE_BARRIER
        : "=&r" (temp)
        : "r" (increment), "r" (ptr)
        : "cc", "memory");

        return temp;
}

inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
                                       Atomic32 old_value,
                                       Atomic32 new_value) {
  return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
}

inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
                                       Atomic32 old_value,
                                       Atomic32 new_value) {
  return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
}

inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
  *ptr = value;
}

inline void MemoryBarrier() {
  __asm__ __volatile__("sync" : : : "memory");
}

inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
  *ptr = value;
  MemoryBarrier();
}

inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
  MemoryBarrier();
  *ptr = value;
}

inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
  return *ptr;
}

inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
  Atomic32 value = *ptr;
  MemoryBarrier();
  return value;

}

inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
  MemoryBarrier();
  return *ptr;
}

} // namespace base::subtle
} // namespace base

#undef ATOMICOPS_COMPILER_BARRIER

#endif  // BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_




bool DataPack::Get(uint32_t resource_id, StringPiece* data) {
  // It won't be hard to make this endian-agnostic, but it's not worth
  // bothering to do right now.
#warning DoTheRightThingMakingThisEndianAgnostic!
  // Linux check
  COMPILE_ASSERT(__BYTE_ORDER == __LITTLE_ENDIAN,
                 datapack_assumes_little_endian);
#elif defined(__BIG_ENDIAN__)
  // Mac check
  #error DataPack assumes little endian
#endif

  DataPackEntry* target = reinterpret_cast<DataPackEntry*>(
      bsearch(&resource_id, mmap_->data() + kHeaderLength, resource_count_,
              sizeof(DataPackEntry), DataPackEntry::CompareById));

Lines 110-117 Link Here

(-)a/ipc/chromium/src/base/debug_util_posix.cc (-1 / +3 lines)
110		110
111	// static	111	// static
112	void DebugUtil::BreakDebugger() {	112	void DebugUtil::BreakDebugger() {
113	#if defined(ARCH_CPU_X86_FAMILY)	113	#if defined(ARCH_CPU_X86_FAMILY) && !defined(ARCH_CPU_PPC)
114	asm ("int3");	114	asm ("int3");
		115	elif defined(ARCH_CPU_PPC)
		116	asm ("trap");
115	#endif	117	#endif
116	}	118	}
117		119

Lines 57-63 Link Here

(-)a/ipc/chromium/src/build/build_config.h (-1 / +1 lines)
57	#define ARCH_CPU_ARMEL 1	57	#define ARCH_CPU_ARMEL 1
58	#define ARCH_CPU_32_BITS 1	58	#define ARCH_CPU_32_BITS 1
59	#define WCHAR_T_IS_UNSIGNED 1	59	#define WCHAR_T_IS_UNSIGNED 1
60	#elif defined(__ppc__)	60	#elif defined(__ppc__) \|\| defined(__powerpc__)
61	#define ARCH_CPU_PPC 1	61	#define ARCH_CPU_PPC 1
62	#define ARCH_CPU_32_BITS 1	62	#define ARCH_CPU_32_BITS 1
63	#else	63	#else





ifneq (86,$(findstring 86,$(OS_TEST))) # {
ifneq (arm,$(findstring arm,$(OS_TEST))) # {
ifneq (powerpc,$(findstring powerpc,$(OS_TEST))) # {
# Use mutex-backed atomics
CPPSRCS += atomicops_internals_mutex.cc
endif # }
endif # }
endif # }

OS_CXXFLAGS += $(TK_CFLAGS)


Return to bug 360427

Lines 91-105 Link Here

(-)a/ipc/chromium/src/base/data_pack.cc (-9 / +1 lines)
91	bool DataPack::Get(uint32_t resource_id, StringPiece* data) {	91	bool DataPack::Get(uint32_t resource_id, StringPiece* data) {
92	// It won't be hard to make this endian-agnostic, but it's not worth	92	// It won't be hard to make this endian-agnostic, but it's not worth
93	// bothering to do right now.	93	// bothering to do right now.
94	#if defined(__BYTE_ORDER)	94	#warning DoTheRightThingMakingThisEndianAgnostic!
95	// Linux check
96	COMPILE_ASSERT(__BYTE_ORDER == __LITTLE_ENDIAN,
97	datapack_assumes_little_endian);
98	#elif defined(__BIG_ENDIAN__)
99	// Mac check
100	#error DataPack assumes little endian
101	#endif
102
103	DataPackEntry* target = reinterpret_cast<DataPackEntry*>(	95	DataPackEntry* target = reinterpret_cast<DataPackEntry*>(
104	bsearch(&resource_id, mmap_->data() + kHeaderLength, resource_count_,	96	bsearch(&resource_id, mmap_->data() + kHeaderLength, resource_count_,
105	sizeof(DataPackEntry), DataPackEntry::CompareById));	97	sizeof(DataPackEntry), DataPackEntry::CompareById));

Lines 318-327 Link Here

(-)a/ipc/chromium/Makefile.in (+2 lines)
318		318
319	ifneq (86,$(findstring 86,$(OS_TEST))) # {	319	ifneq (86,$(findstring 86,$(OS_TEST))) # {
320	ifneq (arm,$(findstring arm,$(OS_TEST))) # {	320	ifneq (arm,$(findstring arm,$(OS_TEST))) # {
		321	ifneq (powerpc,$(findstring powerpc,$(OS_TEST))) # {
321	# Use mutex-backed atomics	322	# Use mutex-backed atomics
322	CPPSRCS += atomicops_internals_mutex.cc	323	CPPSRCS += atomicops_internals_mutex.cc
323	endif # }	324	endif # }
324	endif # }	325	endif # }
		326	endif # }
325		327
326	OS_CXXFLAGS += $(TK_CFLAGS)	328	OS_CXXFLAGS += $(TK_CFLAGS)
327		329

Added Link Here

(-)3ff945bdace7 (+148 lines)
1	// Copyright (c) 2010 JJDaNiMoTh <jjdanimoth@gmail.com>. All rights reserved.
2	// Use of this source code is governed by a BSD-style license that can be
3	// found in the LICENSE file.
4
5	// This file is an internal atomic implementation, use base/atomicops.h instead.
6
7	#ifndef BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_
8	#define BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_
9	#define ATOMICOPS_COMPILER_BARRIER() __asm__ __volatile__("" : : : "memory")
10
11	#define PPC_ACQUIRE_BARRIER "\nisync\n"
12	#define PPC_RELEASE_BARRIER "\nlwsync\n"
13
14	namespace base {
15	namespace subtle {
16
17	// 32-bit low-level operations on any platform.
18
19	/*
20	* Compare and exchange - if *ptr == old, set it to new,
21	* and return the old value of *p.
22	*/
23	inline Atomic32 NoBarrier_CompareAndSwap(volatile Atomic32* ptr,
24	Atomic32 old_value,
25	Atomic32 new_value) {
26	Atomic32 prev;
27
28	__asm__ __volatile__ (
29	"1: lwarx %0,0,%2\n"
30	"cmpw 0,%0,%3\n"
31	"bne- 2f\n"
32	"stwcx. %4,0,%2\n"
33	"bne- 1b\n"
34	"2:\n"
35	: "=&r" (prev), "+m" (*ptr)
36	: "r" (ptr), "r" (old_value), "r" (new_value)
37	: "cc", "memory");
38
39	return prev;
40	}
41
42	/*
43	* Atomic exchange
44	*
45	* Changes the memory location '*ptr' to be new_value and returns
46	* the previous value stored there.
47	*/
48	inline Atomic32 NoBarrier_AtomicExchange(volatile Atomic32* ptr,
49	Atomic32 new_value) {
50	Atomic32 prev;
51
52	__asm__ __volatile__(
53	"1: lwarx %0,0,%2 \n"
54	" stwcx. %3,0,%2 \n\
55	bne- 1b"
56	: "=&r" (prev), "+m" (*ptr)
57	: "r" (ptr), "r" (new_value)
58	: "cc", "memory");
59
60	return prev;
61	}
62
63	inline Atomic32 NoBarrier_AtomicIncrement(volatile Atomic32* ptr,
64	Atomic32 increment) {
65	Atomic32 temp;
66
67	__asm__ __volatile__(
68	"1: lwarx %0,0,%2\n\
69	add %0,%1,%0\n"
70	" stwcx. %0,0,%2 \n\
71	bne- 1b"
72	: "=&r" (temp)
73	: "r" (increment), "r" (ptr)
74	: "cc", "memory");
75
76	return temp;
77	}
78
79	inline Atomic32 Barrier_AtomicIncrement(volatile Atomic32* ptr,
80	Atomic32 increment) {
81	Atomic32 temp;
82
83	__asm__ __volatile__(
84	PPC_RELEASE_BARRIER
85	"1: lwarx %0,0,%2\n\
86	add %0,%1,%0\n"
87	" stwcx. %0,0,%2 \n\
88	bne- 1b"
89	PPC_ACQUIRE_BARRIER
90	: "=&r" (temp)
91	: "r" (increment), "r" (ptr)
92	: "cc", "memory");
93
94	return temp;
95	}
96
97	inline Atomic32 Acquire_CompareAndSwap(volatile Atomic32* ptr,
98	Atomic32 old_value,
99	Atomic32 new_value) {
100	return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
101	}
102
103	inline Atomic32 Release_CompareAndSwap(volatile Atomic32* ptr,
104	Atomic32 old_value,
105	Atomic32 new_value) {
106	return NoBarrier_CompareAndSwap(ptr, old_value, new_value);
107	}
108
109	inline void NoBarrier_Store(volatile Atomic32* ptr, Atomic32 value) {
110	*ptr = value;
111	}
112
113	inline void MemoryBarrier() {
114	__asm__ __volatile__("sync" : : : "memory");
115	}
116
117	inline void Acquire_Store(volatile Atomic32* ptr, Atomic32 value) {
118	*ptr = value;
119	MemoryBarrier();
120	}
121
122	inline void Release_Store(volatile Atomic32* ptr, Atomic32 value) {
123	MemoryBarrier();
124	*ptr = value;
125	}
126
127	inline Atomic32 NoBarrier_Load(volatile const Atomic32* ptr) {
128	return *ptr;
129	}
130
131	inline Atomic32 Acquire_Load(volatile const Atomic32* ptr) {
132	Atomic32 value = *ptr;
133	MemoryBarrier();
134	return value;
135
136	}
137
138	inline Atomic32 Release_Load(volatile const Atomic32* ptr) {
139	MemoryBarrier();
140	return *ptr;
141	}
142
143	} // namespace base::subtle
144	} // namespace base
145
146	#undef ATOMICOPS_COMPILER_BARRIER
147
148	#endif // BASE_ATOMICOPS_INTERNALS_PPC_GCC_H_