Go to:
Gentoo Home
Documentation
Forums
Lists
Bugs
Planet
Store
Wiki
Get Gentoo!
Gentoo's Bugzilla – Attachment 224705 Details for
Bug 309279
sys-devel/gcc-4.3.4 fails to build on alpha with PR42113 fix
Home
|
New
–
[Ex]
|
Browse
|
Search
|
Privacy Policy
|
[?]
|
Reports
|
Requests
|
Help
|
New Account
|
Log In
[x]
|
Forgot Password
Login:
[x]
[patch]
alpha.patch
patch.log (text/plain), 13.75 KB, created by
Raúl Porcel (RETIRED)
on 2010-03-22 16:30:50 UTC
(
hide
)
Description:
alpha.patch
Filename:
MIME Type:
Creator:
Raúl Porcel (RETIRED)
Created:
2010-03-22 16:30:50 UTC
Size:
13.75 KB
patch
obsolete
>Index: gcc/config/alpha/alpha.c >=================================================================== >--- gcc/config/alpha/alpha.c (revision 150465) >+++ gcc/config/alpha/alpha.c (revision 150466) >@@ -2051,11 +2051,22 @@ > > switch (GET_CODE (x)) > { >- case CONST: > case LABEL_REF: > case HIGH: > return true; > >+ case CONST: >+ if (GET_CODE (XEXP (x, 0)) == PLUS >+ && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) >+ x = XEXP (XEXP (x, 0), 0); >+ else >+ return true; >+ >+ if (GET_CODE (x) != SYMBOL_REF) >+ return true; >+ >+ /* FALLTHRU */ >+ > case SYMBOL_REF: > /* TLS symbols are never valid. */ > return SYMBOL_REF_TLS_MODEL (x) == 0; >@@ -3541,7 +3552,7 @@ > emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr)); > break; > case 8: >- emit_insn (gen_insql_le (insl, src, addr)); >+ emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr)); > break; > } > } >Index: gcc/config/alpha/alpha.md >=================================================================== >--- gcc/config/alpha/alpha.md (revision 150734) >+++ gcc/config/alpha/alpha.md (revision 150735) >@@ -255,16 +255,7 @@ > (sign_extend:DI (match_dup 1)))] > "") > >-;; Don't say we have addsi3 if optimizing. This generates better code. We >-;; have the anonymous addsi3 pattern below in case combine wants to make it. >-(define_expand "addsi3" >- [(set (match_operand:SI 0 "register_operand" "") >- (plus:SI (match_operand:SI 1 "reg_or_0_operand" "") >- (match_operand:SI 2 "add_operand" "")))] >- "! optimize" >- "") >- >-(define_insn "*addsi_internal" >+(define_insn "addsi3" > [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") > (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") > (match_operand:SI 2 "add_operand" "rI,O,K,L")))] >@@ -618,14 +609,7 @@ > "" > "subqv $31,%1,%0") > >-(define_expand "subsi3" >- [(set (match_operand:SI 0 "register_operand" "") >- (minus:SI (match_operand:SI 1 "reg_or_0_operand" "") >- (match_operand:SI 2 "reg_or_8bit_operand" "")))] >- "! optimize" >- "") >- >-(define_insn "*subsi_internal" >+(define_insn "subsi3" > [(set (match_operand:SI 0 "register_operand" "=r") > (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") > (match_operand:SI 2 "reg_or_8bit_operand" "rI")))] >Index: gcc/testsuite/lib/target-supports.exp >=================================================================== >--- gcc/testsuite/lib/target-supports.exp (revision 151159) >+++ gcc/testsuite/lib/target-supports.exp (revision 151160) >@@ -1086,7 +1086,8 @@ > verbose "check_effective_target_vect_cmdline_needed: using cached result" 2 > } else { > set et_vect_cmdline_needed_saved 1 >- if { [istarget ia64-*-*] >+ if { [istarget alpha*-*-*] >+ || [istarget ia64-*-*] > || (([istarget x86_64-*-*] || [istarget i?86-*-*]) > && [check_effective_target_lp64]) > || ([istarget powerpc*-*-*] >Index: gcc/config/alpha/alpha.c >=================================================================== >--- gcc/config/alpha/alpha.c (revision 151159) >+++ gcc/config/alpha/alpha.c (revision 151160) >@@ -8259,7 +8259,7 @@ > insn = get_last_insn (); > if (!INSN_P (insn)) > insn = prev_active_insn (insn); >- if (GET_CODE (insn) == CALL_INSN) >+ if (insn && GET_CODE (insn) == CALL_INSN) > output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL); > > #if TARGET_ABI_OSF >Index: gcc/config/alpha/sync.md >=================================================================== >--- gcc/config/alpha/sync.md (revision 151159) >+++ gcc/config/alpha/sync.md (revision 151160) >@@ -62,11 +62,8 @@ > [(set_attr "type" "st_c")]) > > ;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether >-;; the lock is cleared by a TAKEN branch. If we were to honor that, it >-;; would mean that we could not expand a ll/sc sequence until after the >-;; final basic-block reordering pass. Fortunately, it appears that no >-;; Alpha implementation ever built actually clears the lock on branches, >-;; taken or not. >+;; the lock is cleared by a TAKEN branch. This means that we can not >+;; expand a ll/sc sequence until after the final basic-block reordering pass. > > (define_insn_and_split "sync_<fetchop_name><mode>" > [(set (match_operand:I48MODE 0 "memory_operand" "+m") >@@ -77,7 +74,7 @@ > (clobber (match_scratch:I48MODE 2 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_atomic_op (<CODE>, operands[0], operands[1], >@@ -95,7 +92,7 @@ > (clobber (match_scratch:I48MODE 2 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_atomic_op (NOT, operands[0], operands[1], >@@ -115,7 +112,7 @@ > (clobber (match_scratch:I48MODE 3 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_atomic_op (<CODE>, operands[1], operands[2], >@@ -135,7 +132,7 @@ > (clobber (match_scratch:I48MODE 3 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_atomic_op (NOT, operands[1], operands[2], >@@ -156,7 +153,7 @@ > (clobber (match_scratch:I48MODE 3 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_atomic_op (<CODE>, operands[1], operands[2], >@@ -177,7 +174,7 @@ > (clobber (match_scratch:I48MODE 3 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_atomic_op (NOT, operands[1], operands[2], >@@ -212,7 +209,7 @@ > (clobber (match_scratch:DI 6 "=X,&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1], >@@ -249,7 +246,7 @@ > (clobber (match_scratch:I48MODE 4 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_compare_and_swap (operands[0], operands[1], operands[2], >@@ -280,7 +277,7 @@ > (clobber (match_scratch:DI 4 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1], >@@ -299,7 +296,7 @@ > (clobber (match_scratch:I48MODE 3 "=&r"))] > "" > "#" >- "reload_completed" >+ "epilogue_completed" > [(const_int 0)] > { > alpha_split_lock_test_and_set (operands[0], operands[1], >Index: gcc/config/alpha/alpha.md >=================================================================== >--- gcc/config/alpha/alpha.md (revision 151159) >+++ gcc/config/alpha/alpha.md (revision 151160) >@@ -3699,24 +3699,12 @@ > (match_operator:DF 1 "alpha_fp_comparison_operator" > [(match_operand:DF 2 "reg_or_0_operand" "fG") > (match_operand:DF 3 "reg_or_0_operand" "fG")]))] >- "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" >+ "TARGET_FP" > "cmp%-%C1%/ %R2,%R3,%0" > [(set_attr "type" "fadd") > (set_attr "trap" "yes") > (set_attr "trap_suffix" "su")]) > >-(define_insn "*cmpdf_ieee_ext1" >- [(set (match_operand:DF 0 "register_operand" "=&f") >- (match_operator:DF 1 "alpha_fp_comparison_operator" >- [(float_extend:DF >- (match_operand:SF 2 "reg_or_0_operand" "fG")) >- (match_operand:DF 3 "reg_or_0_operand" "fG")]))] >- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" >- "cmp%-%C1%/ %R2,%R3,%0" >- [(set_attr "type" "fadd") >- (set_attr "trap" "yes") >- (set_attr "trap_suffix" "su")]) >- > (define_insn "*cmpdf_ext1" > [(set (match_operand:DF 0 "register_operand" "=f") > (match_operator:DF 1 "alpha_fp_comparison_operator" >@@ -3729,18 +3717,6 @@ > (set_attr "trap" "yes") > (set_attr "trap_suffix" "su")]) > >-(define_insn "*cmpdf_ieee_ext2" >- [(set (match_operand:DF 0 "register_operand" "=&f") >- (match_operator:DF 1 "alpha_fp_comparison_operator" >- [(match_operand:DF 2 "reg_or_0_operand" "fG") >- (float_extend:DF >- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] >- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" >- "cmp%-%C1%/ %R2,%R3,%0" >- [(set_attr "type" "fadd") >- (set_attr "trap" "yes") >- (set_attr "trap_suffix" "su")]) >- > (define_insn "*cmpdf_ext2" > [(set (match_operand:DF 0 "register_operand" "=f") > (match_operator:DF 1 "alpha_fp_comparison_operator" >@@ -3753,19 +3729,6 @@ > (set_attr "trap" "yes") > (set_attr "trap_suffix" "su")]) > >-(define_insn "*cmpdf_ieee_ext3" >- [(set (match_operand:DF 0 "register_operand" "=&f") >- (match_operator:DF 1 "alpha_fp_comparison_operator" >- [(float_extend:DF >- (match_operand:SF 2 "reg_or_0_operand" "fG")) >- (float_extend:DF >- (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] >- "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" >- "cmp%-%C1%/ %R2,%R3,%0" >- [(set_attr "type" "fadd") >- (set_attr "trap" "yes") >- (set_attr "trap_suffix" "su")]) >- > (define_insn "*cmpdf_ext3" > [(set (match_operand:DF 0 "register_operand" "=f") > (match_operator:DF 1 "alpha_fp_comparison_operator" >@@ -3815,7 +3778,7 @@ > (match_operand:DF 2 "const0_operand" "G,G")]) > (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) > (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] >- "TARGET_FP" >+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" > "@ > fcmov%C3 %R4,%R1,%0 > fcmov%D3 %R4,%R5,%0" >@@ -3830,7 +3793,7 @@ > (match_operand:DF 2 "const0_operand" "G,G")]) > (match_operand:DF 1 "reg_or_0_operand" "fG,0") > (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] >- "TARGET_FP" >+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" > "@ > fcmov%C3 %R4,%R1,%0 > fcmov%D3 %R4,%R5,%0" >@@ -3845,7 +3808,7 @@ > (match_operand:DF 2 "const0_operand" "G,G")]) > (match_operand:SF 1 "reg_or_0_operand" "fG,0") > (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] >- "TARGET_FP" >+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" > "@ > fcmov%C3 %R4,%R1,%0 > fcmov%D3 %R4,%R5,%0" >@@ -3860,7 +3823,7 @@ > (match_operand:DF 2 "const0_operand" "G,G")]) > (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) > (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] >- "TARGET_FP" >+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" > "@ > fcmov%C3 %R4,%R1,%0 > fcmov%D3 %R4,%R5,%0" >Index: gcc/config/alpha/alpha.md >=================================================================== >--- gcc/config/alpha/alpha.md (revision 151709) >+++ gcc/config/alpha/alpha.md (revision 151710) >@@ -3862,7 +3862,7 @@ > (set (match_operand:SF 0 "register_operand" "") > (if_then_else:SF (eq (match_dup 3) (match_dup 4)) > (match_dup 1) (match_dup 2)))] >- "TARGET_FP" >+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" > { > operands[3] = gen_reg_rtx (DFmode); > operands[4] = CONST0_RTX (DFmode); >@@ -3875,7 +3875,7 @@ > (set (match_operand:SF 0 "register_operand" "") > (if_then_else:SF (ne (match_dup 3) (match_dup 4)) > (match_dup 1) (match_dup 2)))] >- "TARGET_FP" >+ "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" > { > operands[3] = gen_reg_rtx (DFmode); > operands[4] = CONST0_RTX (DFmode); >Index: gcc/testsuite/gcc.target/alpha/pr22093.c >=================================================================== >--- gcc/testsuite/gcc.target/alpha/pr22093.c (revision 0) >+++ gcc/testsuite/gcc.target/alpha/pr22093.c (revision 152344) >@@ -0,0 +1,14 @@ >+/* { dg-do compile } */ >+/* { dg-options "-O2" } */ >+ >+struct shared_ptr_struct >+{ >+ unsigned long phase : 48; >+ unsigned thread : 16; >+ void *addr; >+} x; >+ >+void foo (void) >+{ >+ x.thread = 2; >+} >Index: gcc/config/alpha/alpha.md >=================================================================== >--- gcc/config/alpha/alpha.md (revision 152343) >+++ gcc/config/alpha/alpha.md (revision 152344) >@@ -5998,7 +5998,7 @@ > (mem:DI (and:DI (match_operand:DI 0 "address_operand" "") > (const_int -8)))) > (set (match_operand:DI 2 "register_operand" "") >- (plus:DI (match_dup 0) (const_int 1))) >+ (plus:DI (match_dup 5) (const_int 1))) > (set (match_dup 3) > (and:DI (not:DI (ashift:DI > (const_int 65535) >@@ -6013,7 +6013,7 @@ > (set (mem:DI (and:DI (match_dup 0) (const_int -8))) > (match_dup 4))] > "WORDS_BIG_ENDIAN" >- "") >+ "operands[5] = force_reg (DImode, operands[0]);") > > ;; Here are the define_expand's for QI and HI moves that use the above > ;; patterns. We have the normal sets, plus the ones that need scratch >Index: gcc/testsuite/gcc.target/alpha/pr42113.c >=================================================================== >--- gcc/testsuite/gcc.target/alpha/pr42113.c (revision 0) >+++ gcc/testsuite/gcc.target/alpha/pr42113.c (revision 154465) >@@ -0,0 +1,12 @@ >+/* { dg-do compile } */ >+/* { dg-options "-O2" } */ >+ >+int foo (int a, int b) >+{ >+ int bar = a * sizeof (int); >+ >+ if (b) >+ bar += sizeof (int); >+ >+ return bar; >+} >Index: gcc/config/alpha/alpha.md >=================================================================== >--- gcc/config/alpha/alpha.md (revision 154464) >+++ gcc/config/alpha/alpha.md (revision 154465) >@@ -4349,7 +4349,7 @@ > (match_dup 4)))] > { > if (can_create_pseudo_p ()) >- operands[5] = gen_reg_rtx (DImode); >+ operands[5] = gen_reg_rtx (SImode); > else if (reg_overlap_mentioned_p (operands[5], operands[4])) > operands[5] = operands[0]; > }) >@@ -4375,9 +4375,9 @@ > (match_dup 4))))] > { > if (can_create_pseudo_p ()) >- operands[5] = gen_reg_rtx (DImode); >+ operands[5] = gen_reg_rtx (SImode); > else if (reg_overlap_mentioned_p (operands[5], operands[4])) >- operands[5] = operands[0]; >+ operands[5] = gen_lowpart (SImode, operands[0]); > }) > > (define_insn_and_split "*cmp_ssub_di" >@@ -4425,7 +4425,7 @@ > (match_dup 4)))] > { > if (can_create_pseudo_p ()) >- operands[5] = gen_reg_rtx (DImode); >+ operands[5] = gen_reg_rtx (SImode); > else if (reg_overlap_mentioned_p (operands[5], operands[4])) > operands[5] = operands[0]; > }) >@@ -4451,9 +4451,9 @@ > (match_dup 4))))] > { > if (can_create_pseudo_p ()) >- operands[5] = gen_reg_rtx (DImode); >+ operands[5] = gen_reg_rtx (SImode); > else if (reg_overlap_mentioned_p (operands[5], operands[4])) >- operands[5] = operands[0]; >+ operands[5] = gen_lowpart (SImode, operands[0]); > }) > > ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
You cannot view the attachment while viewing its details because your browser does not support IFRAMEs.
View the attachment on a separate page
.
View Attachment As Diff
View Attachment As Raw
Actions:
View
|
Diff
Attachments on
bug 309279
:
223429
| 224705 |
224941