Attachment #224705 for bug #309279

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  switch (GET_CODE (x))
    {
    case CONST:
    case LABEL_REF:
    case HIGH:
      return true;

    case CONST:
      if (GET_CODE (XEXP (x, 0)) == PLUS
	  && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
	x = XEXP (XEXP (x, 0), 0);
      else
	return true;

      if (GET_CODE (x) != SYMBOL_REF)
	return true;

      /* FALLTHRU */

    case SYMBOL_REF:
      /* TLS symbols are never valid.  */
      return SYMBOL_REF_TLS_MODEL (x) == 0;

	      emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
	      break;
	    case 8:
	      emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr));
	      break;
	    }
	}




	(sign_extend:DI (match_dup 1)))]
  "")

(define_insn "addsi3"
;; have the anonymous addsi3 pattern below in case combine wants to make it.
(define_expand "addsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
		 (match_operand:SI 2 "add_operand" "")))]
  "! optimize"
  "")

(define_insn "*addsi_internal"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
		 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]

  ""
  "subqv $31,%1,%0")

(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
		  (match_operand:SI 2 "reg_or_8bit_operand" "")))]
  "! optimize"
  "")

(define_insn "*subsi_internal"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
		  (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]

Lines 1086-1092 Link Here

(-)gcc/testsuite/lib/target-supports.exp (-1 / +2 lines)
1086	verbose "check_effective_target_vect_cmdline_needed: using cached result" 2	1086	verbose "check_effective_target_vect_cmdline_needed: using cached result" 2
1087	} else {	1087	} else {
1088	set et_vect_cmdline_needed_saved 1	1088	set et_vect_cmdline_needed_saved 1
1089	if { [istarget ia64--]	1089	if { [istarget alpha--*]
		1090	\|\| [istarget ia64--]
1090	\|\| (([istarget x86_64--] \|\| [istarget i?86--])	1091	\|\| (([istarget x86_64--] \|\| [istarget i?86--])
1091	&& [check_effective_target_lp64])	1092	&& [check_effective_target_lp64])
1092	\|\| ([istarget powerpc--*]	1093	\|\| ([istarget powerpc--*]

Lines 8259-8265 Link Here

(-)gcc/config/alpha/alpha.c (-1 / +1 lines)
8259	insn = get_last_insn ();	8259	insn = get_last_insn ();
8260	if (!INSN_P (insn))	8260	if (!INSN_P (insn))
8261	insn = prev_active_insn (insn);	8261	insn = prev_active_insn (insn);
8262	if (GET_CODE (insn) == CALL_INSN)	8262	if (insn && GET_CODE (insn) == CALL_INSN)
8263	output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL);	8263	output_asm_insn (get_insn_template (CODE_FOR_nop, NULL), NULL);
8264		8264
8265	#if TARGET_ABI_OSF	8265	#if TARGET_ABI_OSF




  [(set_attr "type" "st_c")])

;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
;; the lock is cleared by a TAKEN branch.  This means that we can not
;; expand a ll/sc sequence until after the final basic-block reordering pass.
;; final basic-block reordering pass.  Fortunately, it appears that no
;; Alpha implementation ever built actually clears the lock on branches,
;; taken or not.

(define_insn_and_split "sync_<fetchop_name><mode>"
  [(set (match_operand:I48MODE 0 "memory_operand" "+m")

   (clobber (match_scratch:I48MODE 2 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_atomic_op (<CODE>, operands[0], operands[1],

   (clobber (match_scratch:I48MODE 2 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_atomic_op (NOT, operands[0], operands[1],

   (clobber (match_scratch:I48MODE 3 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_atomic_op (<CODE>, operands[1], operands[2],

   (clobber (match_scratch:I48MODE 3 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_atomic_op (NOT, operands[1], operands[2],

   (clobber (match_scratch:I48MODE 3 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_atomic_op (<CODE>, operands[1], operands[2],

   (clobber (match_scratch:I48MODE 3 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_atomic_op (NOT, operands[1], operands[2],

   (clobber (match_scratch:DI 6 "=X,&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],

   (clobber (match_scratch:I48MODE 4 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_compare_and_swap (operands[0], operands[1], operands[2],

   (clobber (match_scratch:DI 4 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],

   (clobber (match_scratch:I48MODE 3 "=&r"))]
  ""
  "#"
  "epilogue_completed"
  [(const_int 0)]
{
  alpha_split_lock_test_and_set (operands[0], operands[1],




	(match_operator:DF 1 "alpha_fp_comparison_operator"
			   [(match_operand:DF 2 "reg_or_0_operand" "fG")
			    (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
  "TARGET_FP"
  "cmp%-%C1%/ %R2,%R3,%0"
  [(set_attr "type" "fadd")
   (set_attr "trap" "yes")
   (set_attr "trap_suffix" "su")])

(define_insn "*cmpdf_ieee_ext1"
  [(set (match_operand:DF 0 "register_operand" "=&f")
	(match_operator:DF 1 "alpha_fp_comparison_operator"
			   [(float_extend:DF
			     (match_operand:SF 2 "reg_or_0_operand" "fG"))
			    (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
  "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
  "cmp%-%C1%/ %R2,%R3,%0"
  [(set_attr "type" "fadd")
   (set_attr "trap" "yes")
   (set_attr "trap_suffix" "su")])

(define_insn "*cmpdf_ext1"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(match_operator:DF 1 "alpha_fp_comparison_operator"

   (set_attr "trap" "yes")
   (set_attr "trap_suffix" "su")])

(define_insn "*cmpdf_ieee_ext2"
  [(set (match_operand:DF 0 "register_operand" "=&f")
	(match_operator:DF 1 "alpha_fp_comparison_operator"
			   [(match_operand:DF 2 "reg_or_0_operand" "fG")
			    (float_extend:DF
			     (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
  "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
  "cmp%-%C1%/ %R2,%R3,%0"
  [(set_attr "type" "fadd")
   (set_attr "trap" "yes")
   (set_attr "trap_suffix" "su")])

(define_insn "*cmpdf_ext2"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(match_operator:DF 1 "alpha_fp_comparison_operator"

   (set_attr "trap" "yes")
   (set_attr "trap_suffix" "su")])

(define_insn "*cmpdf_ieee_ext3"
  [(set (match_operand:DF 0 "register_operand" "=&f")
	(match_operator:DF 1 "alpha_fp_comparison_operator"
			   [(float_extend:DF
			     (match_operand:SF 2 "reg_or_0_operand" "fG"))
			    (float_extend:DF
			     (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
  "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
  "cmp%-%C1%/ %R2,%R3,%0"
  [(set_attr "type" "fadd")
   (set_attr "trap" "yes")
   (set_attr "trap_suffix" "su")])

(define_insn "*cmpdf_ext3"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(match_operator:DF 1 "alpha_fp_comparison_operator"

			  (match_operand:DF 2 "const0_operand" "G,G")])
	 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
  "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
  "@
   fcmov%C3 %R4,%R1,%0
   fcmov%D3 %R4,%R5,%0"

			  (match_operand:DF 2 "const0_operand" "G,G")])
	 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
  "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
  "@
   fcmov%C3 %R4,%R1,%0
   fcmov%D3 %R4,%R5,%0"

			  (match_operand:DF 2 "const0_operand" "G,G")])
	 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
	 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
  "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
  "@
   fcmov%C3 %R4,%R1,%0
   fcmov%D3 %R4,%R5,%0"

			  (match_operand:DF 2 "const0_operand" "G,G")])
	 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
	 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
  "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
  "@
   fcmov%C3 %R4,%R1,%0
   fcmov%D3 %R4,%R5,%0"

Lines 3862-3868 Link Here

(-)gcc/config/alpha/alpha.md (-2 / +2 lines)
3862	(set (match_operand:SF 0 "register_operand" "")	3862	(set (match_operand:SF 0 "register_operand" "")
3863	(if_then_else:SF (eq (match_dup 3) (match_dup 4))	3863	(if_then_else:SF (eq (match_dup 3) (match_dup 4))
3864	(match_dup 1) (match_dup 2)))]	3864	(match_dup 1) (match_dup 2)))]
3865	"TARGET_FP"	3865	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3866	{	3866	{
3867	operands[3] = gen_reg_rtx (DFmode);	3867	operands[3] = gen_reg_rtx (DFmode);
3868	operands[4] = CONST0_RTX (DFmode);	3868	operands[4] = CONST0_RTX (DFmode);
Lines 3875-3881 Link Here
3875	(set (match_operand:SF 0 "register_operand" "")	3875	(set (match_operand:SF 0 "register_operand" "")
3876	(if_then_else:SF (ne (match_dup 3) (match_dup 4))	3876	(if_then_else:SF (ne (match_dup 3) (match_dup 4))
3877	(match_dup 1) (match_dup 2)))]	3877	(match_dup 1) (match_dup 2)))]
3878	"TARGET_FP"	3878	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3879	{	3879	{
3880	operands[3] = gen_reg_rtx (DFmode);	3880	operands[3] = gen_reg_rtx (DFmode);
3881	operands[4] = CONST0_RTX (DFmode);	3881	operands[4] = CONST0_RTX (DFmode);




/* { dg-do compile } */
/* { dg-options "-O2" } */

struct shared_ptr_struct
{
  unsigned long phase : 48;
  unsigned thread : 16;
  void *addr;
} x;

void foo (void)
{
   x.thread = 2;
}

Lines 5998-6004 Link Here

(-)gcc/config/alpha/alpha.md (-2 / +2 lines)
5998	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")	5998	(mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5999	(const_int -8))))	5999	(const_int -8))))
6000	(set (match_operand:DI 2 "register_operand" "")	6000	(set (match_operand:DI 2 "register_operand" "")
6001	(plus:DI (match_dup 0) (const_int 1)))	6001	(plus:DI (match_dup 5) (const_int 1)))
6002	(set (match_dup 3)	6002	(set (match_dup 3)
6003	(and:DI (not:DI (ashift:DI	6003	(and:DI (not:DI (ashift:DI
6004	(const_int 65535)	6004	(const_int 65535)
Lines 6013-6019 Link Here
6013	(set (mem:DI (and:DI (match_dup 0) (const_int -8)))	6013	(set (mem:DI (and:DI (match_dup 0) (const_int -8)))
6014	(match_dup 4))]	6014	(match_dup 4))]
6015	"WORDS_BIG_ENDIAN"	6015	"WORDS_BIG_ENDIAN"
6016	"")	6016	"operands[5] = force_reg (DImode, operands[0]);")
6017		6017
6018	;; Here are the define_expand's for QI and HI moves that use the above	6018	;; Here are the define_expand's for QI and HI moves that use the above
6019	;; patterns. We have the normal sets, plus the ones that need scratch	6019	;; patterns. We have the normal sets, plus the ones that need scratch




/* { dg-do compile } */
/* { dg-options "-O2" } */

int foo (int a, int b)
{
  int bar = a * sizeof (int);

  if (b)
    bar += sizeof (int);

  return bar;
}




		 (match_dup 4)))]
{
  if (can_create_pseudo_p ())
    operands[5] = gen_reg_rtx (SImode);
  else if (reg_overlap_mentioned_p (operands[5], operands[4]))
    operands[5] = operands[0];
})

				 (match_dup 4))))]
{
  if (can_create_pseudo_p ())
    operands[5] = gen_reg_rtx (SImode);
  else if (reg_overlap_mentioned_p (operands[5], operands[4]))
    operands[5] = gen_lowpart (SImode, operands[0]);
})

(define_insn_and_split "*cmp_ssub_di"

		 (match_dup 4)))]
{
  if (can_create_pseudo_p ())
    operands[5] = gen_reg_rtx (SImode);
  else if (reg_overlap_mentioned_p (operands[5], operands[4]))
    operands[5] = operands[0];
})

				  (match_dup 4))))]
{
  if (can_create_pseudo_p ())
    operands[5] = gen_reg_rtx (SImode);
  else if (reg_overlap_mentioned_p (operands[5], operands[4]))
    operands[5] = gen_lowpart (SImode, operands[0]);
})

;; Here are the CALL and unconditional branch insns.  Calls on NT and OSF

Return to bug 309279

Lines 2051-2061 Link Here

(-)gcc/config/alpha/alpha.c (-2 / +13 lines)
2051		2051
2052	switch (GET_CODE (x))	2052	switch (GET_CODE (x))
2053	{	2053	{
2054	case CONST:
2055	case LABEL_REF:	2054	case LABEL_REF:
2056	case HIGH:	2055	case HIGH:
2057	return true;	2056	return true;
2058		2057
		2058	case CONST:
		2059	if (GET_CODE (XEXP (x, 0)) == PLUS
		2060	&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
		2061	x = XEXP (XEXP (x, 0), 0);
		2062	else
		2063	return true;
		2064
		2065	if (GET_CODE (x) != SYMBOL_REF)
		2066	return true;
		2067
		2068	/* FALLTHRU */
		2069
2059	case SYMBOL_REF:	2070	case SYMBOL_REF:
2060	/* TLS symbols are never valid. */	2071	/* TLS symbols are never valid. */
2061	return SYMBOL_REF_TLS_MODEL (x) == 0;	2072	return SYMBOL_REF_TLS_MODEL (x) == 0;
Lines 3541-3547 Link Here
3541	emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));	3552	emit_insn (gen_insll_le (insl, gen_lowpart (SImode, src), addr));
3542	break;	3553	break;
3543	case 8:	3554	case 8:
3544	emit_insn (gen_insql_le (insl, src, addr));	3555	emit_insn (gen_insql_le (insl, gen_lowpart (DImode, src), addr));
3545	break;	3556	break;
3546	}	3557	}
3547	}	3558	}

Lines 3699-3722 Link Here

(-)gcc/config/alpha/alpha.md (-42 / +5 lines)
3699	(match_operator:DF 1 "alpha_fp_comparison_operator"	3699	(match_operator:DF 1 "alpha_fp_comparison_operator"
3700	[(match_operand:DF 2 "reg_or_0_operand" "fG")	3700	[(match_operand:DF 2 "reg_or_0_operand" "fG")
3701	(match_operand:DF 3 "reg_or_0_operand" "fG")]))]	3701	(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3702	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"	3702	"TARGET_FP"
3703	"cmp%-%C1%/ %R2,%R3,%0"	3703	"cmp%-%C1%/ %R2,%R3,%0"
3704	[(set_attr "type" "fadd")	3704	[(set_attr "type" "fadd")
3705	(set_attr "trap" "yes")	3705	(set_attr "trap" "yes")
3706	(set_attr "trap_suffix" "su")])	3706	(set_attr "trap_suffix" "su")])
3707		3707
3708	(define_insn "*cmpdf_ieee_ext1"
3709	[(set (match_operand:DF 0 "register_operand" "=&f")
3710	(match_operator:DF 1 "alpha_fp_comparison_operator"
3711	[(float_extend:DF
3712	(match_operand:SF 2 "reg_or_0_operand" "fG"))
3713	(match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3714	"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3715	"cmp%-%C1%/ %R2,%R3,%0"
3716	[(set_attr "type" "fadd")
3717	(set_attr "trap" "yes")
3718	(set_attr "trap_suffix" "su")])
3719
3720	(define_insn "*cmpdf_ext1"	3708	(define_insn "*cmpdf_ext1"
3721	[(set (match_operand:DF 0 "register_operand" "=f")	3709	[(set (match_operand:DF 0 "register_operand" "=f")
3722	(match_operator:DF 1 "alpha_fp_comparison_operator"	3710	(match_operator:DF 1 "alpha_fp_comparison_operator"
Lines 3729-3746 Link Here
3729	(set_attr "trap" "yes")	3717	(set_attr "trap" "yes")
3730	(set_attr "trap_suffix" "su")])	3718	(set_attr "trap_suffix" "su")])
3731		3719
3732	(define_insn "*cmpdf_ieee_ext2"
3733	[(set (match_operand:DF 0 "register_operand" "=&f")
3734	(match_operator:DF 1 "alpha_fp_comparison_operator"
3735	[(match_operand:DF 2 "reg_or_0_operand" "fG")
3736	(float_extend:DF
3737	(match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3738	"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3739	"cmp%-%C1%/ %R2,%R3,%0"
3740	[(set_attr "type" "fadd")
3741	(set_attr "trap" "yes")
3742	(set_attr "trap_suffix" "su")])
3743
3744	(define_insn "*cmpdf_ext2"	3720	(define_insn "*cmpdf_ext2"
3745	[(set (match_operand:DF 0 "register_operand" "=f")	3721	[(set (match_operand:DF 0 "register_operand" "=f")
3746	(match_operator:DF 1 "alpha_fp_comparison_operator"	3722	(match_operator:DF 1 "alpha_fp_comparison_operator"
Lines 3753-3771 Link Here
3753	(set_attr "trap" "yes")	3729	(set_attr "trap" "yes")
3754	(set_attr "trap_suffix" "su")])	3730	(set_attr "trap_suffix" "su")])
3755		3731
3756	(define_insn "*cmpdf_ieee_ext3"
3757	[(set (match_operand:DF 0 "register_operand" "=&f")
3758	(match_operator:DF 1 "alpha_fp_comparison_operator"
3759	[(float_extend:DF
3760	(match_operand:SF 2 "reg_or_0_operand" "fG"))
3761	(float_extend:DF
3762	(match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3763	"TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3764	"cmp%-%C1%/ %R2,%R3,%0"
3765	[(set_attr "type" "fadd")
3766	(set_attr "trap" "yes")
3767	(set_attr "trap_suffix" "su")])
3768
3769	(define_insn "*cmpdf_ext3"	3732	(define_insn "*cmpdf_ext3"
3770	[(set (match_operand:DF 0 "register_operand" "=f")	3733	[(set (match_operand:DF 0 "register_operand" "=f")
3771	(match_operator:DF 1 "alpha_fp_comparison_operator"	3734	(match_operator:DF 1 "alpha_fp_comparison_operator"
Lines 3815-3821 Link Here
3815	(match_operand:DF 2 "const0_operand" "G,G")])	3778	(match_operand:DF 2 "const0_operand" "G,G")])
3816	(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))	3779	(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3817	(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]	3780	(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3818	"TARGET_FP"	3781	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3819	"@	3782	"@
3820	fcmov%C3 %R4,%R1,%0	3783	fcmov%C3 %R4,%R1,%0
3821	fcmov%D3 %R4,%R5,%0"	3784	fcmov%D3 %R4,%R5,%0"
Lines 3830-3836 Link Here
3830	(match_operand:DF 2 "const0_operand" "G,G")])	3793	(match_operand:DF 2 "const0_operand" "G,G")])
3831	(match_operand:DF 1 "reg_or_0_operand" "fG,0")	3794	(match_operand:DF 1 "reg_or_0_operand" "fG,0")
3832	(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]	3795	(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3833	"TARGET_FP"	3796	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3834	"@	3797	"@
3835	fcmov%C3 %R4,%R1,%0	3798	fcmov%C3 %R4,%R1,%0
3836	fcmov%D3 %R4,%R5,%0"	3799	fcmov%D3 %R4,%R5,%0"
Lines 3845-3851 Link Here
3845	(match_operand:DF 2 "const0_operand" "G,G")])	3808	(match_operand:DF 2 "const0_operand" "G,G")])
3846	(match_operand:SF 1 "reg_or_0_operand" "fG,0")	3809	(match_operand:SF 1 "reg_or_0_operand" "fG,0")
3847	(match_operand:SF 5 "reg_or_0_operand" "0,fG")))]	3810	(match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3848	"TARGET_FP"	3811	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3849	"@	3812	"@
3850	fcmov%C3 %R4,%R1,%0	3813	fcmov%C3 %R4,%R1,%0
3851	fcmov%D3 %R4,%R5,%0"	3814	fcmov%D3 %R4,%R5,%0"
Lines 3860-3866 Link Here
3860	(match_operand:DF 2 "const0_operand" "G,G")])	3823	(match_operand:DF 2 "const0_operand" "G,G")])
3861	(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))	3824	(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3862	(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]	3825	(match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3863	"TARGET_FP"	3826	"TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3864	"@	3827	"@
3865	fcmov%C3 %R4,%R1,%0	3828	fcmov%C3 %R4,%R1,%0
3866	fcmov%D3 %R4,%R5,%0"	3829	fcmov%D3 %R4,%R5,%0"

Lines 4349-4355 Link Here

(-)gcc/config/alpha/alpha.md (-6 / +6 lines)
4349	(match_dup 4)))]	4349	(match_dup 4)))]
4350	{	4350	{
4351	if (can_create_pseudo_p ())	4351	if (can_create_pseudo_p ())
4352	operands[5] = gen_reg_rtx (DImode);	4352	operands[5] = gen_reg_rtx (SImode);
4353	else if (reg_overlap_mentioned_p (operands[5], operands[4]))	4353	else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4354	operands[5] = operands[0];	4354	operands[5] = operands[0];
4355	})	4355	})
Lines 4375-4383 Link Here
4375	(match_dup 4))))]	4375	(match_dup 4))))]
4376	{	4376	{
4377	if (can_create_pseudo_p ())	4377	if (can_create_pseudo_p ())
4378	operands[5] = gen_reg_rtx (DImode);	4378	operands[5] = gen_reg_rtx (SImode);
4379	else if (reg_overlap_mentioned_p (operands[5], operands[4]))	4379	else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4380	operands[5] = operands[0];	4380	operands[5] = gen_lowpart (SImode, operands[0]);
4381	})	4381	})
4382		4382
4383	(define_insn_and_split "*cmp_ssub_di"	4383	(define_insn_and_split "*cmp_ssub_di"
Lines 4425-4431 Link Here
4425	(match_dup 4)))]	4425	(match_dup 4)))]
4426	{	4426	{
4427	if (can_create_pseudo_p ())	4427	if (can_create_pseudo_p ())
4428	operands[5] = gen_reg_rtx (DImode);	4428	operands[5] = gen_reg_rtx (SImode);
4429	else if (reg_overlap_mentioned_p (operands[5], operands[4]))	4429	else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4430	operands[5] = operands[0];	4430	operands[5] = operands[0];
4431	})	4431	})
Lines 4451-4459 Link Here
4451	(match_dup 4))))]	4451	(match_dup 4))))]
4452	{	4452	{
4453	if (can_create_pseudo_p ())	4453	if (can_create_pseudo_p ())
4454	operands[5] = gen_reg_rtx (DImode);	4454	operands[5] = gen_reg_rtx (SImode);
4455	else if (reg_overlap_mentioned_p (operands[5], operands[4]))	4455	else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4456	operands[5] = operands[0];	4456	operands[5] = gen_lowpart (SImode, operands[0]);
4457	})	4457	})
4458		4458
4459	;; Here are the CALL and unconditional branch insns. Calls on NT and OSF	4459	;; Here are the CALL and unconditional branch insns. Calls on NT and OSF

Lines 255-270 Link Here

(-)gcc/config/alpha/alpha.md (-18 / +2 lines)
255	(sign_extend:DI (match_dup 1)))]	255	(sign_extend:DI (match_dup 1)))]
256	"")	256	"")
257		257
258	;; Don't say we have addsi3 if optimizing. This generates better code. We	258	(define_insn "addsi3"
259	;; have the anonymous addsi3 pattern below in case combine wants to make it.
260	(define_expand "addsi3"
261	[(set (match_operand:SI 0 "register_operand" "")
262	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
263	(match_operand:SI 2 "add_operand" "")))]
264	"! optimize"
265	"")
266
267	(define_insn "*addsi_internal"
268	[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")	259	[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
269	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")	260	(plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
270	(match_operand:SI 2 "add_operand" "rI,O,K,L")))]	261	(match_operand:SI 2 "add_operand" "rI,O,K,L")))]
Lines 618-631 Link Here
618	""	609	""
619	"subqv $31,%1,%0")	610	"subqv $31,%1,%0")
620		611
621	(define_expand "subsi3"	612	(define_insn "subsi3"
622	[(set (match_operand:SI 0 "register_operand" "")
623	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
624	(match_operand:SI 2 "reg_or_8bit_operand" "")))]
625	"! optimize"
626	"")
627
628	(define_insn "*subsi_internal"
629	[(set (match_operand:SI 0 "register_operand" "=r")	613	[(set (match_operand:SI 0 "register_operand" "=r")
630	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")	614	(minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
631	(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]	615	(match_operand:SI 2 "reg_or_8bit_operand" "rI")))]

Lines 62-72 Link Here

(-)gcc/config/alpha/sync.md (-15 / +12 lines)
62	[(set_attr "type" "st_c")])	62	[(set_attr "type" "st_c")])
63		63
64	;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether	64	;; The Alpha Architecture Handbook says that it is UNPREDICTABLE whether
65	;; the lock is cleared by a TAKEN branch. If we were to honor that, it	65	;; the lock is cleared by a TAKEN branch. This means that we can not
66	;; would mean that we could not expand a ll/sc sequence until after the	66	;; expand a ll/sc sequence until after the final basic-block reordering pass.
67	;; final basic-block reordering pass. Fortunately, it appears that no
68	;; Alpha implementation ever built actually clears the lock on branches,
69	;; taken or not.
70		67
71	(define_insn_and_split "sync_<fetchop_name><mode>"	68	(define_insn_and_split "sync_<fetchop_name><mode>"
72	[(set (match_operand:I48MODE 0 "memory_operand" "+m")	69	[(set (match_operand:I48MODE 0 "memory_operand" "+m")
Lines 77-83 Link Here
77	(clobber (match_scratch:I48MODE 2 "=&r"))]	74	(clobber (match_scratch:I48MODE 2 "=&r"))]
78	""	75	""
79	"#"	76	"#"
80	"reload_completed"	77	"epilogue_completed"
81	[(const_int 0)]	78	[(const_int 0)]
82	{	79	{
83	alpha_split_atomic_op (<CODE>, operands[0], operands[1],	80	alpha_split_atomic_op (<CODE>, operands[0], operands[1],
Lines 95-101 Link Here
95	(clobber (match_scratch:I48MODE 2 "=&r"))]	92	(clobber (match_scratch:I48MODE 2 "=&r"))]
96	""	93	""
97	"#"	94	"#"
98	"reload_completed"	95	"epilogue_completed"
99	[(const_int 0)]	96	[(const_int 0)]
100	{	97	{
101	alpha_split_atomic_op (NOT, operands[0], operands[1],	98	alpha_split_atomic_op (NOT, operands[0], operands[1],
Lines 115-121 Link Here
115	(clobber (match_scratch:I48MODE 3 "=&r"))]	112	(clobber (match_scratch:I48MODE 3 "=&r"))]
116	""	113	""
117	"#"	114	"#"
118	"reload_completed"	115	"epilogue_completed"
119	[(const_int 0)]	116	[(const_int 0)]
120	{	117	{
121	alpha_split_atomic_op (<CODE>, operands[1], operands[2],	118	alpha_split_atomic_op (<CODE>, operands[1], operands[2],
Lines 135-141 Link Here
135	(clobber (match_scratch:I48MODE 3 "=&r"))]	132	(clobber (match_scratch:I48MODE 3 "=&r"))]
136	""	133	""
137	"#"	134	"#"
138	"reload_completed"	135	"epilogue_completed"
139	[(const_int 0)]	136	[(const_int 0)]
140	{	137	{
141	alpha_split_atomic_op (NOT, operands[1], operands[2],	138	alpha_split_atomic_op (NOT, operands[1], operands[2],
Lines 156-162 Link Here
156	(clobber (match_scratch:I48MODE 3 "=&r"))]	153	(clobber (match_scratch:I48MODE 3 "=&r"))]
157	""	154	""
158	"#"	155	"#"
159	"reload_completed"	156	"epilogue_completed"
160	[(const_int 0)]	157	[(const_int 0)]
161	{	158	{
162	alpha_split_atomic_op (<CODE>, operands[1], operands[2],	159	alpha_split_atomic_op (<CODE>, operands[1], operands[2],
Lines 177-183 Link Here
177	(clobber (match_scratch:I48MODE 3 "=&r"))]	174	(clobber (match_scratch:I48MODE 3 "=&r"))]
178	""	175	""
179	"#"	176	"#"
180	"reload_completed"	177	"epilogue_completed"
181	[(const_int 0)]	178	[(const_int 0)]
182	{	179	{
183	alpha_split_atomic_op (NOT, operands[1], operands[2],	180	alpha_split_atomic_op (NOT, operands[1], operands[2],
Lines 212-218 Link Here
212	(clobber (match_scratch:DI 6 "=X,&r"))]	209	(clobber (match_scratch:DI 6 "=X,&r"))]
213	""	210	""
214	"#"	211	"#"
215	"reload_completed"	212	"epilogue_completed"
216	[(const_int 0)]	213	[(const_int 0)]
217	{	214	{
218	alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],	215	alpha_split_compare_and_swap_12 (<MODE>mode, operands[0], operands[1],
Lines 249-255 Link Here
249	(clobber (match_scratch:I48MODE 4 "=&r"))]	246	(clobber (match_scratch:I48MODE 4 "=&r"))]
250	""	247	""
251	"#"	248	"#"
252	"reload_completed"	249	"epilogue_completed"
253	[(const_int 0)]	250	[(const_int 0)]
254	{	251	{
255	alpha_split_compare_and_swap (operands[0], operands[1], operands[2],	252	alpha_split_compare_and_swap (operands[0], operands[1], operands[2],
Lines 280-286 Link Here
280	(clobber (match_scratch:DI 4 "=&r"))]	277	(clobber (match_scratch:DI 4 "=&r"))]
281	""	278	""
282	"#"	279	"#"
283	"reload_completed"	280	"epilogue_completed"
284	[(const_int 0)]	281	[(const_int 0)]
285	{	282	{
286	alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],	283	alpha_split_lock_test_and_set_12 (<MODE>mode, operands[0], operands[1],
Lines 299-305 Link Here
299	(clobber (match_scratch:I48MODE 3 "=&r"))]	296	(clobber (match_scratch:I48MODE 3 "=&r"))]
300	""	297	""
301	"#"	298	"#"
302	"reload_completed"	299	"epilogue_completed"
303	[(const_int 0)]	300	[(const_int 0)]
304	{	301	{
305	alpha_split_lock_test_and_set (operands[0], operands[1],	302	alpha_split_lock_test_and_set (operands[0], operands[1],

Line 0 Link Here

(-)gcc/testsuite/gcc.target/alpha/pr22093.c (+14 lines)
	1	/* { dg-do compile } */
	2	/* { dg-options "-O2" } */
	3
	4	struct shared_ptr_struct
	5	{
	6	unsigned long phase : 48;
	7	unsigned thread : 16;
	8	void *addr;
	9	} x;
	10
	11	void foo (void)
	12	{
	13	x.thread = 2;
	14	}

Line 0 Link Here

(-)gcc/testsuite/gcc.target/alpha/pr42113.c (+12 lines)
	1	/* { dg-do compile } */
	2	/* { dg-options "-O2" } */
	3
	4	int foo (int a, int b)
	5	{
	6	int bar = a * sizeof (int);
	7
	8	if (b)
	9	bar += sizeof (int);
	10
	11	return bar;
	12	}