[patch] 5350_ia64_4.2.99.901-hp-nv-memory-barrier.patch (updated for 4.3.99.901)

5350_ia64_4.2.99.901-hp-nv-memory-barrier.patch (text/plain), 3.77 KB, created by Aron Griffis (RETIRED) on 2003-12-09 12:29:45 UTC

(updated by agriffis to apply to 4.3.99.901)

This patch fixes various MCAs (Machine Check Architecture) on Hewlett
Packard Itanium 2 platforms by adding memory barriers where needed.

Mike A. Harris <[e-mail]>

--- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c.agriffis	2003-12-09 14:42:30.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c	2003-12-09 15:10:31.000000000 -0500
@@ -49,11 +49,13 @@
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PCIO, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
     VGA_WR08(pNv->PCIO, pVga->IOBase + VGA_CRTC_DATA_OFFSET,  value);
+    write_mem_barrier();
 }
 static CARD8 NVReadCrtc(vgaHWPtr pVga, CARD8 index)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PCIO, pVga->IOBase + VGA_CRTC_INDEX_OFFSET, index);
+    write_mem_barrier();
     return (VGA_RD08(pNv->PCIO, pVga->IOBase + VGA_CRTC_DATA_OFFSET));
 }
 static void NVWriteGr(vgaHWPtr pVga, CARD8 index, CARD8 value)
@@ -61,11 +63,13 @@
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PVIO, VGA_GRAPH_INDEX, index);
     VGA_WR08(pNv->PVIO, VGA_GRAPH_DATA,  value);
+    write_mem_barrier();
 }
 static CARD8 NVReadGr(vgaHWPtr pVga, CARD8 index)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PVIO, VGA_GRAPH_INDEX, index);
+    write_mem_barrier();
     return (VGA_RD08(pNv->PVIO, VGA_GRAPH_DATA));
 }
 static void NVWriteSeq(vgaHWPtr pVga, CARD8 index, CARD8 value)
@@ -73,11 +77,16 @@
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PVIO, VGA_SEQ_INDEX, index);
     VGA_WR08(pNv->PVIO, VGA_SEQ_DATA,  value);
+    write_mem_barrier();
+#if defined(linux) && defined(__ia64__)
+    usleep(250);
+#endif
 }
 static CARD8 NVReadSeq(vgaHWPtr pVga, CARD8 index)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PVIO, VGA_SEQ_INDEX, index);
+    write_mem_barrier();
     return (VGA_RD08(pNv->PVIO, VGA_SEQ_DATA));
 }
 static void NVWriteAttr(vgaHWPtr pVga, CARD8 index, CARD8 value)
@@ -92,6 +101,7 @@
         index |= 0x20;
     VGA_WR08(pNv->PCIO, VGA_ATTR_INDEX,  index);
     VGA_WR08(pNv->PCIO, VGA_ATTR_DATA_W, value);
+    write_mem_barrier();
 }
 static CARD8 NVReadAttr(vgaHWPtr pVga, CARD8 index)
 {
@@ -104,12 +114,14 @@
     else
         index |= 0x20;
     VGA_WR08(pNv->PCIO, VGA_ATTR_INDEX, index);
+    write_mem_barrier();
     return (VGA_RD08(pNv->PCIO, VGA_ATTR_DATA_R));
 }
 static void NVWriteMiscOut(vgaHWPtr pVga, CARD8 value)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PVIO, VGA_MISC_OUT_W, value);
+    write_mem_barrier();
 }
 static CARD8 NVReadMiscOut(vgaHWPtr pVga)
 {
@@ -123,6 +135,7 @@
 
     tmp = VGA_RD08(pNv->PCIO, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
     VGA_WR08(pNv->PCIO, VGA_ATTR_INDEX, 0x00);
+    write_mem_barrier();
     pVga->paletteEnabled = TRUE;
 }
 static void NVDisablePalette(vgaHWPtr pVga)
@@ -132,12 +145,14 @@
 
     tmp = VGA_RD08(pNv->PCIO, pVga->IOBase + VGA_IN_STAT_1_OFFSET);
     VGA_WR08(pNv->PCIO, VGA_ATTR_INDEX, 0x20);
+    write_mem_barrier();
     pVga->paletteEnabled = FALSE;
 }
 static void NVWriteDacMask(vgaHWPtr pVga, CARD8 value)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PDIO, VGA_DAC_MASK, value);
+    write_mem_barrier();
 }
 static CARD8 NVReadDacMask(vgaHWPtr pVga)
 {
@@ -148,16 +163,19 @@
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PDIO, VGA_DAC_READ_ADDR, value);
+    write_mem_barrier();
 }
 static void NVWriteDacWriteAddr(vgaHWPtr pVga, CARD8 value)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PDIO, VGA_DAC_WRITE_ADDR, value);
+    write_mem_barrier();
 }
 static void NVWriteDacData(vgaHWPtr pVga, CARD8 value)
 {
     NVPtr pNv = (NVPtr)pVga->MMIOBase;
     VGA_WR08(pNv->PDIO, VGA_DAC_DATA, value);
+    write_mem_barrier();
 }
 static CARD8 NVReadDacData(vgaHWPtr pVga)
 {