Attachment #183445 for bug #160627

Lines 369-375 Link Here

(-)qemu-0.9.1.orig/cpu-all.h (+6 lines)
369		369
370	static inline void stq_le_p(void *ptr, uint64_t v)	370	static inline void stq_le_p(void *ptr, uint64_t v)
371	{	371	{
		372	#if defined(__i386__) && __GNUC__ >= 4
		373	const union { uint64_t v; uint32_t p[2]; } x = { .v = v };
		374	((uint32_t *)ptr)[0] = x.p[0];
		375	((uint32_t *)ptr)[1] = x.p[1];
		376	#else
372	(uint64_t )ptr = v;	377	(uint64_t )ptr = v;
		378	#endif
373	}	379	}
374		380
375	/* float access */	381	/* float access */




void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);

#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
    (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU) && (__GNUC__ < 4)

#define CPU_TLB_ENTRY_BITS 4


                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%edx", "memory", "cc");
    return res;
}


                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__ld, SUFFIX), MMUSUFFIX))
                  : "%eax", "%edx", "memory", "cc");
    return res;
}
#endif

static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE val)
{
    RES_TYPE v = val;
    asm volatile ("movl %0, %%edx\n"
                  "movl %0, %%eax\n"
                  "shrl %3, %%edx\n"

                  "2:\n"
                  :
                  : "r" (ptr),
                  "q" (v),
   with T1 ! */
                  "r" (v),
                  "i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
                  "i" (TARGET_PAGE_MASK | (DATA_SIZE - 1)),
                  "m" (*(uint32_t *)offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
                  "i" (CPU_MMU_INDEX),
                  "m" (*(uint8_t *)&glue(glue(__st, SUFFIX), MMUSUFFIX))
                  : "%eax", "%edx", "memory", "cc");
}

#else

Lines 3607-3614 Link Here

(-)qemu-0.9.1.orig/target-i386/helper.c (+7 lines)
3607	nb_xmm_regs = 8 << data64;	3607	nb_xmm_regs = 8 << data64;
3608	addr = ptr + 0xa0;	3608	addr = ptr + 0xa0;
3609	for(i = 0; i < nb_xmm_regs; i++) {	3609	for(i = 0; i < nb_xmm_regs; i++) {
		3610	#if defined(__i386__) && __GNUC__ >= 4
		3611	env->xmm_regs[i].XMM_L(0) = ldl(addr);
		3612	env->xmm_regs[i].XMM_L(1) = ldl(addr + 4);
		3613	env->xmm_regs[i].XMM_L(2) = ldl(addr + 8);
		3614	env->xmm_regs[i].XMM_L(3) = ldl(addr + 12);
		3615	#else
3610	env->xmm_regs[i].XMM_Q(0) = ldq(addr);	3616	env->xmm_regs[i].XMM_Q(0) = ldq(addr);
3611	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);	3617	env->xmm_regs[i].XMM_Q(1) = ldq(addr + 8);
		3618	#endif
3612	addr += 16;	3619	addr += 16;
3613	}	3620	}
3614	}	3621	}

Lines 34-39 Link Here

(-)qemu-0.9.1.orig/target-i386/ops_sse.h (-1 / +7 lines)
34	#define Q(n) XMM_Q(n)	34	#define Q(n) XMM_Q(n)
35	#define SUFFIX _xmm	35	#define SUFFIX _xmm
36	#endif	36	#endif
		37	#if defined(__i386__) && __GNUC__ >= 4
		38	#define RegCopy(d, s) __builtin_memcpy(&(d), &(s), sizeof(d))
		39	#endif
		40	#ifndef RegCopy
		41	#define RegCopy(d, s) d = s
		42	#endif
37		43
38	void OPPROTO glue(op_psrlw, SUFFIX)(void)	44	void OPPROTO glue(op_psrlw, SUFFIX)(void)
39	{	45	{
Lines 589-595 Link Here
589	r.W(1) = s->W((order >> 2) & 3);	595	r.W(1) = s->W((order >> 2) & 3);
590	r.W(2) = s->W((order >> 4) & 3);	596	r.W(2) = s->W((order >> 4) & 3);
591	r.W(3) = s->W((order >> 6) & 3);	597	r.W(3) = s->W((order >> 6) & 3);
592	*d = r;	598	RegCopy(*d, r);
593	}	599	}
594	#else	600	#else
595	void OPPROTO op_shufps(void)	601	void OPPROTO op_shufps(void)

Return to bug 160627

Lines 75-81 Link Here

(-)qemu-0.9.1.orig/softmmu_header.h (-8 / +7 lines)
75	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);	75	void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
76		76
77	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \	77	#if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
78	(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)	78	(ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU) && (__GNUC__ < 4)
79		79
80	#define CPU_TLB_ENTRY_BITS 4	80	#define CPU_TLB_ENTRY_BITS 4
81		81
Lines 117-123 Link Here
117	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),	117	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
118	"i" (CPU_MMU_INDEX),	118	"i" (CPU_MMU_INDEX),
119	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))	119	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
120	: "%eax", "%ecx", "%edx", "memory", "cc");	120	: "%eax", "%edx", "memory", "cc");
121	return res;	121	return res;
122	}	122	}
123		123
Lines 164-176 Link Here
164	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),	164	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_read)),
165	"i" (CPU_MMU_INDEX),	165	"i" (CPU_MMU_INDEX),
166	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))	166	"m" ((uint8_t )&glue(glue(__ld, SUFFIX), MMUSUFFIX))
167	: "%eax", "%ecx", "%edx", "memory", "cc");	167	: "%eax", "%edx", "memory", "cc");
168	return res;	168	return res;
169	}	169	}
170	#endif	170	#endif
171		171
172	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE v)	172	static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE val)
173	{	173	{
		174	RES_TYPE v = val;
174	asm volatile ("movl %0, %%edx\n"	175	asm volatile ("movl %0, %%edx\n"
175	"movl %0, %%eax\n"	176	"movl %0, %%eax\n"
176	"shrl %3, %%edx\n"	177	"shrl %3, %%edx\n"
Lines 207-222 Link Here
207	"2:\n"	208	"2:\n"
208	:	209	:
209	: "r" (ptr),	210	: "r" (ptr),
210	/* NOTE: 'q' would be needed as constraint, but we could not use it	211	"q" (v),
211	with T1 ! */
212	"r" (v),
213	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),	212	"i" ((CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS),
214	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),	213	"i" (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
215	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),	214	"i" (TARGET_PAGE_MASK \| (DATA_SIZE - 1)),
216	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),	215	"m" ((uint32_t )offsetof(CPUState, tlb_table[CPU_MMU_INDEX][0].addr_write)),
217	"i" (CPU_MMU_INDEX),	216	"i" (CPU_MMU_INDEX),
218	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))	217	"m" ((uint8_t )&glue(glue(__st, SUFFIX), MMUSUFFIX))
219	: "%eax", "%ecx", "%edx", "memory", "cc");	218	: "%eax", "%edx", "memory", "cc");
220	}	219	}
221		220
222	#else	221	#else