Attachment #167073 for bug #239425

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Lines 23-29 Link Here

(-)orig/tools/ioemu/hw/e1000.c (-26 / +33 lines)
23	*/	23	*/
24		24
25		25
26	#include "vl.h"	26	#include "hw.h"
		27	#include "pci.h"
		28	#include "net.h"
27		29
28	#include "e1000_hw.h"	30	#include "e1000_hw.h"
29		31
Lines 74-80 Link Here
74	PCIDevice dev;	76	PCIDevice dev;
75	VLANClientState *vc;	77	VLANClientState *vc;
76	NICInfo *nd;	78	NICInfo *nd;
77	uint32_t instance;
78	uint32_t mmio_base;	79	uint32_t mmio_base;
79	int mmio_index;	80	int mmio_index;
80		81
Lines 103-109 Link Here
103	char tse;	104	char tse;
104	char ip;	105	char ip;
105	char tcp;	106	char tcp;
106	char cptse; //current packet tse bit	107	char cptse; // current packet tse bit
107	} tx;	108	} tx;
108		109
109	struct {	110	struct {
Lines 136-142 Link Here
136	[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,	137	[PHY_CTRL] = PHY_RW, [PHY_1000T_CTRL] = PHY_RW,
137	[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,	138	[PHY_LP_ABILITY] = PHY_R, [PHY_1000T_STATUS] = PHY_R,
138	[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,	139	[PHY_AUTONEG_ADV] = PHY_RW, [M88E1000_RX_ERR_CNTR] = PHY_R,
139	[PHY_ID2] = PHY_R,	140	[PHY_ID2] = PHY_R, [M88E1000_PHY_SPEC_STATUS] = PHY_R
140	};	141	};
141		142
142	static void	143	static void
Lines 152-158 Link Here
152	if (val)	153	if (val)
153	val \|= E1000_ICR_INT_ASSERTED;	154	val \|= E1000_ICR_INT_ASSERTED;
154	s->mac_reg[ICR] = val;	155	s->mac_reg[ICR] = val;
155	pci_set_irq(&s->dev, 0, (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);	156	qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
156	}	157	}
157		158
158	static void	159	static void
Lines 325-331 Link Here
325	if (tp->tcp) {	326	if (tp->tcp) {
326	sofar = frames * tp->mss;	327	sofar = frames * tp->mss;
327	cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq	328	cpu_to_be32wu((uint32_t *)(tp->data+css+4), // seq
328	be32_to_cpup((uint32_t *)(tp->data+css+4))+sofar);	329	be32_to_cpupu((uint32_t *)(tp->data+css+4))+sofar);
329	if (tp->paylen - sofar > tp->mss)	330	if (tp->paylen - sofar > tp->mss)
330	tp->data[css + 13] &= ~9; // PSH, FIN	331	tp->data[css + 13] &= ~9; // PSH, FIN
331	} else // UDP	332	} else // UDP
Lines 381-387 Link Here
381	tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);	382	tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
382	}	383	}
383	return;	384	return;
384	} else if (dtype == (E1000_TXD_CMD_DEXT \| E1000_TXD_DTYP_D)){	385	} else if (dtype == (E1000_TXD_CMD_DEXT \| E1000_TXD_DTYP_D)) {
385	// data descriptor	386	// data descriptor
386	tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;	387	tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
387	tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;	388	tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
Lines 459-465 Link Here
459	cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));	460	cpu_physical_memory_read(base, (void *)&desc, sizeof(desc));
460		461
461	DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],	462	DBGOUT(TX, "index %d: %p : %x %x\n", s->mac_reg[TDH],
462	(void *)desc.buffer_addr, desc.lower.data,	463	(void *)(intptr_t)desc.buffer_addr, desc.lower.data,
463	desc.upper.data);	464	desc.upper.data);
464		465
465	process_tx_desc(s, &desc);	466	process_tx_desc(s, &desc);
Lines 531-538 Link Here
531	{	532	{
532	E1000State *s = opaque;	533	E1000State *s = opaque;
533		534
534	return (!(s->mac_reg[RCTL] & E1000_RCTL_EN) \|\|	535	return (s->mac_reg[RCTL] & E1000_RCTL_EN);
535	s->mac_reg[RDH] != s->mac_reg[RDT]);
536	}	536	}
537		537
538	static void	538	static void
Lines 731-738 Link Here
731	E1000State *s = opaque;	731	E1000State *s = opaque;
732	unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;	732	unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
733		733
		734	#ifdef TARGET_WORDS_BIGENDIAN
		735	val = bswap32(val);
		736	#endif
734	if (index < NWRITEOPS && macreg_writeops[index])	737	if (index < NWRITEOPS && macreg_writeops[index])
735	macreg_writeops[index](s, index, le32_to_cpu(val));	738	macreg_writeops[index](s, index, val);
736	else if (index < NREADOPS && macreg_readops[index])	739	else if (index < NREADOPS && macreg_readops[index])
737	DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);	740	DBGOUT(MMIO, "e1000_mmio_writel RO %x: 0x%04x\n", index<<2, val);
738	else	741	else
Lines 745-751 Link Here
745	{	748	{
746	// emulate hw without byte enables: no RMW	749	// emulate hw without byte enables: no RMW
747	e1000_mmio_writel(opaque, addr & ~3,	750	e1000_mmio_writel(opaque, addr & ~3,
748	cpu_to_le32(le16_to_cpu(val & 0xffff) << (8*(addr & 3))));	751	(val & 0xffff) << (8*(addr & 3)));
749	}	752	}
750		753
751	static void	754	static void
Lines 753-759 Link Here
753	{	756	{
754	// emulate hw without byte enables: no RMW	757	// emulate hw without byte enables: no RMW
755	e1000_mmio_writel(opaque, addr & ~3,	758	e1000_mmio_writel(opaque, addr & ~3,
756	cpu_to_le32((val & 0xff) << (8*(addr & 3))));	759	(val & 0xff) << (8*(addr & 3)));
757	}	760	}
758		761
759	static uint32_t	762	static uint32_t
Lines 763-769 Link Here
763	unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;	766	unsigned int index = ((addr - s->mmio_base) & 0x1ffff) >> 2;
764		767
765	if (index < NREADOPS && macreg_readops[index])	768	if (index < NREADOPS && macreg_readops[index])
766	return cpu_to_le32(macreg_readops[index](s, index));	769	{
		770	uint32_t val = macreg_readops[index](s, index);
		771	#ifdef TARGET_WORDS_BIGENDIAN
		772	val = bswap32(val);
		773	#endif
		774	return val;
		775	}
767	DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);	776	DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
768	return 0;	777	return 0;
769	}	778	}
Lines 771-788 Link Here
771	static uint32_t	780	static uint32_t
772	e1000_mmio_readb(void *opaque, target_phys_addr_t addr)	781	e1000_mmio_readb(void *opaque, target_phys_addr_t addr)
773	{	782	{
774	return (le32_to_cpu(e1000_mmio_readl(opaque, addr & ~3)) >>	783	return ((e1000_mmio_readl(opaque, addr & ~3)) >>
775	(8 * (addr & 3))) & 0xff;	784	(8 * (addr & 3))) & 0xff;
776	}	785	}
777		786
778	static uint32_t	787	static uint32_t
779	e1000_mmio_readw(void *opaque, target_phys_addr_t addr)	788	e1000_mmio_readw(void *opaque, target_phys_addr_t addr)
780	{	789	{
781	return cpu_to_le16((le32_to_cpu(e1000_mmio_readl(opaque, addr & ~3)) >>	790	return ((e1000_mmio_readl(opaque, addr & ~3)) >>
782	(8 * (addr & 3))) & 0xffff);	791	(8 * (addr & 3))) & 0xffff;
783	}	792	}
784		793
785	int mac_regtosave[] = {	794	static int mac_regtosave[] = {
786	CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,	795	CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,
787	LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,	796	LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,
788	RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,	797	RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,
Lines 790-796 Link Here
790	};	799	};
791	enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };	800	enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };
792		801
793	struct {	802	static struct {
794	int size;	803	int size;
795	int array0;	804	int array0;
796	} mac_regarraystosave[] = { {32, RA}, {128, MTA} };	805	} mac_regarraystosave[] = { {32, RA}, {128, MTA} };
Lines 803-809 Link Here
803	int i, j;	812	int i, j;
804		813
805	pci_device_save(&s->dev, f);	814	pci_device_save(&s->dev, f);
806	qemu_put_be32s(f, &s->instance);
807	qemu_put_be32s(f, &s->mmio_base);	815	qemu_put_be32s(f, &s->mmio_base);
808	qemu_put_be32s(f, &s->rxbuf_size);	816	qemu_put_be32s(f, &s->rxbuf_size);
809	qemu_put_be32s(f, &s->rxbuf_min_shift);	817	qemu_put_be32s(f, &s->rxbuf_min_shift);
Lines 848-854 Link Here
848		856
849	if ((ret = pci_device_load(&s->dev, f)) < 0)	857	if ((ret = pci_device_load(&s->dev, f)) < 0)
850	return ret;	858	return ret;
851	qemu_get_be32s(f, &s->instance);	859	if (version_id == 1)
		860	qemu_get_be32s(f, &i); /* once some unused instance id */
852	qemu_get_be32s(f, &s->mmio_base);	861	qemu_get_be32s(f, &s->mmio_base);
853	qemu_get_be32s(f, &s->rxbuf_size);	862	qemu_get_be32s(f, &s->rxbuf_size);
854	qemu_get_be32s(f, &s->rxbuf_min_shift);	863	qemu_get_be32s(f, &s->rxbuf_min_shift);
Lines 903-908 Link Here
903	[PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,	912	[PHY_1000T_CTRL] = 0x0e00, [M88E1000_PHY_SPEC_CTRL] = 0x360,
904	[M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,	913	[M88E1000_EXT_PHY_SPEC_CTRL] = 0x0d60, [PHY_AUTONEG_ADV] = 0xde1,
905	[PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,	914	[PHY_LP_ABILITY] = 0x1e0, [PHY_1000T_STATUS] = 0x3c00,
		915	[M88E1000_PHY_SPEC_STATUS] = 0xac00,
906	};	916	};
907		917
908	static uint32_t mac_reg_init[] = {	918	static uint32_t mac_reg_init[] = {
Lines 946-954 Link Here
946	{	956	{
947	E1000State *d;	957	E1000State *d;
948	uint8_t *pci_conf;	958	uint8_t *pci_conf;
949	static int instance;
950	uint16_t checksum = 0;	959	uint16_t checksum = 0;
951	char *info_str = "e1000";	960	static const char info_str[] = "e1000";
952	int i;	961	int i;
953		962
954	d = (E1000State *)pci_register_device(bus, "e1000",	963	d = (E1000State *)pci_register_device(bus, "e1000",
Lines 977-984 Link Here
977	pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,	986	pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
978	PCI_ADDRESS_SPACE_IO, ioport_map);	987	PCI_ADDRESS_SPACE_IO, ioport_map);
979		988
980	d->instance = instance++;
981
982	d->nd = nd;	989	d->nd = nd;
983	memmove(d->eeprom_data, e1000_eeprom_template,	990	memmove(d->eeprom_data, e1000_eeprom_template,
984	sizeof e1000_eeprom_template);	991	sizeof e1000_eeprom_template);
Lines 1004-1008 Link Here
1004	d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],	1011	d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],
1005	d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);	1012	d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);
1006		1013
1007	register_savevm(info_str, d->instance, 1, nic_save, nic_load, d);	1014	register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1008	}	1015	}




    PCIDevice dev;
    VLANClientState *vc;
    NICInfo *nd;
    uint32_t instance;
    uint32_t mmio_base;
    int mmio_index;


        char tse;
        char ip;
        char tcp;
        char cptse;     // current packet tse bit
    } tx;

    struct {

    unsigned int frames = s->tx.tso_frames, css, sofar, n;
    struct e1000_tx *tp = &s->tx;

    if (tp->tse && tp->cptse) {
        css = tp->ipcss;
        DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
               frames, tp->size, css);

            tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
        }
        return;
    } else if (dtype == (E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D)) {
        // data descriptor
        tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
        tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
    } else
        // legacy descriptor
        tp->cptse = 0;

    addr = le64_to_cpu(dp->buffer_addr);
    if (tp->tse && tp->cptse) {
        hdr = tp->hdr_len;
        msh = hdr + tp->mss;
        do {
            bytes = split_size;
            if (tp->size + bytes > msh)
                bytes = msh - tp->size;
            cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
            if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
                memmove(tp->header, tp->data, hdr);
            tp->size = sz;
            addr += bytes;
            if (sz == msh) {
                xmit_seg(s);
                memmove(tp->data, tp->header, hdr);
                tp->size = hdr;
            }
        } while (split_size -= bytes);
    } else if (!tp->tse && tp->cptse) {
        // context descriptor TSE is not set, while data descriptor TSE is set
        DBGOUT(TXERR, "TCP segmentaion Error\n");
    } else {
        cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
        tp->size += split_size;
    }
    do {
        bytes = split_size;
        if (tp->size + bytes > msh)
            bytes = msh - tp->size;
        cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
        if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
            memmove(tp->header, tp->data, hdr);
        tp->size = sz;
        addr += bytes;
        if (sz == msh) {
            xmit_seg(s);
            memmove(tp->data, tp->header, hdr);
            tp->size = hdr;
        }
    } while (split_size -= bytes);

    if (!(txd_lower & E1000_TXD_CMD_EOP))
        return;
    if (!(tp->tse && tp->cptse && tp->size < hdr))
        xmit_seg(s);
    tp->tso_frames = 0;
    tp->sum_needed = 0;
    tp->size = 0;
    tp->cptse = 0;
}

static uint32_t

{
    E1000State *s = opaque;

    return (s->mac_reg[RCTL] & E1000_RCTL_EN);
            s->mac_reg[RDH] != s->mac_reg[RDT]);
}

static void

            (8 * (addr & 3))) & 0xffff;
}

static int mac_regtosave[] = {
    CTRL,	EECD,	EERD,	GPRC,	GPTC,	ICR,	ICS,	IMC,	IMS,
    LEDCTL,	MANC,	MDIC,	MPC,	PBA,	RCTL,	RDBAH,	RDBAL,	RDH,
    RDLEN,	RDT,	STATUS,	SWSM,	TCTL,	TDBAH,	TDBAL,	TDH,	TDLEN,

};
enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };

static struct {
    int size;
    int array0;
} mac_regarraystosave[] = { {32, RA}, {128, MTA} };

    int i, j;

    pci_device_save(&s->dev, f);
    qemu_put_be32s(f, &s->instance);
    qemu_put_be32s(f, &s->mmio_base);
    qemu_put_be32s(f, &s->rxbuf_size);
    qemu_put_be32s(f, &s->rxbuf_min_shift);


    if ((ret = pci_device_load(&s->dev, f)) < 0)
        return ret;
    if (version_id == 1)
        qemu_get_be32s(f, &i); /* once some unused instance id */
    qemu_get_be32s(f, &s->mmio_base);
    qemu_get_be32s(f, &s->rxbuf_size);
    qemu_get_be32s(f, &s->rxbuf_min_shift);

{
    E1000State *d;
    uint8_t *pci_conf;
    static int instance;
    uint16_t checksum = 0;
    static const char info_str[] = "e1000";
    int i;

    d = (E1000State *)pci_register_device(bus, "e1000",

    pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
                           PCI_ADDRESS_SPACE_IO, ioport_map);

    d->instance = instance++;

    d->nd = nd;
    memmove(d->eeprom_data, e1000_eeprom_template,
        sizeof e1000_eeprom_template);

             d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],
             d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);

    register_savevm(info_str, -1, 2, nic_save, nic_load, d);
}

Return to bug 239425

Lines 76-82 Link Here

(-)orig/tools/ioemu-qemu-xen/hw/e1000.c (-31 / +39 lines)
76	PCIDevice dev;	76	PCIDevice dev;
77	VLANClientState *vc;	77	VLANClientState *vc;
78	NICInfo *nd;	78	NICInfo *nd;
79	uint32_t instance;
80	uint32_t mmio_base;	79	uint32_t mmio_base;
81	int mmio_index;	80	int mmio_index;
82		81
Lines 105-110 Link Here
105	char tse;	104	char tse;
106	char ip;	105	char ip;
107	char tcp;	106	char tcp;
		107	char cptse; // current packet tse bit
108	} tx;	108	} tx;
109		109
110	struct {	110	struct {
Lines 308-314 Link Here
308	unsigned int frames = s->tx.tso_frames, css, sofar, n;	308	unsigned int frames = s->tx.tso_frames, css, sofar, n;
309	struct e1000_tx *tp = &s->tx;	309	struct e1000_tx *tp = &s->tx;
310		310
311	if (tp->tse) {	311	if (tp->tse && tp->cptse) {
312	css = tp->ipcss;	312	css = tp->ipcss;
313	DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",	313	DBGOUT(TXSUM, "frames %d size %d ipcss %d\n",
314	frames, tp->size, css);	314	frames, tp->size, css);
Lines 382-418 Link Here
382	tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);	382	tp->tucso = tp->tucss + (tp->tcp ? 16 : 6);
383	}	383	}
384	return;	384	return;
385	} else if (dtype == (E1000_TXD_CMD_DEXT \| E1000_TXD_DTYP_D))	385	} else if (dtype == (E1000_TXD_CMD_DEXT \| E1000_TXD_DTYP_D)) {
		386	// data descriptor
386	tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;	387	tp->sum_needed = le32_to_cpu(dp->upper.data) >> 8;
		388	tp->cptse = ( txd_lower & E1000_TXD_CMD_TSE ) ? 1 : 0;
		389	} else
		390	// legacy descriptor
		391	tp->cptse = 0;
387		392
388	addr = le64_to_cpu(dp->buffer_addr);	393	addr = le64_to_cpu(dp->buffer_addr);
389	if (tp->tse) {	394	if (tp->tse && tp->cptse) {
390	hdr = tp->hdr_len;	395	hdr = tp->hdr_len;
391	msh = hdr + tp->mss;	396	msh = hdr + tp->mss;
		397	do {
		398	bytes = split_size;
		399	if (tp->size + bytes > msh)
		400	bytes = msh - tp->size;
		401	cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
		402	if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
		403	memmove(tp->header, tp->data, hdr);
		404	tp->size = sz;
		405	addr += bytes;
		406	if (sz == msh) {
		407	xmit_seg(s);
		408	memmove(tp->data, tp->header, hdr);
		409	tp->size = hdr;
		410	}
		411	} while (split_size -= bytes);
		412	} else if (!tp->tse && tp->cptse) {
		413	// context descriptor TSE is not set, while data descriptor TSE is set
		414	DBGOUT(TXERR, "TCP segmentaion Error\n");
		415	} else {
		416	cpu_physical_memory_read(addr, tp->data + tp->size, split_size);
		417	tp->size += split_size;
392	}	418	}
393	do {
394	bytes = split_size;
395	if (tp->size + bytes > msh)
396	bytes = msh - tp->size;
397	cpu_physical_memory_read(addr, tp->data + tp->size, bytes);
398	if ((sz = tp->size + bytes) >= hdr && tp->size < hdr)
399	memmove(tp->header, tp->data, hdr);
400	tp->size = sz;
401	addr += bytes;
402	if (sz == msh) {
403	xmit_seg(s);
404	memmove(tp->data, tp->header, hdr);
405	tp->size = hdr;
406	}
407	} while (split_size -= bytes);
408		419
409	if (!(txd_lower & E1000_TXD_CMD_EOP))	420	if (!(txd_lower & E1000_TXD_CMD_EOP))
410	return;	421	return;
411	if (tp->size > hdr)	422	if (!(tp->tse && tp->cptse && tp->size < hdr))
412	xmit_seg(s);	423	xmit_seg(s);
413	tp->tso_frames = 0;	424	tp->tso_frames = 0;
414	tp->sum_needed = 0;	425	tp->sum_needed = 0;
415	tp->size = 0;	426	tp->size = 0;
		427	tp->cptse = 0;
416	}	428	}
417		429
418	static uint32_t	430	static uint32_t
Lines 520-527 Link Here
520	{	532	{
521	E1000State *s = opaque;	533	E1000State *s = opaque;
522		534
523	return (!(s->mac_reg[RCTL] & E1000_RCTL_EN) \|\|	535	return (s->mac_reg[RCTL] & E1000_RCTL_EN);
524	s->mac_reg[RDH] != s->mac_reg[RDT]);
525	}	536	}
526		537
527	static void	538	static void
Lines 780-786 Link Here
780	(8 * (addr & 3))) & 0xffff;	791	(8 * (addr & 3))) & 0xffff;
781	}	792	}
782		793
783	int mac_regtosave[] = {	794	static int mac_regtosave[] = {
784	CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,	795	CTRL, EECD, EERD, GPRC, GPTC, ICR, ICS, IMC, IMS,
785	LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,	796	LEDCTL, MANC, MDIC, MPC, PBA, RCTL, RDBAH, RDBAL, RDH,
786	RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,	797	RDLEN, RDT, STATUS, SWSM, TCTL, TDBAH, TDBAL, TDH, TDLEN,
Lines 788-794 Link Here
788	};	799	};
789	enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };	800	enum { MAC_NSAVE = sizeof mac_regtosave/sizeof *mac_regtosave };
790		801
791	struct {	802	static struct {
792	int size;	803	int size;
793	int array0;	804	int array0;
794	} mac_regarraystosave[] = { {32, RA}, {128, MTA} };	805	} mac_regarraystosave[] = { {32, RA}, {128, MTA} };
Lines 801-807 Link Here
801	int i, j;	812	int i, j;
802		813
803	pci_device_save(&s->dev, f);	814	pci_device_save(&s->dev, f);
804	qemu_put_be32s(f, &s->instance);
805	qemu_put_be32s(f, &s->mmio_base);	815	qemu_put_be32s(f, &s->mmio_base);
806	qemu_put_be32s(f, &s->rxbuf_size);	816	qemu_put_be32s(f, &s->rxbuf_size);
807	qemu_put_be32s(f, &s->rxbuf_min_shift);	817	qemu_put_be32s(f, &s->rxbuf_min_shift);
Lines 846-852 Link Here
846		856
847	if ((ret = pci_device_load(&s->dev, f)) < 0)	857	if ((ret = pci_device_load(&s->dev, f)) < 0)
848	return ret;	858	return ret;
849	qemu_get_be32s(f, &s->instance);	859	if (version_id == 1)
		860	qemu_get_be32s(f, &i); /* once some unused instance id */
850	qemu_get_be32s(f, &s->mmio_base);	861	qemu_get_be32s(f, &s->mmio_base);
851	qemu_get_be32s(f, &s->rxbuf_size);	862	qemu_get_be32s(f, &s->rxbuf_size);
852	qemu_get_be32s(f, &s->rxbuf_min_shift);	863	qemu_get_be32s(f, &s->rxbuf_min_shift);
Lines 945-953 Link Here
945	{	956	{
946	E1000State *d;	957	E1000State *d;
947	uint8_t *pci_conf;	958	uint8_t *pci_conf;
948	static int instance;
949	uint16_t checksum = 0;	959	uint16_t checksum = 0;
950	char *info_str = "e1000";	960	static const char info_str[] = "e1000";
951	int i;	961	int i;
952		962
953	d = (E1000State *)pci_register_device(bus, "e1000",	963	d = (E1000State *)pci_register_device(bus, "e1000",
Lines 976-983 Link Here
976	pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,	986	pci_register_io_region((PCIDevice *)d, 1, IOPORT_SIZE,
977	PCI_ADDRESS_SPACE_IO, ioport_map);	987	PCI_ADDRESS_SPACE_IO, ioport_map);
978		988
979	d->instance = instance++;
980
981	d->nd = nd;	989	d->nd = nd;
982	memmove(d->eeprom_data, e1000_eeprom_template,	990	memmove(d->eeprom_data, e1000_eeprom_template,
983	sizeof e1000_eeprom_template);	991	sizeof e1000_eeprom_template);
Lines 1003-1007 Link Here
1003	d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],	1011	d->nd->macaddr[0], d->nd->macaddr[1], d->nd->macaddr[2],
1004	d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);	1012	d->nd->macaddr[3], d->nd->macaddr[4], d->nd->macaddr[5]);
1005		1013
1006	register_savevm(info_str, d->instance, 1, nic_save, nic_load, d);	1014	register_savevm(info_str, -1, 2, nic_save, nic_load, d);
1007	}	1015	}