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Gentoo's Bugzilla – Attachment 130762 Details for
Bug 192349
xorg-server-1.4 consistently crashes w/ x11-drivers/xf86-video-ati on shutdown or ctrl-alt-backspace
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Xorg.0.log
Xorg.0.log (text/plain), 162.67 KB, created by
trefoil
on 2007-09-12 20:17:12 UTC
(
hide
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Description:
Xorg.0.log
Filename:
MIME Type:
Creator:
trefoil
Created:
2007-09-12 20:17:12 UTC
Size:
162.67 KB
patch
obsolete
> >X.Org X Server 1.4.0 >Release Date: 5 September 2007 >X Protocol Version 11, Revision 0 >Build Operating System: Linux 2.6.22-gentoo-r6 i686 >Current Operating System: Linux localhost 2.6.22-gentoo-r6 #1 Mon Sep 3 12:37:12 EDT 2007 i686 >Build Date: 12 September 2007 11:50:13AM > > Before reporting problems, check http://wiki.x.org > to make sure that you have the latest version. >Module Loader present >Markers: (--) probed, (**) from config file, (==) default setting, > (++) from command line, (!!) notice, (II) informational, > (WW) warning, (EE) error, (NI) not implemented, (??) unknown. >(==) Log file: "/var/log/Xorg.0.log", Time: Wed Sep 12 12:03:48 2007 >(EE) Unable to locate/open config file >(II) Loader magic: 0x81de660 >(II) Module ABI versions: > X.Org ANSI C Emulation: 0.3 > X.Org Video Driver: 2.0 > X.Org XInput driver : 2.0 > X.Org Server Extension : 0.3 > X.Org Font Renderer : 0.5 >(II) Loader running on linux >(II) LoadModule: "pcidata" >(II) Loading /usr/lib/xorg/modules//libpcidata.so >(II) Module pcidata: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org Video Driver, version 2.0 >(--) using VT number 7 > >(II) PCI: PCI scan (all values are in hex) >(II) PCI: 00:00:0: chip 10de,01e0 card 1043,80ac rev c1 class 06,00,00 hdr 80 >(II) PCI: 00:00:1: chip 10de,01ea card 1043,80ac rev c1 class 05,00,00 hdr 80 >(II) PCI: 00:00:2: chip 10de,01ee card 1043,80ac rev c1 class 05,00,00 hdr 80 >(II) PCI: 00:00:3: chip 10de,01ed card 1043,80ac rev c1 class 05,00,00 hdr 80 >(II) PCI: 00:00:4: chip 10de,01ec card 1043,80ac rev c1 class 05,00,00 hdr 80 >(II) PCI: 00:00:5: chip 10de,01ef card 1043,80ac rev c1 class 05,00,00 hdr 80 >(II) PCI: 00:01:0: chip 10de,0060 card 1043,80ad rev a4 class 06,01,00 hdr 80 >(II) PCI: 00:01:1: chip 10de,0064 card 1043,0c11 rev a2 class 0c,05,00 hdr 80 >(II) PCI: 00:02:0: chip 10de,0067 card 1043,0c11 rev a4 class 0c,03,10 hdr 80 >(II) PCI: 00:02:1: chip 10de,0067 card 1043,0c11 rev a4 class 0c,03,10 hdr 80 >(II) PCI: 00:02:2: chip 10de,0068 card 1043,0c11 rev a4 class 0c,03,20 hdr 80 >(II) PCI: 00:04:0: chip 10de,0066 card 1043,80a7 rev a1 class 02,00,00 hdr 00 >(II) PCI: 00:08:0: chip 10de,006c card 0000,0000 rev a3 class 06,04,00 hdr 01 >(II) PCI: 00:09:0: chip 10de,0065 card 1043,0c11 rev a2 class 01,01,8a hdr 00 >(II) PCI: 00:1e:0: chip 10de,01e8 card 0000,0000 rev c1 class 06,04,00 hdr 01 >(II) PCI: 01:08:0: chip 1102,0002 card 1102,8040 rev 05 class 04,01,00 hdr 80 >(II) PCI: 01:08:1: chip 1102,7002 card 1102,0020 rev 05 class 09,80,00 hdr 80 >(II) PCI: 02:00:0: chip 1002,4150 card 1002,4150 rev 00 class 03,00,00 hdr 80 >(II) PCI: 02:00:1: chip 1002,4170 card 1002,4151 rev 00 class 03,80,00 hdr 00 >(II) PCI: End of PCI scan >(II) Host-to-PCI bridge: >(II) Bus 0: bridge is at (0:0:0), (0,0,2), BCTRL: 0x0008 (VGA_EN is set) >(II) Bus 0 I/O range: > [0] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] >(II) Bus 0 non-prefetchable memory range: > [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] >(II) Bus 0 prefetchable memory range: > [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] >(II) PCI-to-ISA bridge: >(II) Bus -1: bridge is at (0:1:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set) >(II) PCI-to-PCI bridge: >(II) Bus 1: bridge is at (0:8:0), (0,1,1), BCTRL: 0x0202 (VGA_EN is cleared) >(II) Bus 1 I/O range: > [0] -1 0 0x0000c000 - 0x0000cfff (0x1000) IX[B] >(II) PCI-to-PCI bridge: >(II) Bus 2: bridge is at (0:30:0), (0,2,2), BCTRL: 0x000a (VGA_EN is set) >(II) Bus 2 I/O range: > [0] -1 0 0x0000d000 - 0x0000dfff (0x1000) IX[B] >(II) Bus 2 non-prefetchable memory range: > [0] -1 0 0xe4000000 - 0xe5ffffff (0x2000000) MX[B] >(II) Bus 2 prefetchable memory range: > [0] -1 0 0xc0000000 - 0xdfffffff (0x20000000) MX[B] >(--) PCI:*(2:0:0) ATI Technologies Inc RV350 AP [Radeon 9600] rev 0, Mem @ 0xc0000000/28, 0xe5000000/16, I/O @ 0xd000/8 >(--) PCI: (2:0:1) ATI Technologies Inc RV350 AP [Radeon 9600] (Secondary) rev 0, Mem @ 0xd0000000/28, 0xe5010000/16 >New driver is "ati" >(==) Using default built-in configuration (55 lines) >(==) --- Start of built-in configuration --- > Section "Module" > Load "extmod" > Load "dbe" > Load "glx" > Load "freetype" > Load "type1" > Load "record" > Load "dri" > EndSection > Section "Monitor" > Identifier "Builtin Default Monitor" > EndSection > Section "Device" > Identifier "Builtin Default ati Device 0" > Driver "ati" > EndSection > Section "Screen" > Identifier "Builtin Default ati Screen 0" > Device "Builtin Default ati Device 0" > Monitor "Builtin Default Monitor" > EndSection > Section "Device" > Identifier "Builtin Default fbdev Device 0" > Driver "fbdev" > EndSection > Section "Screen" > Identifier "Builtin Default fbdev Screen 0" > Device "Builtin Default fbdev Device 0" > Monitor "Builtin Default Monitor" > EndSection > Section "Device" > Identifier "Builtin Default vesa Device 0" > Driver "vesa" > EndSection > Section "Screen" > Identifier "Builtin Default vesa Screen 0" > Device "Builtin Default vesa Device 0" > Monitor "Builtin Default Monitor" > EndSection > Section "Device" > Identifier "Builtin Default vga Device 0" > Driver "vga" > EndSection > Section "Screen" > Identifier "Builtin Default vga Screen 0" > Device "Builtin Default vga Device 0" > Monitor "Builtin Default Monitor" > EndSection > Section "ServerLayout" > Identifier "Builtin Default Layout" > Screen "Builtin Default ati Screen 0" > Screen "Builtin Default fbdev Screen 0" > Screen "Builtin Default vesa Screen 0" > Screen "Builtin Default vga Screen 0" > EndSection >(==) --- End of built-in configuration --- >(==) ServerLayout "Builtin Default Layout" >(**) |-->Screen "Builtin Default ati Screen 0" (0) >(**) | |-->Monitor "Builtin Default Monitor" >(**) | |-->Device "Builtin Default ati Device 0" >(**) |-->Screen "Builtin Default fbdev Screen 0" (1) >(**) | |-->Monitor "Builtin Default Monitor" >(**) | |-->Device "Builtin Default fbdev Device 0" >(**) |-->Screen "Builtin Default vesa Screen 0" (2) >(**) | |-->Monitor "Builtin Default Monitor" >(**) | |-->Device "Builtin Default vesa Device 0" >(**) |-->Screen "Builtin Default vga Screen 0" (3) >(**) | |-->Monitor "Builtin Default Monitor" >(**) | |-->Device "Builtin Default vga Device 0" >(==) Automatically adding devices >(==) Automatically enabling devices >(==) No FontPath specified. Using compiled-in default. >(WW) The directory "/usr/share/fonts/OTF" does not exist. > Entry deleted from font path. >(==) FontPath set to: > /usr/share/fonts/misc/, > /usr/share/fonts/TTF/, > /usr/share/fonts/Type1/, > /usr/share/fonts/100dpi/, > /usr/share/fonts/75dpi/ >(==) RgbPath set to "/usr/share/X11/rgb" >(==) ModulePath set to "/usr/lib/xorg/modules" >(==) |-->Input Device "<default pointer>" >(==) |-->Input Device "<default keyboard>" >(==) The core pointer device wasn't specified explicitly in the layout. > Using the default mouse configuration. >(==) The core keyboard device wasn't specified explicitly in the layout. > Using the default keyboard configuration. >(II) Open ACPI successful (/var/run/acpid.socket) >(II) Addressable bus resource ranges are > [0] -1 0 0x00000000 - 0xffffffff (0x0) MX[B] > [1] -1 0 0x00000000 - 0x0000ffff (0x10000) IX[B] >(II) OS-reported resource ranges: > [0] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [4] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [5] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] >(II) PCI Memory resource overlap reduced 0xe0000000 from 0xe3ffffff to 0xdfffffff >(II) Active PCI resource ranges: > [0] -1 0 0xe6001000 - 0xe6001fff (0x1000) MX[B] > [1] -1 0 0xe6000000 - 0xe60000ff (0x100) MX[B] > [2] -1 0 0xe6003000 - 0xe6003fff (0x1000) MX[B] > [3] -1 0 0xe6002000 - 0xe6002fff (0x1000) MX[B] > [4] -1 0 0xe0000000 - 0xdfffffff (0x0) MX[B]O > [5] -1 0 0xe5000000 - 0xe500ffff (0x10000) MX[B](B) > [6] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [7] -1 0 0x0000c400 - 0x0000c407 (0x8) IX[B] > [8] -1 0 0x0000c000 - 0x0000c01f (0x20) IX[B] > [9] -1 0 0x0000f000 - 0x0000f00f (0x10) IX[B] > [10] -1 0 0x0000e400 - 0x0000e407 (0x8) IX[B] > [11] -1 0 0x0000e000 - 0x0000e01f (0x20) IX[B] > [12] -1 0 0x0000d000 - 0x0000d0ff (0x100) IX[B](B) >(II) Inactive PCI resource ranges: > [0] -1 0 0xe5010000 - 0xe501ffff (0x10000) MX[B](B) > [1] -1 0 0xd0000000 - 0xdfffffff (0x10000000) MX[B](B) >(II) Active PCI resource ranges after removing overlaps: > [0] -1 0 0xe6001000 - 0xe6001fff (0x1000) MX[B] > [1] -1 0 0xe6000000 - 0xe60000ff (0x100) MX[B] > [2] -1 0 0xe6003000 - 0xe6003fff (0x1000) MX[B] > [3] -1 0 0xe6002000 - 0xe6002fff (0x1000) MX[B] > [4] -1 0 0xe0000000 - 0xdfffffff (0x0) MX[B]O > [5] -1 0 0xe5000000 - 0xe500ffff (0x10000) MX[B](B) > [6] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [7] -1 0 0x0000c400 - 0x0000c407 (0x8) IX[B] > [8] -1 0 0x0000c000 - 0x0000c01f (0x20) IX[B] > [9] -1 0 0x0000f000 - 0x0000f00f (0x10) IX[B] > [10] -1 0 0x0000e400 - 0x0000e407 (0x8) IX[B] > [11] -1 0 0x0000e000 - 0x0000e01f (0x20) IX[B] > [12] -1 0 0x0000d000 - 0x0000d0ff (0x100) IX[B](B) >(II) Inactive PCI resource ranges after removing overlaps: > [0] -1 0 0xe5010000 - 0xe501ffff (0x10000) MX[B](B) > [1] -1 0 0xd0000000 - 0xdfffffff (0x10000000) MX[B](B) >(II) OS-reported resource ranges after removing overlaps with PCI: > [0] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [4] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [5] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] >(II) All system resource ranges: > [0] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [4] -1 0 0xe6001000 - 0xe6001fff (0x1000) MX[B] > [5] -1 0 0xe6000000 - 0xe60000ff (0x100) MX[B] > [6] -1 0 0xe6003000 - 0xe6003fff (0x1000) MX[B] > [7] -1 0 0xe6002000 - 0xe6002fff (0x1000) MX[B] > [8] -1 0 0xe0000000 - 0xdfffffff (0x0) MX[B]O > [9] -1 0 0xe5000000 - 0xe500ffff (0x10000) MX[B](B) > [10] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [11] -1 0 0xe5010000 - 0xe501ffff (0x10000) MX[B](B) > [12] -1 0 0xd0000000 - 0xdfffffff (0x10000000) MX[B](B) > [13] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [14] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] > [15] -1 0 0x0000c400 - 0x0000c407 (0x8) IX[B] > [16] -1 0 0x0000c000 - 0x0000c01f (0x20) IX[B] > [17] -1 0 0x0000f000 - 0x0000f00f (0x10) IX[B] > [18] -1 0 0x0000e400 - 0x0000e407 (0x8) IX[B] > [19] -1 0 0x0000e000 - 0x0000e01f (0x20) IX[B] > [20] -1 0 0x0000d000 - 0x0000d0ff (0x100) IX[B](B) >(II) "extmod" will be loaded. This was enabled by default and also specified in the config file. >(II) "dbe" will be loaded. This was enabled by default and also specified in the config file. >(II) "glx" will be loaded. This was enabled by default and also specified in the config file. >(II) "freetype" will be loaded. This was enabled by default and also specified in the config file. >(II) "type1" will be loaded. This was enabled by default and also specified in the config file. >(II) "record" will be loaded. This was enabled by default and also specified in the config file. >(II) "dri" will be loaded. This was enabled by default and also specified in the config file. >(II) LoadModule: "extmod" >(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so >(II) Module extmod: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > Module class: X.Org Server Extension > ABI class: X.Org Server Extension, version 0.3 >(II) Loading extension SHAPE >(II) Loading extension MIT-SUNDRY-NONSTANDARD >(II) Loading extension BIG-REQUESTS >(II) Loading extension SYNC >(II) Loading extension MIT-SCREEN-SAVER >(II) Loading extension XC-MISC >(II) Loading extension XFree86-VidModeExtension >(II) Loading extension XFree86-Misc >(II) Loading extension XFree86-DGA >(II) Loading extension DPMS >(II) Loading extension TOG-CUP >(II) Loading extension Extended-Visual-Information >(II) Loading extension XVideo >(II) Loading extension XVideo-MotionCompensation >(II) Loading extension X-Resource >(II) LoadModule: "dbe" >(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so >(II) Module dbe: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > Module class: X.Org Server Extension > ABI class: X.Org Server Extension, version 0.3 >(II) Loading extension DOUBLE-BUFFER >(II) LoadModule: "glx" >(II) Loading /usr/lib/xorg/modules/extensions//libglx.so >(II) Module glx: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org Server Extension, version 0.3 >(==) AIGLX enabled >(II) Loading extension GLX >(II) LoadModule: "freetype" >(II) Loading /usr/lib/xorg/modules/fonts//libfreetype.so >(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project" > compiled for 1.4.0, module version = 2.1.0 > Module class: X.Org Font Renderer > ABI class: X.Org Font Renderer, version 0.5 >(II) Loading font FreeType >(II) LoadModule: "type1" >(II) Loading /usr/lib/xorg/modules/fonts//libtype1.so >(II) Module type1: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.2 > Module class: X.Org Font Renderer > ABI class: X.Org Font Renderer, version 0.5 >(II) Loading font Type1 >(II) LoadModule: "record" >(II) Loading /usr/lib/xorg/modules/extensions//librecord.so >(II) Module record: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.13.0 > Module class: X.Org Server Extension > ABI class: X.Org Server Extension, version 0.3 >(II) Loading extension RECORD >(II) LoadModule: "dri" >(II) Loading /usr/lib/xorg/modules/extensions//libdri.so >(II) Module dri: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org Server Extension, version 0.3 >(II) Loading extension XFree86-DRI >(II) LoadModule: "ati" >(II) Loading /usr/lib/xorg/modules/drivers//ati_drv.so >(II) Module ati: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 6.6.3 > Module class: X.Org Video Driver > ABI class: X.Org Video Driver, version 2.0 >(II) LoadModule: "fbdev" >(II) Loading /usr/lib/xorg/modules/drivers//fbdev_drv.so >(II) Module fbdev: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 0.3.1 > ABI class: X.Org Video Driver, version 2.0 >(II) LoadModule: "vesa" >(II) Loading /usr/lib/xorg/modules/drivers//vesa_drv.so >(II) Module vesa: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.3.0 > Module class: X.Org Video Driver > ABI class: X.Org Video Driver, version 2.0 >(II) LoadModule: "vga" >(WW) Warning, couldn't open module vga >(II) UnloadModule: "vga" >(EE) Failed to load module "vga" (module does not exist, 0) >(II) LoadModule: "mouse" >(II) Loading /usr/lib/xorg/modules/input//mouse_drv.so >(II) Module mouse: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.2.2 > Module class: X.Org XInput Driver > ABI class: X.Org XInput driver, version 2.0 >(II) LoadModule: "kbd" >(II) Loading /usr/lib/xorg/modules/input//kbd_drv.so >(II) Module kbd: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.2.2 > Module class: X.Org XInput Driver > ABI class: X.Org XInput driver, version 2.0 >(II) ATI: ATI driver (version 6.6.3) for chipsets: ati, ativga >(II) R128: Driver for ATI Rage 128 chipsets: > ATI Rage 128 Mobility M3 LE (PCI), ATI Rage 128 Mobility M3 LF (AGP), > ATI Rage 128 Mobility M4 MF (AGP), ATI Rage 128 Mobility M4 ML (AGP), > ATI Rage 128 Pro GL PA (PCI/AGP), ATI Rage 128 Pro GL PB (PCI/AGP), > ATI Rage 128 Pro GL PC (PCI/AGP), ATI Rage 128 Pro GL PD (PCI), > ATI Rage 128 Pro GL PE (PCI/AGP), ATI Rage 128 Pro GL PF (AGP), > ATI Rage 128 Pro VR PG (PCI/AGP), ATI Rage 128 Pro VR PH (PCI/AGP), > ATI Rage 128 Pro VR PI (PCI/AGP), ATI Rage 128 Pro VR PJ (PCI/AGP), > ATI Rage 128 Pro VR PK (PCI/AGP), ATI Rage 128 Pro VR PL (PCI/AGP), > ATI Rage 128 Pro VR PM (PCI/AGP), ATI Rage 128 Pro VR PN (PCI/AGP), > ATI Rage 128 Pro VR PO (PCI/AGP), ATI Rage 128 Pro VR PP (PCI), > ATI Rage 128 Pro VR PQ (PCI/AGP), ATI Rage 128 Pro VR PR (PCI), > ATI Rage 128 Pro VR PS (PCI/AGP), ATI Rage 128 Pro VR PT (PCI/AGP), > ATI Rage 128 Pro VR PU (PCI/AGP), ATI Rage 128 Pro VR PV (PCI/AGP), > ATI Rage 128 Pro VR PW (PCI/AGP), ATI Rage 128 Pro VR PX (PCI/AGP), > ATI Rage 128 GL RE (PCI), ATI Rage 128 GL RF (AGP), > ATI Rage 128 RG (AGP), ATI Rage 128 VR RK (PCI), > ATI Rage 128 VR RL (AGP), ATI Rage 128 4X SE (PCI/AGP), > ATI Rage 128 4X SF (PCI/AGP), ATI Rage 128 4X SG (PCI/AGP), > ATI Rage 128 4X SH (PCI/AGP), ATI Rage 128 4X SK (PCI/AGP), > ATI Rage 128 4X SL (PCI/AGP), ATI Rage 128 4X SM (AGP), > ATI Rage 128 4X SN (PCI/AGP), ATI Rage 128 Pro ULTRA TF (AGP), > ATI Rage 128 Pro ULTRA TL (AGP), ATI Rage 128 Pro ULTRA TR (AGP), > ATI Rage 128 Pro ULTRA TS (AGP?), ATI Rage 128 Pro ULTRA TT (AGP?), > ATI Rage 128 Pro ULTRA TU (AGP?) >(II) RADEON: Driver for ATI Radeon chipsets: ATI Radeon QD (AGP), > ATI Radeon QE (AGP), ATI Radeon QF (AGP), ATI Radeon QG (AGP), > ATI Radeon VE/7000 QY (AGP/PCI), ATI Radeon VE/7000 QZ (AGP/PCI), > ATI ES1000 515E (PCI), ATI ES1000 5969 (PCI), > ATI Radeon Mobility M7 LW (AGP), > ATI Mobility FireGL 7800 M7 LX (AGP), > ATI Radeon Mobility M6 LY (AGP), ATI Radeon Mobility M6 LZ (AGP), > ATI Radeon IGP320 (A3) 4136, ATI Radeon IGP320M (U1) 4336, > ATI Radeon IGP330/340/350 (A4) 4137, > ATI Radeon IGP330M/340M/350M (U2) 4337, > ATI Radeon 7000 IGP (A4+) 4237, ATI Radeon Mobility 7000 IGP 4437, > ATI FireGL 8700/8800 QH (AGP), ATI Radeon 8500 QL (AGP), > ATI Radeon 9100 QM (AGP), ATI Radeon 8500 AIW BB (AGP), > ATI Radeon 8500 AIW BC (AGP), ATI Radeon 7500 QW (AGP/PCI), > ATI Radeon 7500 QX (AGP/PCI), ATI Radeon 9000/PRO If (AGP/PCI), > ATI Radeon 9000 Ig (AGP/PCI), ATI FireGL Mobility 9000 (M9) Ld (AGP), > ATI Radeon Mobility 9000 (M9) Lf (AGP), > ATI Radeon Mobility 9000 (M9) Lg (AGP), > ATI Radeon 9100 IGP (A5) 5834, > ATI Radeon Mobility 9100 IGP (U3) 5835, ATI Radeon 9100 PRO IGP 7834, > ATI Radeon Mobility 9200 IGP 7835, ATI Radeon 9250 5960 (AGP), > ATI Radeon 9200 5961 (AGP), ATI Radeon 9200 5962 (AGP), > ATI Radeon 9200SE 5964 (AGP), ATI FireMV 2200 (PCI), > ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), > ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Radeon 9500 AD (AGP), > ATI Radeon 9500 AE (AGP), ATI Radeon 9600TX AF (AGP), > ATI FireGL Z1 AG (AGP), ATI Radeon 9700 Pro ND (AGP), > ATI Radeon 9700/9500Pro NE (AGP), ATI Radeon 9600TX NF (AGP), > ATI FireGL X1 NG (AGP), ATI Radeon 9600 AP (AGP), > ATI Radeon 9600SE AQ (AGP), ATI Radeon 9600XT AR (AGP), > ATI Radeon 9600 AS (AGP), ATI FireGL T2 AT (AGP), > ATI FireGL RV360 AV (AGP), > ATI Radeon Mobility 9600/9700 (M10/M11) NP (AGP), > ATI Radeon Mobility 9600 (M10) NQ (AGP), > ATI Radeon Mobility 9600 (M11) NR (AGP), > ATI Radeon Mobility 9600 (M10) NS (AGP), > ATI FireGL Mobility T2 (M10) NT (AGP), > ATI FireGL Mobility T2e (M11) NV (AGP), ATI Radeon 9650, > ATI Radeon 9800SE AH (AGP), ATI Radeon 9800 AI (AGP), > ATI Radeon 9800 AJ (AGP), ATI FireGL X2 AK (AGP), > ATI Radeon 9800PRO NH (AGP), ATI Radeon 9800 NI (AGP), > ATI FireGL X2 NK (AGP), ATI Radeon 9800XT NJ (AGP), > ATI Radeon X600 (RV380) 3E50 (PCIE), > ATI FireGL V3200 (RV380) 3E54 (PCIE), > ATI Radeon Mobility X600 (M24) 3150 (PCIE), > ATI Radeon Mobility X300 (M24) 3152 (PCIE), > ATI FireGL M24 GL 3154 (PCIE), ATI Radeon X300 (RV370) 5B60 (PCIE), > ATI Radeon X600 (RV370) 5B62 (PCIE), > ATI Radeon X550 (RV370) 5B63 (PCIE), > ATI FireGL V3100 (RV370) 5B64 (PCIE), > ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE), > ATI Radeon Mobility X300 (M22) 5460 (PCIE), > ATI Radeon Mobility X600 SE (M24C) 5462 (PCIE), > ATI FireGL M22 GL 5464 (PCIE), ATI Radeon XPRESS 200 5A41 (PCIE), > ATI Radeon XPRESS 200M 5A42 (PCIE), > ATI Radeon XPRESS 200 5A61 (PCIE), > ATI Radeon XPRESS 200M 5A62 (PCIE), > ATI Radeon XPRESS 200 5954 (PCIE), > ATI Radeon XPRESS 200M 5955 (PCIE), > ATI Radeon XPRESS 200 5974 (PCIE), > ATI Radeon XPRESS 200M 5975 (PCIE), ATI FireGL V5000 (RV410) (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility FireGL V5000 (M26) (PCIE), > ATI Mobility Radeon X700 XL (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Mobility Radeon X700 (M26) (PCIE), > ATI Radeon X700 PRO (RV410) (PCIE), > ATI Radeon X700 XT (RV410) (PCIE), ATI Radeon X700 (RV410) (PCIE), > ATI Radeon X700 SE (RV410) (PCIE), ATI Radeon X700 SE (RV410) (PCIE), > ATI Radeon X800 (R420) JH (AGP), ATI Radeon X800PRO (R420) JI (AGP), > ATI Radeon X800SE (R420) JJ (AGP), ATI Radeon X800 (R420) JK (AGP), > ATI Radeon X800 (R420) JL (AGP), ATI FireGL X3 (R420) JM (AGP), > ATI Radeon Mobility 9800 (M18) JN (AGP), > ATI Radeon X800XT (R420) JP (AGP), ATI Radeon X800 SE (R420) (AGP), > ATI Radeon AIW X800 VE (R420) JT (AGP), > ATI Radeon X800 (R423) UH (PCIE), > ATI Radeon X800PRO (R423) UI (PCIE), > ATI Radeon X800LE (R423) UJ (PCIE), > ATI Radeon X800SE (R423) UK (PCIE), > ATI FireGL V5100 (R423) UQ (PCIE), > ATI FireGL unknown (R423) UR (PCIE), > ATI FireGL unknown (R423) UT (PCIE), > ATI Radeon X800XT (R423) 5D57 (PCIE), ATI FireGL V7100 (R423) (PCIE), > ATI Mobility FireGL V5100 (M28) (PCIE), > ATI Mobility Radeon X800 (M28) (PCIE), > ATI Mobility Radeon X800 XT (M28) (PCIE), > ATI Radeon X800 (R430) (PCIE), ATI Radeon X800 XL (R430) (PCIE), > ATI Radeon X800 SE (R430) (PCIE), ATI Radeon X800 XTP (R430) (PCIE), > ATI Radeon X850 5D4C (PCIE), > ATI unknown Radeon / FireGL (R480) 5D50 (PCIE), > ATI Radeon X850 SE (R480) (PCIE), ATI Radeon X850 PRO (R480) (PCIE), > ATI Radeon X850 XT (R480) (PCIE), > ATI Radeon X850 XT PE (R480) (PCIE), > ATI Radeon X850 PRO (R480) (AGP), ATI Radeon X850 SE (R480) (AGP), > ATI Radeon X850 XT (R480) (AGP), ATI Radeon X850 XT PE (R480) (AGP) >(II) FBDEV: driver for framebuffer: fbdev >(II) VESA: driver for VESA chipsets: vesa >(II) Primary Device is: PCI 02:00:0 >(II) ATI: Candidate "Device" section "Builtin Default ati Device 0". >(--) Assigning device section with no busID to primary device >(WW) RADEON: No matching Device section for instance (BusID PCI:2:0:1) found >(--) Chipset ATI Radeon 9600 AP (AGP) found >(II) resource ranges after xf86ClaimFixedResources() call: > [0] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [4] -1 0 0xe6001000 - 0xe6001fff (0x1000) MX[B] > [5] -1 0 0xe6000000 - 0xe60000ff (0x100) MX[B] > [6] -1 0 0xe6003000 - 0xe6003fff (0x1000) MX[B] > [7] -1 0 0xe6002000 - 0xe6002fff (0x1000) MX[B] > [8] -1 0 0xe0000000 - 0xdfffffff (0x0) MX[B]O > [9] -1 0 0xe5000000 - 0xe500ffff (0x10000) MX[B](B) > [10] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [11] -1 0 0xe5010000 - 0xe501ffff (0x10000) MX[B](B) > [12] -1 0 0xd0000000 - 0xdfffffff (0x10000000) MX[B](B) > [13] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [14] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] > [15] -1 0 0x0000c400 - 0x0000c407 (0x8) IX[B] > [16] -1 0 0x0000c000 - 0x0000c01f (0x20) IX[B] > [17] -1 0 0x0000f000 - 0x0000f00f (0x10) IX[B] > [18] -1 0 0x0000e400 - 0x0000e407 (0x8) IX[B] > [19] -1 0 0x0000e000 - 0x0000e01f (0x20) IX[B] > [20] -1 0 0x0000d000 - 0x0000d0ff (0x100) IX[B](B) >(II) Loading sub module "radeon" >(II) LoadModule: "radeon" >(II) Loading /usr/lib/xorg/modules/drivers//radeon_drv.so >(II) Module radeon: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 4.2.0 > Module class: X.Org Video Driver > ABI class: X.Org Video Driver, version 2.0 >(II) Loading sub module "fbdevhw" >(II) LoadModule: "fbdevhw" >(II) Loading /usr/lib/xorg/modules/linux//libfbdevhw.so >(II) Module fbdevhw: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 0.0.2 > ABI class: X.Org Video Driver, version 2.0 >(EE) open /dev/fb0: No such file or directory >(--) Assigning device section with no busID to primary device >(--) Chipset vesa found >(II) resource ranges after probing: > [0] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [1] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [2] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [3] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [4] -1 0 0xe6001000 - 0xe6001fff (0x1000) MX[B] > [5] -1 0 0xe6000000 - 0xe60000ff (0x100) MX[B] > [6] -1 0 0xe6003000 - 0xe6003fff (0x1000) MX[B] > [7] -1 0 0xe6002000 - 0xe6002fff (0x1000) MX[B] > [8] -1 0 0xe0000000 - 0xdfffffff (0x0) MX[B]O > [9] -1 0 0xe5000000 - 0xe500ffff (0x10000) MX[B](B) > [10] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [11] -1 0 0xe5010000 - 0xe501ffff (0x10000) MX[B](B) > [12] -1 0 0xd0000000 - 0xdfffffff (0x10000000) MX[B](B) > [13] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B] > [14] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B] > [15] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B] > [16] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [17] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] > [18] -1 0 0x0000c400 - 0x0000c407 (0x8) IX[B] > [19] -1 0 0x0000c000 - 0x0000c01f (0x20) IX[B] > [20] -1 0 0x0000f000 - 0x0000f00f (0x10) IX[B] > [21] -1 0 0x0000e400 - 0x0000e407 (0x8) IX[B] > [22] -1 0 0x0000e000 - 0x0000e01f (0x20) IX[B] > [23] -1 0 0x0000d000 - 0x0000d0ff (0x100) IX[B](B) > [24] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B] > [25] 0 0 0x000003c0 - 0x000003df (0x20) IS[B] >(II) Setting vga for screen 0. >(**) RADEON(0): RADEONPreInit >(II) RADEON(0): MMIO registers at 0xe5000000: size 64KB >(II) RADEON(0): PCI bus 2 card 0 func 0 >(II) RADEON(0): Creating default Display subsection in Screen section > "Builtin Default ati Screen 0" for depth/fbbpp 24/32 >(==) RADEON(0): Depth 24, (==) framebuffer bpp 32 >(II) RADEON(0): Pixel depth = 24 bits stored in 4 bytes (32 bpp pixmaps) >(==) RADEON(0): Default visual is TrueColor >(II) Loading sub module "vgahw" >(II) LoadModule: "vgahw" >(II) Loading /usr/lib/xorg/modules//libvgahw.so >(II) Module vgahw: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 0.1.0 > ABI class: X.Org Video Driver, version 2.0 >(II) RADEON(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000 >(==) RADEON(0): RGB weight 888 >(II) RADEON(0): Using 8 bits per RGB (8 bit DAC) >(==) RADEON(0): X server will not keep DPI constant for all screen sizes >(II) Loading sub module "int10" >(II) LoadModule: "int10" >(II) Loading /usr/lib/xorg/modules//libint10.so >(II) Module int10: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org Video Driver, version 2.0 >(II) RADEON(0): initializing int10 >(II) RADEON(0): Primary V_BIOS segment is: 0xc000 >(--) RADEON(0): Chipset: "ATI Radeon 9600 AP (AGP)" (ChipID = 0x4150) >(--) RADEON(0): Linear framebuffer at 0xc0000000 >(II) RADEON(0): AGP card detected >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 7, (OK) >drmOpenByBusid: Searching for BusID pci:0000:02:00.0 >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 7, (OK) >drmOpenByBusid: drmOpenMinor returns 7 >drmOpenByBusid: drmGetBusid reports pci:0000:02:00.0 >(II) RADEON(0): [dri] Found DRI library version 1.3.0 and kernel module version 1.27.0 >(II) RADEON(0): AGP Fast Write disabled by default >(II) Loading sub module "shadowfb" >(II) LoadModule: "shadowfb" >(II) Loading /usr/lib/xorg/modules//libshadowfb.so >(II) Module shadowfb: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org ANSI C Emulation, version 0.3 >(II) RADEON(0): Page flipping disabled >(II) RADEON(0): Will try to use DMA for Xv image transfers >(II) RADEON(0): Generation 2 PCI interface, using max accessible memory >(II) RADEON(0): Detected total video RAM=131072K, accessible=262144K (PCI BAR=262144K) >(--) RADEON(0): Mapped VideoRAM: 131072 kByte (128 bit DDR SDRAM) >(II) RADEON(0): Color tiling enabled by default >(II) Loading sub module "ddc" >(II) LoadModule: "ddc"(II) Module "ddc" already built-in >(II) Loading sub module "i2c" >(II) LoadModule: "i2c"(II) Module "i2c" already built-in >(II) RADEON(0): I2C bus "DDC" initialized. >(II) RADEON(0): Legacy BIOS detected >(II) RADEON(0): Connector0: DDCType-2, DACType-1, TMDSType-0, ConnectorType-3 >(II) RADEON(0): Connector1: DDCType-3, DACType-0, TMDSType--1, ConnectorType-2 >(II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. >(II) RADEON(0): DDC Type: 2, Detected Type: 3 >(II) RADEON(0): I2C device "DDC:ddc2" removed. >(II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. >(II) RADEON(0): I2C device "DDC:ddc2" removed. >(II) RADEON(0): I2C device "DDC:ddc2" registered at address 0xA0. >(II) RADEON(0): I2C device "DDC:ddc2" removed. >(II) RADEON(0): DDC Type: 3, Detected Type: 0 >(II) RADEON(0): EDID data from the display on port 1 ---------------------- >(II) RADEON(0): Manufacturer: SAM Model: ed Serial#: 1145647417 >(II) RADEON(0): Year: 2004 Week: 43 >(II) RADEON(0): EDID Version: 1.3 >(II) RADEON(0): Digital Display Input >(II) RADEON(0): Max H-Image Size [cm]: horiz.: 38 vert.: 30 >(II) RADEON(0): Gamma: 2.20 >(II) RADEON(0): DPMS capabilities: Off; RGB/Color Display >(II) RADEON(0): First detailed timing is preferred mode >(II) RADEON(0): redX: 0.640 redY: 0.330 greenX: 0.300 greenY: 0.600 >(II) RADEON(0): blueX: 0.150 blueY: 0.060 whiteX: 0.313 whiteY: 0.329 >(II) RADEON(0): Supported VESA Video Modes: >(II) RADEON(0): 720x400@70Hz >(II) RADEON(0): 640x480@60Hz >(II) RADEON(0): 640x480@67Hz >(II) RADEON(0): 640x480@72Hz >(II) RADEON(0): 640x480@75Hz >(II) RADEON(0): 800x600@56Hz >(II) RADEON(0): 800x600@60Hz >(II) RADEON(0): 800x600@72Hz >(II) RADEON(0): 800x600@75Hz >(II) RADEON(0): 832x624@75Hz >(II) RADEON(0): 1024x768@60Hz >(II) RADEON(0): 1024x768@70Hz >(II) RADEON(0): 1024x768@75Hz >(II) RADEON(0): 1280x1024@75Hz >(II) RADEON(0): 1152x870@75Hz >(II) RADEON(0): Manufacturer's mask: 0 >(II) RADEON(0): Supported Future Video Modes: >(II) RADEON(0): #0: hsize: 1280 vsize 1024 refresh: 60 vid: 32897 >(II) RADEON(0): #1: hsize: 1152 vsize 864 refresh: 75 vid: 20337 >(II) RADEON(0): Supported additional Video Mode: >(II) RADEON(0): clock: 108.0 MHz Image Size: 376 x 301 mm >(II) RADEON(0): h_active: 1280 h_sync: 1328 h_sync_end 1440 h_blank_end 1688 h_border: 0 >(II) RADEON(0): v_active: 1024 v_sync: 1025 v_sync_end 1028 v_blanking: 1066 v_border: 0 >(II) RADEON(0): Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 81 kHz, PixClock max 140 MHz >(II) RADEON(0): Monitor name: SyncMaster >(II) RADEON(0): Serial No: H4JXA03930 >(II) RADEON(0): EDID (in hex): >(II) RADEON(0): 00ffffffffffff004c2ded0039314944 >(II) RADEON(0): 2b0e010380261e782aee95a3544c9926 >(II) RADEON(0): 0f5054bfef808180714f010101010101 >(II) RADEON(0): 010101010101302a009851002a403070 >(II) RADEON(0): 1300782d1100001e000000fd00384c1e >(II) RADEON(0): 510e000a202020202020000000fc0053 >(II) RADEON(0): 796e634d61737465720a2020000000ff >(II) RADEON(0): 0048344a584130333933300a202000e1 >(II) RADEON(0): >(II) RADEON(0): Primary: > Monitor -- TMDS > Connector -- DVI-I > DAC Type -- TVDAC/ExtDAC > TMDS Type -- Internal > DDC Type -- DVI_DDC >(II) RADEON(0): Secondary: > Monitor -- NONE > Connector -- VGA > DAC Type -- Primary > TMDS Type -- NONE > DDC Type -- VGA_DDC >(II) RADEON(0): PLL parameters: rf=2700 rd=12 min=20000 max=40000; xclk=30000 >(WW) RADEON(0): Failed to detect secondary monitor, MergedFB/Clone mode disabled >(==) RADEON(0): Using gamma correction (1.0, 1.0, 1.0) >(II) RADEON(0): Validating modes on Primary head --------- >(II) RADEON(0): DFP table revision: 3 >(II) RADEON(0): Panel infos found from DDC detailed: 1280x1024 >(II) RADEON(0): Valid Mode from Detailed timing table: 1280x1024 >(II) RADEON(0): Valid Mode from standard timing table: 1280x1024 >(II) RADEON(0): Valid Mode from standard timing table: 1152x864 >(II) RADEON(0): Valid Mode from established timing table: 1280x1024 >(II) RADEON(0): Valid Mode from established timing table: 1024x768 >(II) RADEON(0): Valid Mode from established timing table: 1024x768 >(II) RADEON(0): Valid Mode from established timing table: 1024x768 >(II) RADEON(0): Valid Mode from established timing table: 832x624 >(II) RADEON(0): Valid Mode from established timing table: 800x600 >(II) RADEON(0): Valid Mode from established timing table: 800x600 >(II) RADEON(0): Valid Mode from established timing table: 800x600 >(II) RADEON(0): Valid Mode from established timing table: 800x600 >(II) RADEON(0): Valid Mode from established timing table: 640x480 >(II) RADEON(0): Valid Mode from established timing table: 640x480 >(II) RADEON(0): Valid Mode from established timing table: 640x480 >(II) RADEON(0): Total of 15 mode(s) found. >(II) RADEON(0): Total number of valid DDC mode(s) found: 15 >(--) RADEON(0): Virtual size is 1280x1024 (pitch 1280) >(**) RADEON(0): *Default mode "1280x1024": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "1280x1024": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "1280x1024": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1280x1024"x0.0 108.00 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "1152x864": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1152x864"x0.0 108.00 1152 1328 1440 1688 864 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "1024x768": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1024x768"x0.0 108.00 1024 1328 1440 1688 768 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "1024x768": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1024x768"x0.0 108.00 1024 1328 1440 1688 768 1025 1028 1066 -hsync -vsync (64.0 kHz) >(**) RADEON(0): *Default mode "1024x768": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "1024x768"x0.0 108.00 1024 1328 1440 1688 768 1025 1028 1066 -hsync -vsync (64.0 kHz) >(**) RADEON(0): *Default mode "832x624": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "832x624"x0.0 108.00 832 1328 1440 1688 624 1025 1028 1066 -hsync -vsync (64.0 kHz) >(**) RADEON(0): *Default mode "800x600": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "800x600"x0.0 108.00 800 1328 1440 1688 600 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "800x600": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "800x600"x0.0 108.00 800 1328 1440 1688 600 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "800x600": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "800x600"x0.0 108.00 800 1328 1440 1688 600 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "800x600": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "800x600"x0.0 108.00 800 1328 1440 1688 600 1025 1028 1066 +hsync +vsync (64.0 kHz) >(**) RADEON(0): *Default mode "640x480": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "640x480"x0.0 108.00 640 1328 1440 1688 480 1025 1028 1066 -hsync -vsync (64.0 kHz) >(**) RADEON(0): *Default mode "640x480": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "640x480"x0.0 108.00 640 1328 1440 1688 480 1025 1028 1066 -hsync -vsync (64.0 kHz) >(**) RADEON(0): *Default mode "640x480": 108.0 MHz (scaled from 0.0 MHz), 64.0 kHz, 60.0 Hz >(II) RADEON(0): Modeline "640x480"x0.0 108.00 640 1328 1440 1688 480 1025 1028 1066 -hsync -vsync (64.0 kHz) >(--) RADEON(0): Display dimensions: (380, 300) mm >(--) RADEON(0): DPI set to (85, 86) >(II) Loading sub module "fb" >(II) LoadModule: "fb" >(II) Loading /usr/lib/xorg/modules//libfb.so >(II) Module fb: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org ANSI C Emulation, version 0.3 >(II) Loading sub module "ramdac" >(II) LoadModule: "ramdac"(II) Module "ramdac" already built-in >(==) RADEON(0): Using XAA acceleration architecture >(II) Loading sub module "xaa" >(II) LoadModule: "xaa" >(II) Loading /usr/lib/xorg/modules//libxaa.so >(II) Module xaa: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.2.0 > ABI class: X.Org Video Driver, version 2.0 >(II) RADEON(0): No MM_TABLE found - assuming CARD is not TV-in capable. >(!!) RADEON(0): For information on using the multimedia capabilities > of this adapter, please see http://gatos.sf.net. >(II) UnloadModule: "fbdev" >(II) Unloading /usr/lib/xorg/modules/drivers//fbdev_drv.so >(II) UnloadModule: "fbdevhw" >(II) Unloading /usr/lib/xorg/modules/linux//libfbdevhw.so >(II) UnloadModule: "vesa" >(II) Unloading /usr/lib/xorg/modules/drivers//vesa_drv.so >(--) Depth 24 pixmap format is 32 bpp >(II) do I need RAC? No, I don't. >(II) resource ranges after preInit: > [0] 0 0 0xe5000000 - 0xe500ffff (0x10000) MX[B] > [1] 0 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B] > [2] -1 0 0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B) > [3] -1 0 0x000f0000 - 0x000fffff (0x10000) MX[B] > [4] -1 0 0x000c0000 - 0x000effff (0x30000) MX[B] > [5] -1 0 0x00000000 - 0x0009ffff (0xa0000) MX[B] > [6] -1 0 0xe6001000 - 0xe6001fff (0x1000) MX[B] > [7] -1 0 0xe6000000 - 0xe60000ff (0x100) MX[B] > [8] -1 0 0xe6003000 - 0xe6003fff (0x1000) MX[B] > [9] -1 0 0xe6002000 - 0xe6002fff (0x1000) MX[B] > [10] -1 0 0xe0000000 - 0xdfffffff (0x0) MX[B]O > [11] -1 0 0xe5000000 - 0xe500ffff (0x10000) MX[B](B) > [12] -1 0 0xc0000000 - 0xcfffffff (0x10000000) MX[B](B) > [13] -1 0 0xe5010000 - 0xe501ffff (0x10000) MX[B](B) > [14] -1 0 0xd0000000 - 0xdfffffff (0x10000000) MX[B](B) > [15] 0 0 0x000a0000 - 0x000affff (0x10000) MS[B](OprU) > [16] 0 0 0x000b0000 - 0x000b7fff (0x8000) MS[B](OprU) > [17] 0 0 0x000b8000 - 0x000bffff (0x8000) MS[B](OprU) > [18] 0 0 0x0000d000 - 0x0000d0ff (0x100) IX[B] > [19] -1 0 0x0000ffff - 0x0000ffff (0x1) IX[B] > [20] -1 0 0x00000000 - 0x000000ff (0x100) IX[B] > [21] -1 0 0x0000c400 - 0x0000c407 (0x8) IX[B] > [22] -1 0 0x0000c000 - 0x0000c01f (0x20) IX[B] > [23] -1 0 0x0000f000 - 0x0000f00f (0x10) IX[B] > [24] -1 0 0x0000e400 - 0x0000e407 (0x8) IX[B] > [25] -1 0 0x0000e000 - 0x0000e01f (0x20) IX[B] > [26] -1 0 0x0000d000 - 0x0000d0ff (0x100) IX[B](B) > [27] 0 0 0x000003b0 - 0x000003bb (0xc) IS[B](OprU) > [28] 0 0 0x000003c0 - 0x000003df (0x20) IS[B](OprU) >(**) RADEON(0): RADEONScreenInit c0000000 0 >(**) RADEON(0): Map: 0xc0000000, 0x08000000 >(==) RADEON(0): Write-combining range (0xc0000000,0x8000000) >(**) RADEON(0): RADEONSave >(**) RADEON(0): RADEONSaveMode(0x8228398) >(**) RADEON(0): Read: 0x00080002 0x00040018 0x00000000 >(**) RADEON(0): Read: rd=2, fd=24, pd=4 >(**) RADEON(0): RADEONSaveMode returns 0x8228398 >(==) RADEON(0): Using 24 bit depth buffer >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 7, (OK) >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 7, (OK) >drmOpenByBusid: Searching for BusID pci:0000:02:00.0 >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 7, (OK) >drmOpenByBusid: drmOpenMinor returns 7 >drmOpenByBusid: drmGetBusid reports pci:0000:02:00.0 >(II) [drm] DRM interface version 1.3 >(II) [drm] DRM open master succeeded. >(II) RADEON(0): [drm] Using the DRM lock SAREA also for drawables. >(II) RADEON(0): [drm] framebuffer handle = 0xc0000000 >(II) RADEON(0): [drm] added 1 reserved context for kernel >(II) RADEON(0): X context handle = 0x1 >(II) RADEON(0): [drm] installed DRM signal handler >(II) RADEON(0): [agp] Mode 0x1f004209 [AGP 0x10de/0x01e0; Card 0x1002/0x4150] >(II) RADEON(0): [agp] 8192 kB allocated with handle 0x00000001 >(II) RADEON(0): [agp] ring handle = 0xe0000000 >(II) RADEON(0): [agp] Ring mapped at 0xaf8a8000 >(II) RADEON(0): [agp] ring read ptr handle = 0xe0101000 >(II) RADEON(0): [agp] Ring read ptr mapped at 0xb7f75000 >(II) RADEON(0): [agp] vertex/indirect buffers handle = 0xe0102000 >(II) RADEON(0): [agp] Vertex/indirect buffers mapped at 0xaf6a8000 >(II) RADEON(0): [agp] GART texture map handle = 0xe0302000 >(II) RADEON(0): [agp] GART Texture map mapped at 0xaf1c8000 >(II) RADEON(0): [drm] register handle = 0xe5000000 >(II) RADEON(0): [dri] Visual configs initialized >(**) RADEON(0): DRI New memory map param >(**) RADEON(0): RADEONInitMemoryMap() : >(**) RADEON(0): mem_size : 0x08000000 >(**) RADEON(0): MC_FB_LOCATION : 0xc7ffc000 >(**) RADEON(0): MC_AGP_LOCATION : 0xffffffc0 >(**) RADEON(0): RADEONModeInit() >1280x1024 108.00 1280 1328 1440 1688 1024 1025 1028 1066 (24,32) +H +V >1280x1024 108.00 1280 1328 1440 1688 1024 1025 1028 1066 (24,32) +H +V >(**) RADEON(0): Pitch = 10485920 bytes (virtualX = 1280, displayWidth = 1280) >(**) RADEON(0): dc=10800, of=21600, fd=96, pd=2 >(**) RADEON(0): TMDS_PLL from 1fbb0155 to 1fbb0155 >(II) RADEON(0): BIOS HotKeys Disabled >(**) RADEON(0): RADEONInit returns 0x8228d48 >(**) RADEON(0): RADEONRestoreMode() >(**) RADEON(0): RADEONRestoreMode(0x8228d48) >(**) RADEON(0): RADEONRestoreMemMapRegisters() : >(**) RADEON(0): MC_FB_LOCATION : 0xc7ffc000 >(**) RADEON(0): MC_AGP_LOCATION : 0xffffffc0 >(**) RADEON(0): Map Changed ! Applying ... >(**) RADEON(0): Map applied, resetting engine ... >(**) RADEON(0): Updating display base addresses... >(**) RADEON(0): Memory map updated. >(**) RADEON(0): Programming CRTC1, offset: 0x00000000 >(**) RADEON(0): Wrote: 0x0000000c 0x00010060 0x00000000 (0x0000bf00) >(**) RADEON(0): Wrote: rd=12, fd=96, pd=1 >(**) RADEON(0): GRPH_BUFFER_CNTL from 30004c4c to 201a7c7c >(**) RADEON(0): RADEONSaveScreen(0) >(II) RADEON(0): Depth moves disabled by default >(**) RADEON(0): Setting up initial surfaces >(**) RADEON(0): Initializing fb layer >(**) RADEON(0): Setting up accel memmap >(II) RADEON(0): CP in BM mode >(II) RADEON(0): Using 8 MB GART aperture >(II) RADEON(0): Using 1 MB for the ring buffer >(II) RADEON(0): Using 2 MB for vertex/indirect buffers >(II) RADEON(0): Using 5 MB for GART textures >(II) RADEON(0): Memory manager initialized to (0,0) (1280,8191) >(II) RADEON(0): Reserved area from (0,1024) to (1280,1026) >(II) RADEON(0): Largest offscreen area available: 1280 x 7165 >(II) RADEON(0): Will use back buffer at offset 0x1400000 >(II) RADEON(0): Will use depth buffer at offset 0x1900000 >(II) RADEON(0): Will use 100352 kb for textures at offset 0x1e00000 >(**) RADEON(0): Initializing backing store >(==) RADEON(0): Backing store disabled >(**) RADEON(0): DRI Finishing init ! >(II) RADEON(0): [DRI] installation complete >(**) RADEON(0): EngineRestore (32/32) >(II) RADEON(0): [drm] Added 32 65536 byte vertex/indirect buffers >(II) RADEON(0): [drm] Mapped 32 vertex/indirect buffers >(II) RADEON(0): [drm] dma control initialized, using IRQ 16 >(II) RADEON(0): [drm] Initialized kernel GART heap manager, 5111808 >(WW) RADEON(0): DRI init changed memory map, adjusting ... >(WW) RADEON(0): MC_FB_LOCATION was: 0xc7ffc000 is: 0xc7ffc000 >(WW) RADEON(0): MC_AGP_LOCATION was: 0xffffffc0 is: 0xe07fe000 >(**) RADEON(0): GRPH_BUFFER_CNTL from 30004c4c to 201a7c7c >(II) RADEON(0): Direct rendering enabled >(**) RADEON(0): Setting up final surfaces >(**) RADEON(0): Initializing Acceleration >(II) RADEON(0): Render acceleration unsupported on Radeon 9500/9700 and newer. >(II) RADEON(0): Render acceleration disabled >(**) RADEON(0): EngineInit (32/32) >(**) RADEON(0): Pitch for acceleration = 160 >(**) RADEON(0): EngineRestore (32/32) >(II) RADEON(0): Using XFree86 Acceleration Architecture (XAA) > Screen to screen bit blits > Solid filled rectangles > 8x8 mono pattern filled rectangles > Indirect CPU to Screen color expansion > Solid Lines > Scanline Image Writes > Offscreen Pixmaps > Setting up tile and stipple cache: > 32 128x128 slots > 32 256x256 slots > 16 512x512 slots >(II) RADEON(0): Acceleration enabled >(**) RADEON(0): Initializing DPMS >(**) RADEON(0): Initializing Cursor >(==) RADEON(0): Silken mouse enabled >(II) RADEON(0): Using hardware cursor (scanline 1026) >(II) RADEON(0): Largest offscreen area available: 1280 x 7161 >(**) RADEON(0): Initializing color map >(**) RADEON(0): Initializing DGA >(**) RADEON(0): Initializing Xv >(II) RADEON(0): No video input capabilities detected and no information is provided - disabling multimedia i2c >(II) Loading sub module "theatre_detect" >(II) LoadModule: "theatre_detect" >(II) Loading /usr/lib/xorg/modules/multimedia//theatre_detect_drv.so >(II) Module theatre_detect: vendor="X.Org Foundation" > compiled for 1.4.0, module version = 1.0.0 > ABI class: X.Org Video Driver, version 2.0 >(II) RADEON(0): no multimedia table present, disabling Rage Theatre. >(**) RADEON(0): RADEONScreenInit finished >(==) RandR enabled >(II) Initializing built-in extension MIT-SHM >(II) Initializing built-in extension XInputExtension >(II) Initializing built-in extension XTEST >(II) Initializing built-in extension XKEYBOARD >(II) Initializing built-in extension XC-APPGROUP >(II) Initializing built-in extension XAccessControlExtension >(II) Initializing built-in extension SECURITY >(II) Initializing built-in extension XINERAMA >(II) Initializing built-in extension XFIXES >(II) Initializing built-in extension XFree86-Bigfont >(II) Initializing built-in extension RENDER >(II) Initializing built-in extension RANDR >(II) Initializing built-in extension COMPOSITE >(II) Initializing built-in extension DAMAGE >(II) Initializing built-in extension XEVIE >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 8, (OK) >drmOpenByBusid: Searching for BusID pci:0000:02:00.0 >drmOpenDevice: node name is /dev/dri/card0 >drmOpenDevice: open result is 8, (OK) >drmOpenByBusid: drmOpenMinor returns 8 >drmOpenByBusid: drmGetBusid reports pci:0000:02:00.0 >(WW) AIGLX: 3D driver claims to not support visual 0x23 >(WW) AIGLX: 3D driver claims to not support visual 0x24 >(WW) AIGLX: 3D driver claims to not support visual 0x25 >(WW) AIGLX: 3D driver claims to not support visual 0x26 >(WW) AIGLX: 3D driver claims to not support visual 0x27 >(WW) AIGLX: 3D driver claims to not support visual 0x28 >(WW) AIGLX: 3D driver claims to not support visual 0x29 >(WW) AIGLX: 3D driver claims to not support visual 0x2a >(WW) AIGLX: 3D driver claims to not support visual 0x2b >(WW) AIGLX: 3D driver claims to not support visual 0x2c >(WW) AIGLX: 3D driver claims to not support visual 0x2d >(WW) AIGLX: 3D driver claims to not support visual 0x2e >(WW) AIGLX: 3D driver claims to not support visual 0x2f >(WW) AIGLX: 3D driver claims to not support visual 0x30 >(WW) AIGLX: 3D driver claims to not support visual 0x31 >(WW) AIGLX: 3D driver claims to not support visual 0x32 >(II) AIGLX: Loaded and initialized /usr/lib/dri/r300_dri.so >(II) GLX: Initialized DRI GL provider for screen 0 >(WW) <default pointer>: No Device specified, looking for one... >(II) <default pointer>: Setting Device option to "/dev/input/mice" >(--) <default pointer>: Device: "/dev/input/mice" >(==) <default pointer>: Protocol: "Auto" >(**) Option "CorePointer" >(**) <default pointer>: always reports core events >(==) <default pointer>: Emulate3Buttons, Emulate3Timeout: 50 >(**) <default pointer>: ZAxisMapping: buttons 4 and 5 >(**) <default pointer>: Buttons: 9 >(**) <default pointer>: Sensitivity: 1 >(**) Option "CoreKeyboard" >(**) <default keyboard>: always reports core events >(**) Option "Protocol" "standard" >(**) <default keyboard>: Protocol: standard >(**) Option "AutoRepeat" "500 30" >(**) Option "XkbRules" "xorg" >(**) <default keyboard>: XkbRules: "xorg" >(**) Option "XkbModel" "pc105" >(**) <default keyboard>: XkbModel: "pc105" >(**) Option "XkbLayout" "us" >(**) <default keyboard>: XkbLayout: "us" >(**) Option "CustomKeycodes" "off" >(**) <default keyboard>: CustomKeycodes disabled >(II) evaluating device (<default keyboard>) >(II) XINPUT: Adding extended input device "<default keyboard>" (type: KEYBOARD) >(II) evaluating device (<default pointer>) >(II) XINPUT: Adding extended input device "<default pointer>" (type: MOUSE) >(--) <default pointer>: PnP-detected protocol: "ExplorerPS/2" >(II) <default pointer>: ps2EnableDataReporting: succeeded >(**) RADEON(0): RADEONSaveScreen(2) >SetClientVersion: 0 9 >SetKbdSettings - type: -1216459046 rate: 30 delay: 500 snumlk: 172 >(II) 3rd Button detected: disabling emulate3Button >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): EngineRestore (32/32) >(**) RADEON(0): RADEONSwitchMode() !n(**) RADEON(0): RADEONModeInit() >800x600 108.00 800 1328 1440 1688 600 1025 1028 1066 (24,32) +H +V >800x600 108.00 800 1328 1440 1688 600 1025 1028 1066 (24,32) +H +V >(**) RADEON(0): Pitch = 10485920 bytes (virtualX = 1280, displayWidth = 1280) >(**) RADEON(0): dc=10800, of=21600, fd=96, pd=2 >(**) RADEON(0): TMDS_PLL from 1fbb0155 to 1fbb0155 >(II) RADEON(0): BIOS HotKeys Disabled >(**) RADEON(0): RADEONInit returns 0x8228d48 >(**) RADEON(0): RADEONRestoreMode() >(**) RADEON(0): RADEONRestoreMode(0x8228d48) >(**) RADEON(0): RADEONRestoreMemMapRegisters() : >(**) RADEON(0): MC_FB_LOCATION : 0xc7ffc000 >(**) RADEON(0): MC_AGP_LOCATION : 0xe07fe000 >(**) RADEON(0): Updating display base addresses... >(**) RADEON(0): Memory map updated. >(**) RADEON(0): Programming CRTC1, offset: 0x00000000 >(**) RADEON(0): Wrote: 0x0000000c 0x00010060 0x00000000 (0x0000bf00) >(**) RADEON(0): Wrote: rd=12, fd=96, pd=1 >(**) RADEON(0): GRPH_BUFFER_CNTL from 30004c4c to 201a7c7c >(**) RADEON(0): EngineRestore (32/32) >(**) RADEON(0): EngineRestore (32/32) >(**) RADEON(0): RADEONSwitchMode() !n(**) RADEON(0): RADEONModeInit() >1280x1024 108.00 1280 1328 1440 1688 1024 1025 1028 1066 (24,32) +H +V >1280x1024 108.00 1280 1328 1440 1688 1024 1025 1028 1066 (24,32) +H +V >(**) RADEON(0): Pitch = 10485920 bytes (virtualX = 1280, displayWidth = 1280) >(**) RADEON(0): dc=10800, of=21600, fd=96, pd=2 >(**) RADEON(0): TMDS_PLL from 1fbb0155 to 1fbb0155 >(II) RADEON(0): BIOS HotKeys Disabled >(**) RADEON(0): RADEONInit returns 0x8228d48 >(**) RADEON(0): RADEONRestoreMode() >(**) RADEON(0): RADEONRestoreMode(0x8228d48) >(**) RADEON(0): RADEONRestoreMemMapRegisters() : >(**) RADEON(0): MC_FB_LOCATION : 0xc7ffc000 >(**) RADEON(0): MC_AGP_LOCATION : 0xe07fe000 >(**) RADEON(0): Updating display base addresses... >(**) RADEON(0): Memory map updated. >(**) RADEON(0): Programming CRTC1, offset: 0x00000000 >(**) RADEON(0): Wrote: 0x0000000c 0x00010060 0x00000000 (0x0000bf00) >(**) RADEON(0): Wrote: rd=12, fd=96, pd=1 >(**) RADEON(0): GRPH_BUFFER_CNTL from 30004c4c to 201a7c7c >(**) RADEON(0): EngineRestore (32/32) >(**) RADEON(0): RADEONSaveScreen(0) >(**) RADEON(0): RADEONSaveScreen(1) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONSaveScreen(0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(1,0x0) >(**) RADEON(0): RADEONSaveScreen(2) >(**) RADEON(0): RADEONDisplayPowerManagementSet(2,0x0) >(**) RADEON(0): RADEONSaveScreen(1) >(**) RADEON(0): RADEONDisplayPowerManagementSet(0,0x0)
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