Attachment #119507 for bug #174063




	host_path_cntl = INREG(HOST_PATH_CNTL);
	rbbm_soft_reset = INREG(RBBM_SOFT_RESET);

	if (IS_R300_VARIANT(rinfo)) {
	    rinfo->family == CHIP_FAMILY_R350 ||
	    rinfo->family == CHIP_FAMILY_RV350) {
		u32 tmp;

		OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset |

	INREG(HOST_PATH_CNTL);
	OUTREG(HOST_PATH_CNTL, host_path_cntl);

	if (IS_R300_VARIANT(rinfo))
	    rinfo->family != CHIP_FAMILY_R350 ||
	    rinfo->family != CHIP_FAMILY_RV350)
		OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);

	OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);

{
	unsigned long temp;

	/* disable 3D engine */
	OUTREG(RB3D_CNTL, 0);

	radeonfb_engine_reset(rinfo);

	radeon_fifo_wait (1);
	if (IS_R300_VARIANT(rinfo)) {
		temp = INREG(RB2D_DSTCACHE_MODE);
		OUTREG(RB2D_DSTCACHE_MODE, temp | (1<<17)); /* FIXME */
	} else {
		OUTREG(RB2D_DSTCACHE_MODE, 0);
	}

	radeon_fifo_wait (3);
	/* We re-read MC_FB_LOCATION from card as it can have been




	return 0;
}

static void radeon_detect_bios_type(struct radeonfb_info *rinfo)
{
#ifndef CONFIG_PPC_OF
          int offset = rinfo->fp_bios_start + 4;
          unsigned char sign[4];

                  sign[0] = BIOS_IN8(offset);
                  sign[1] = BIOS_IN8(offset + 1);
                  sign[2] = BIOS_IN8(offset + 2);
                  sign[3] = BIOS_IN8(offset + 3);

          if (!memcmp(sign, "ATOM", 4) || !memcmp(sign, "MOTA", 4)) {
                rinfo->is_atom_bios = 1;
                rinfo->atom_data_start = BIOS_IN16(rinfo->fp_bios_start + 32);

       		printk(KERN_INFO "radeonfb: ATOM BIOS signature found\n");

		return;
          } 
#endif  /* NOT CONFIG_PPC_OF */

          rinfo->is_atom_bios = 0;

	  return;
}

/*
 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
 */

#endif /* CONFIG_PPC_OF || CONFIG_SPARC */

	/*
	 * Check out if we have an ATOM BIOS which gave us some PLL informations
	 * and if yes, retrieve them
	 */

	if (!force_measure_pll && rinfo->bios_seg) {
        	u16 pll_info_block;

		if(rinfo->is_atom_bios) {
        		pll_info_block = BIOS_IN16(rinfo->atom_data_start + 12);
		rinfo->pll.ref_clk	= BIOS_IN16(pll_info_block + 0x0e);
		rinfo->pll.ref_div	= BIOS_IN16(pll_info_block + 0x10);
		rinfo->pll.ppll_min	= BIOS_IN32(pll_info_block + 0x12);
		rinfo->pll.ppll_max	= BIOS_IN32(pll_info_block + 0x16);

        		rinfo->pll.sclk = BIOS_IN32(pll_info_block + 8);
        		rinfo->pll.mclk = BIOS_IN32(pll_info_block + 12);
        		rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 82);
        		rinfo->pll.ref_div = 0; /* Have to get it elsewhere */
        		rinfo->pll.ppll_min = BIOS_IN16(pll_info_block + 78);
        		rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 32);
		} else {
	/*
	 * Check out if we have an X86 which gave us some PLL informations
	 * and if yes, retrieve them
	 */
			pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);

			rinfo->pll.sclk		= BIOS_IN16(pll_info_block + 0x08);
			rinfo->pll.mclk		= BIOS_IN16(pll_info_block + 0x0a);
			rinfo->pll.ref_clk	= BIOS_IN16(pll_info_block + 0x0e);
			rinfo->pll.ref_div	= BIOS_IN16(pll_info_block + 0x10);
			rinfo->pll.ppll_min	= BIOS_IN32(pll_info_block + 0x12);
			rinfo->pll.ppll_max	= BIOS_IN32(pll_info_block + 0x16);
		}
		printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");

		goto found;
	}


	/*
	 * Fall back to already-set defaults...
	 */
       	printk(KERN_INFO "radeonfb: Fall back to default PLL infos\n");

found:
       /* Check and fix-up the PLL divisor if necessary */
        if (rinfo->pll.ref_div < 2) {
                int tmp = INPLL(PPLL_REF_DIV);
                if (rinfo->family == CHIP_FAMILY_RS300) {
                        rinfo->pll.ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
                } else {
                        rinfo->pll.ref_div = tmp & PPLL_REF_DIV_MASK;
                }

                /* Sane default */
                if (rinfo->pll.ref_div < 2) {
       			printk(KERN_INFO "radeonfb: Set a sane default PLL divisor\n");
                        rinfo->pll.ref_div = 12;
                }
        }

	/*
	 * Some methods fail to retrieve SCLK and MCLK values, we apply default
	 * settings in this case (200Mhz). If that really happen often, we could
	 * fetch from registers instead...
	 */
	if (rinfo->pll.mclk == 0) {
       		printk(KERN_INFO "radeonfb: Set a sane default MCLK value\n");
		rinfo->pll.mclk = 20000;
	}
	if (rinfo->pll.mclk == 0) {
       		printk(KERN_INFO "radeonfb: Set a sane default SCLK value\n");
		rinfo->pll.sclk = 20000;
	}

	printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
	       rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,

	if (rinfo->bios_seg == NULL && rinfo->is_mobility)
		radeon_map_ROM(rinfo, pdev);

        /* Check BIOS Type */
        radeon_detect_bios_type(rinfo);

	/* Get informations about the board's PLL */
	radeon_get_pllinfo(rinfo);



        radeonfb_bl_exit(rinfo);

        radeonfb_bl_exit(rinfo);

        iounmap(rinfo->mmio_base);
        iounmap(rinfo->fb_base);
 

Lines 301-306 Link Here

(-)radeonfb.h.ori (+3 lines)
301	void __iomem *bios_seg;	301	void __iomem *bios_seg;
302	int fp_bios_start;	302	int fp_bios_start;
303		303
		304	int is_atom_bios;
		305	int atom_data_start;
		306
304	u32 pseudo_palette[17];	307	u32 pseudo_palette[17];
305	struct { u8 red, green, blue, pad; }	308	struct { u8 red, green, blue, pad; }
306	palette[256];	309	palette[256];




		
		RTRACE("Starting monitor auto detection...\n");

#if DEBUG && defined(CONFIG_FB_RADEON_I2C)
		{
			u8 *EDIDs[4] = { NULL, NULL, NULL, NULL };
			int mon_types[4] = {MT_NONE, MT_NONE, MT_NONE, MT_NONE};
			int i;

			for (i = 0; i < 4; i++)
				mon_types[i] = radeon_probe_i2c_connector(rinfo,
									  i+1, &EDIDs[i]);
		}
#endif /* DEBUG */
		/*
		 * Old single head cards
		 */

				if (!BIOS_IN8(tmp + i*2) && i > 1)
					break;
				tmp0 = BIOS_IN16(tmp + i*2);
				if ((!(tmp0 & 0x01)) && ((((tmp0 >> 8) & 0x0f) == ddc_dvi) || (((tmp0 >> 8) & 0x0f) == ddc_monid))) {
					rinfo->reversed_DAC = 1;
					printk(KERN_INFO "radeonfb: Reversed DACs detected\n");
				}
				if ((((tmp0 >> 8) & 0x0f) == ddc_dvi || (((tmp0 >> 8) & 0x0f) == ddc_monid)) && ((tmp0 >> 4) & 0x01)) {
					rinfo->reversed_TMDS = 1;
					printk(KERN_INFO "radeonfb: Reversed TMDS detected\n");
				}

#endif /* CONFIG_PPC_OF || CONFIG_SPARC */
#ifdef CONFIG_FB_RADEON_I2C
		if (rinfo->mon1_type == MT_NONE)
			rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_monid,
								      &rinfo->mon1_EDID);
		if (rinfo->mon1_type == MT_NONE)
			rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi,
								      &rinfo->mon1_EDID);
		if (rinfo->mon1_type == MT_NONE) {



/*
 * This functions applies any arch/model/machine specific fixups
 * to the panel info. It may eventually alter EDID block as
 * well or whatever is specific to a given model and not probed
 * properly by the default code

Return to bug 174063

Lines 203-211 Link Here

(-)radeon_accel.c.ori (-12 / +7 lines)
203	host_path_cntl = INREG(HOST_PATH_CNTL);	203	host_path_cntl = INREG(HOST_PATH_CNTL);
204	rbbm_soft_reset = INREG(RBBM_SOFT_RESET);	204	rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
205		205
206	if (rinfo->family == CHIP_FAMILY_R300 \|\|	206	if (IS_R300_VARIANT(rinfo)) {
207	rinfo->family == CHIP_FAMILY_R350 \|\|
208	rinfo->family == CHIP_FAMILY_RV350) {
209	u32 tmp;	207	u32 tmp;
210		208
211	OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset \|	209	OUTREG(RBBM_SOFT_RESET, (rbbm_soft_reset \|
Lines 241-249 Link Here
241	INREG(HOST_PATH_CNTL);	239	INREG(HOST_PATH_CNTL);
242	OUTREG(HOST_PATH_CNTL, host_path_cntl);	240	OUTREG(HOST_PATH_CNTL, host_path_cntl);
243		241
244	if (rinfo->family != CHIP_FAMILY_R300 \|\|	242	if (IS_R300_VARIANT(rinfo))
245	rinfo->family != CHIP_FAMILY_R350 \|\|
246	rinfo->family != CHIP_FAMILY_RV350)
247	OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);	243	OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
248		244
249	OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);	245	OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
Lines 254-269 Link Here
254	{	250	{
255	unsigned long temp;	251	unsigned long temp;
256		252
257	/* disable 3D engine */
258	OUTREG(RB3D_CNTL, 0);
259
260	radeonfb_engine_reset(rinfo);	253	radeonfb_engine_reset(rinfo);
261		254
262	radeon_fifo_wait (1);	255	radeon_fifo_wait (1);
263	if ((rinfo->family != CHIP_FAMILY_R300) &&	256	if (IS_R300_VARIANT(rinfo)) {
264	(rinfo->family != CHIP_FAMILY_R350) &&	257	temp = INREG(RB2D_DSTCACHE_MODE);
265	(rinfo->family != CHIP_FAMILY_RV350))	258	OUTREG(RB2D_DSTCACHE_MODE, temp \| (1<<17)); /* FIXME */
		259	} else {
266	OUTREG(RB2D_DSTCACHE_MODE, 0);	260	OUTREG(RB2D_DSTCACHE_MODE, 0);
		261	}
267		262
268	radeon_fifo_wait (3);	263	radeon_fifo_wait (3);
269	/* We re-read MC_FB_LOCATION from card as it can have been	264	/* We re-read MC_FB_LOCATION from card as it can have been

Lines 582-587 Link Here

(-)radeon_base.c.ori (-12 / +81 lines)
582	return 0;	582	return 0;
583	}	583	}
584		584
		585	static void radeon_detect_bios_type(struct radeonfb_info *rinfo)
		586	{
		587	#ifndef CONFIG_PPC_OF
		588	int offset = rinfo->fp_bios_start + 4;
		589	unsigned char sign[4];
		590
		591	sign[0] = BIOS_IN8(offset);
		592	sign[1] = BIOS_IN8(offset + 1);
		593	sign[2] = BIOS_IN8(offset + 2);
		594	sign[3] = BIOS_IN8(offset + 3);
		595
		596	if (!memcmp(sign, "ATOM", 4) \|\| !memcmp(sign, "MOTA", 4)) {
		597	rinfo->is_atom_bios = 1;
		598	rinfo->atom_data_start = BIOS_IN16(rinfo->fp_bios_start + 32);
		599
		600	printk(KERN_INFO "radeonfb: ATOM BIOS signature found\n");
		601
		602	return;
		603	}
		604	#endif /* NOT CONFIG_PPC_OF */
		605
		606	rinfo->is_atom_bios = 0;
		607
		608	return;
		609	}
		610
585	/*	611	/*
586	* Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)	612	* Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
587	*/	613	*/
Lines 658-677 Link Here
658	#endif /* CONFIG_PPC_OF \|\| CONFIG_SPARC */	684	#endif /* CONFIG_PPC_OF \|\| CONFIG_SPARC */
659		685
660	/*	686	/*
661	* Check out if we have an X86 which gave us some PLL informations	687	* Check out if we have an ATOM BIOS which gave us some PLL informations
662	* and if yes, retrieve them	688	* and if yes, retrieve them
663	*/	689	*/
		690
664	if (!force_measure_pll && rinfo->bios_seg) {	691	if (!force_measure_pll && rinfo->bios_seg) {
665	u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);	692	u16 pll_info_block;
666		693
667	rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);	694	if(rinfo->is_atom_bios) {
668	rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);	695	pll_info_block = BIOS_IN16(rinfo->atom_data_start + 12);
669	rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
670	rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
671	rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
672	rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
673		696
		697	rinfo->pll.sclk = BIOS_IN32(pll_info_block + 8);
		698	rinfo->pll.mclk = BIOS_IN32(pll_info_block + 12);
		699	rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 82);
		700	rinfo->pll.ref_div = 0; /* Have to get it elsewhere */
		701	rinfo->pll.ppll_min = BIOS_IN16(pll_info_block + 78);
		702	rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 32);
		703	} else {
		704	/*
		705	* Check out if we have an X86 which gave us some PLL informations
		706	* and if yes, retrieve them
		707	*/
		708	pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
		709
		710	rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
		711	rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
		712	rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
		713	rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
		714	rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
		715	rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
		716	}
674	printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");	717	printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
		718
675	goto found;	719	goto found;
676	}	720	}
677		721
Lines 687-704 Link Here
687	/*	731	/*
688	* Fall back to already-set defaults...	732	* Fall back to already-set defaults...
689	*/	733	*/
690	printk(KERN_INFO "radeonfb: Used default PLL infos\n");	734	printk(KERN_INFO "radeonfb: Fall back to default PLL infos\n");
691		735
692	found:	736	found:
		737	/* Check and fix-up the PLL divisor if necessary */
		738	if (rinfo->pll.ref_div < 2) {
		739	int tmp = INPLL(PPLL_REF_DIV);
		740	if (rinfo->family == CHIP_FAMILY_RS300) {
		741	rinfo->pll.ref_div = (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> R300_PPLL_REF_DIV_ACC_SHIFT;
		742	} else {
		743	rinfo->pll.ref_div = tmp & PPLL_REF_DIV_MASK;
		744	}
		745
		746	/* Sane default */
		747	if (rinfo->pll.ref_div < 2) {
		748	printk(KERN_INFO "radeonfb: Set a sane default PLL divisor\n");
		749	rinfo->pll.ref_div = 12;
		750	}
		751	}
		752
693	/*	753	/*
694	* Some methods fail to retrieve SCLK and MCLK values, we apply default	754	* Some methods fail to retrieve SCLK and MCLK values, we apply default
695	* settings in this case (200Mhz). If that really happne often, we could	755	* settings in this case (200Mhz). If that really happen often, we could
696	* fetch from registers instead...	756	* fetch from registers instead...
697	*/	757	*/
698	if (rinfo->pll.mclk == 0)	758	if (rinfo->pll.mclk == 0) {
		759	printk(KERN_INFO "radeonfb: Set a sane default MCLK value\n");
699	rinfo->pll.mclk = 20000;	760	rinfo->pll.mclk = 20000;
700	if (rinfo->pll.sclk == 0)	761	}
		762	if (rinfo->pll.mclk == 0) {
		763	printk(KERN_INFO "radeonfb: Set a sane default SCLK value\n");
701	rinfo->pll.sclk = 20000;	764	rinfo->pll.sclk = 20000;
		765	}
702		766
703	printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",	767	printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
704	rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,	768	rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
Lines 2302-2307 Link Here
2302	if (rinfo->bios_seg == NULL && rinfo->is_mobility)	2366	if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2303	radeon_map_ROM(rinfo, pdev);	2367	radeon_map_ROM(rinfo, pdev);
2304		2368
		2369	/* Check BIOS Type */
		2370	radeon_detect_bios_type(rinfo);
		2371
2305	/* Get informations about the board's PLL */	2372	/* Get informations about the board's PLL */
2306	radeon_get_pllinfo(rinfo);	2373	radeon_get_pllinfo(rinfo);
2307		2374
Lines 2429-2434 Link Here
2429		2496
2430	radeonfb_bl_exit(rinfo);	2497	radeonfb_bl_exit(rinfo);
2431		2498
		2499	radeonfb_bl_exit(rinfo);
		2500
2432	iounmap(rinfo->mmio_base);	2501	iounmap(rinfo->mmio_base);
2433	iounmap(rinfo->fb_base);	2502	iounmap(rinfo->fb_base);
2434		2503

Lines 481-497 Link Here

(-)radeon_monitor.c.ori (-14 / +6 lines)
481		481
482	RTRACE("Starting monitor auto detection...\n");	482	RTRACE("Starting monitor auto detection...\n");
483		483
484	#if DEBUG && defined(CONFIG_FB_RADEON_I2C)
485	{
486	u8 *EDIDs[4] = { NULL, NULL, NULL, NULL };
487	int mon_types[4] = {MT_NONE, MT_NONE, MT_NONE, MT_NONE};
488	int i;
489
490	for (i = 0; i < 4; i++)
491	mon_types[i] = radeon_probe_i2c_connector(rinfo,
492	i+1, &EDIDs[i]);
493	}
494	#endif /* DEBUG */
495	/*	484	/*
496	* Old single head cards	485	* Old single head cards
497	*/	486	*/
Lines 531-541 Link Here
531	if (!BIOS_IN8(tmp + i*2) && i > 1)	520	if (!BIOS_IN8(tmp + i*2) && i > 1)
532	break;	521	break;
533	tmp0 = BIOS_IN16(tmp + i*2);	522	tmp0 = BIOS_IN16(tmp + i*2);
534	if ((!(tmp0 & 0x01)) && (((tmp0 >> 8) & 0x0f) == ddc_dvi)) {	523	if ((!(tmp0 & 0x01)) && ((((tmp0 >> 8) & 0x0f) == ddc_dvi) \|\| (((tmp0 >> 8) & 0x0f) == ddc_monid))) {
535	rinfo->reversed_DAC = 1;	524	rinfo->reversed_DAC = 1;
536	printk(KERN_INFO "radeonfb: Reversed DACs detected\n");	525	printk(KERN_INFO "radeonfb: Reversed DACs detected\n");
537	}	526	}
538	if ((((tmp0 >> 8) & 0x0f) == ddc_dvi) && ((tmp0 >> 4) & 0x01)) {	527	if ((((tmp0 >> 8) & 0x0f) == ddc_dvi \|\| (((tmp0 >> 8) & 0x0f) == ddc_monid)) && ((tmp0 >> 4) & 0x01)) {
539	rinfo->reversed_TMDS = 1;	528	rinfo->reversed_TMDS = 1;
540	printk(KERN_INFO "radeonfb: Reversed TMDS detected\n");	529	printk(KERN_INFO "radeonfb: Reversed TMDS detected\n");
541	}	530	}
Lines 552-557 Link Here
552	#endif /* CONFIG_PPC_OF \|\| CONFIG_SPARC */	541	#endif /* CONFIG_PPC_OF \|\| CONFIG_SPARC */
553	#ifdef CONFIG_FB_RADEON_I2C	542	#ifdef CONFIG_FB_RADEON_I2C
554	if (rinfo->mon1_type == MT_NONE)	543	if (rinfo->mon1_type == MT_NONE)
		544	rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_monid,
		545	&rinfo->mon1_EDID);
		546	if (rinfo->mon1_type == MT_NONE)
555	rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi,	547	rinfo->mon1_type = radeon_probe_i2c_connector(rinfo, ddc_dvi,
556	&rinfo->mon1_EDID);	548	&rinfo->mon1_EDID);
557	if (rinfo->mon1_type == MT_NONE) {	549	if (rinfo->mon1_type == MT_NONE) {
Lines 643-649 Link Here
643		635
644		636
645	/*	637	/*
646	* This functions applyes any arch/model/machine specific fixups	638	* This functions applies any arch/model/machine specific fixups
647	* to the panel info. It may eventually alter EDID block as	639	* to the panel info. It may eventually alter EDID block as
648	* well or whatever is specific to a given model and not probed	640	* well or whatever is specific to a given model and not probed
649	* properly by the default code	641	* properly by the default code