Attachment #104775 for bug #149649

Lines 1429-1434 case "$LIBINTL" in $LIBICONV) Link Here

(-)gcc/configure.ac (+23 lines)
1429	LIBICONV= ;;	1429	LIBICONV= ;;
1430	esac	1430	esac
1431		1431
		1432	AC_ARG_ENABLE(secureplt,
		1433	[ --enable-secureplt enable -msecure-plt by default for PowerPC],
		1434	[], [])
		1435
1432	# Windows32 Registry support for specifying GCC installation paths.	1436	# Windows32 Registry support for specifying GCC installation paths.
1433	AC_ARG_ENABLE(win32-registry,	1437	AC_ARG_ENABLE(win32-registry,
1434	[ --disable-win32-registry	1438	[ --disable-win32-registry
Lines 2762-2767 foo: nop Link Here
2762	[$conftest_s],,	2766	[$conftest_s],,
2763	[AC_DEFINE(HAVE_AS_MFCRF, 1,	2767	[AC_DEFINE(HAVE_AS_MFCRF, 1,
2764	[Define if your assembler supports mfcr field.])])	2768	[Define if your assembler supports mfcr field.])])
		2769
		2770	case $target in
		2771	--aix*) conftest_s=' .csect .text[[PR]]
		2772	LCF..0:
		2773	addis 11,30,_GLOBAL_OFFSET_TABLE_-LCF..0@ha';;
		2774	--darwin*)
		2775	conftest_s=' .text
		2776	LCF0:
		2777	addis r11,r30,_GLOBAL_OFFSET_TABLE_-LCF0@ha';;
		2778	*) conftest_s=' .text
		2779	.LCF0:
		2780	addis 11,30,_GLOBAL_OFFSET_TABLE_-.LCF0@ha';;
		2781	esac
		2782
		2783	gcc_GAS_CHECK_FEATURE([rel16 relocs],
		2784	gcc_cv_as_powerpc_rel16, [2,17,0], -a32,
		2785	[$conftest_s],,
		2786	[AC_DEFINE(HAVE_AS_REL16, 1,
		2787	[Define if your assembler supports R_PPC_REL16 relocs.])])
2765	;;	2788	;;
2766		2789
2767	mips--*)	2790	mips--*)

Lines 890-895 Optional Features: Link Here

(-)gcc/configure (+57 lines)
890	--enable-initfini-array use .init_array/.fini_array sections	890	--enable-initfini-array use .init_array/.fini_array sections
891	--enable-sjlj-exceptions	891	--enable-sjlj-exceptions
892	arrange to use setjmp/longjmp exception handling	892	arrange to use setjmp/longjmp exception handling
		893	--enable-secureplt enable -msecure-plt by default for PowerPC
893	--disable-win32-registry	894	--disable-win32-registry
894	disable lookup of installation paths in the	895	disable lookup of installation paths in the
895	Registry on Windows hosts	896	Registry on Windows hosts
Lines 12330-12335 case "$LIBINTL" in $LIBICONV) Link Here
12330	LIBICONV= ;;	12331	LIBICONV= ;;
12331	esac	12332	esac
12332		12333
		12334	# Check whether --enable-secureplt or --disable-secureplt was given.
		12335	if test "${enable_secureplt+set}" = set; then
		12336	enableval="$enable_secureplt"
		12337
		12338	fi;
		12339
12333	# Windows32 Registry support for specifying GCC installation paths.	12340	# Windows32 Registry support for specifying GCC installation paths.
12334	# Check whether --enable-win32-registry or --disable-win32-registry was given.	12341	# Check whether --enable-win32-registry or --disable-win32-registry was given.
12335	if test "${enable_win32_registry+set}" = set; then	12342	if test "${enable_win32_registry+set}" = set; then
Lines 14664-14669 cat >>confdefs.h <<\_ACEOF Link Here
14664	_ACEOF	14671	_ACEOF
14665		14672
14666	fi	14673	fi
		14674
		14675	case $target in
		14676	--aix*) conftest_s=' .csect .text[PR]
		14677	LCF..0:
		14678	addis 11,30,_GLOBAL_OFFSET_TABLE_-LCF..0@ha';;
		14679	--darwin*)
		14680	conftest_s=' .text
		14681	LCF0:
		14682	addis r11,r30,_GLOBAL_OFFSET_TABLE_-LCF0@ha';;
		14683	*) conftest_s=' .text
		14684	.LCF0:
		14685	addis 11,30,_GLOBAL_OFFSET_TABLE_-.LCF0@ha';;
		14686	esac
		14687
		14688	echo "$as_me:$LINENO: checking assembler for rel16 relocs" >&5
		14689	echo $ECHO_N "checking assembler for rel16 relocs... $ECHO_C" >&6
		14690	if test "${gcc_cv_as_powerpc_rel16+set}" = set; then
		14691	echo $ECHO_N "(cached) $ECHO_C" >&6
		14692	else
		14693	gcc_cv_as_powerpc_rel16=no
		14694	if test $in_tree_gas = yes; then
		14695	if test $gcc_cv_gas_vers -ge `expr $ \( 2 \* 1000 $ + 17 \) \* 1000 + 0`
		14696	then gcc_cv_as_powerpc_rel16=yes
		14697	fi
		14698	elif test x$gcc_cv_as != x; then
		14699	echo "$conftest_s" > conftest.s
		14700	if { ac_try='$gcc_cv_as -a32 -o conftest.o conftest.s >&5'
		14701	{ (eval echo "$as_me:$LINENO: \"$ac_try\"") >&5
		14702	(eval $ac_try) 2>&5
		14703	ac_status=$?
		14704	echo "$as_me:$LINENO: \$? = $ac_status" >&5
		14705	(exit $ac_status); }; }
		14706	then
		14707	gcc_cv_as_powerpc_rel16=yes
		14708	else
		14709	echo "configure: failed program was" >&5
		14710	cat conftest.s >&5
		14711	fi
		14712	rm -f conftest.o conftest.s
		14713	fi
		14714	fi
		14715	echo "$as_me:$LINENO: result: $gcc_cv_as_powerpc_rel16" >&5
		14716	echo "${ECHO_T}$gcc_cv_as_powerpc_rel16" >&6
		14717	if test $gcc_cv_as_powerpc_rel16 = yes; then
		14718
		14719	cat >>confdefs.h <<\_ACEOF
		14720	#define HAVE_AS_REL16 1
		14721	_ACEOF
		14722
		14723	fi
14667	;;	14724	;;
14668		14725
14669	mips--*)	14726	mips--*)

Lines 122-127 Link Here

(-)gcc/config.in (+3 lines)
122	/* Define if your assembler supports .register. */	122	/* Define if your assembler supports .register. */
123	#undef HAVE_AS_REGISTER_PSEUDO_OP	123	#undef HAVE_AS_REGISTER_PSEUDO_OP
124		124
		125	/* Define if your assembler supports R_PPC_REL16 relocs. */
		126	#undef HAVE_AS_REL16
		127
125	/* Define if your assembler supports -relax option. */	128	/* Define if your assembler supports -relax option. */
126	#undef HAVE_AS_RELAX_OPTION	129	#undef HAVE_AS_RELAX_OPTION
127		130

Lines 1559-1564 powerpc64--linux) Link Here

(-)gcc/config.gcc (+6 lines)
1559	test x$with_cpu != x \|\| cpu_is_64bit=yes	1559	test x$with_cpu != x \|\| cpu_is_64bit=yes
1560	test x$cpu_is_64bit != xyes \|\| tm_file="${tm_file} rs6000/default64.h"	1560	test x$cpu_is_64bit != xyes \|\| tm_file="${tm_file} rs6000/default64.h"
1561	tm_file="rs6000/biarch64.h ${tm_file} rs6000/linux64.h"	1561	tm_file="rs6000/biarch64.h ${tm_file} rs6000/linux64.h"
		1562	if test x${enable_secureplt} = xyes; then
		1563	tm_file="rs6000/secureplt.h ${tm_file}"
		1564	fi
1562	tmake_file="rs6000/t-fprules ${tmake_file} rs6000/t-ppccomm rs6000/t-linux64"	1565	tmake_file="rs6000/t-fprules ${tmake_file} rs6000/t-ppccomm rs6000/t-linux64"
1563	;;	1566	;;
1564	powerpc64--gnu)	1567	powerpc64--gnu)
Lines 1651-1656 powerpc--linux) Link Here
1651	tm_file="${tm_file} rs6000/linux.h"	1654	tm_file="${tm_file} rs6000/linux.h"
1652	;;	1655	;;
1653	esac	1656	esac
		1657	if test x${enable_secureplt} = xyes; then
		1658	tm_file="rs6000/secureplt.h ${tm_file}"
		1659	fi
1654	;;	1660	;;
1655	powerpc--gnu-gnualtivec)	1661	powerpc--gnu-gnualtivec)
1656	tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h"	1662	tm_file="${cpu_type}/${cpu_type}.h elfos.h svr4.h freebsd-spec.h gnu.h rs6000/sysv4.h rs6000/linux.h rs6000/linuxaltivec.h rs6000/gnu.h"




Specify that the compiler should
use DWARF 2 debugging information as the default.

@item --enable-targets=all
@itemx --enable-targets=@var{target_list}
Some GCC targets, e.g.@: powerpc64-linux, build bi-arch compilers.
These are compilers that are able to generate either 64-bit or 32-bit
code.  Typicially, the corresponding 32-bit target, e.g.@:
powerpc-linux for powerpc64-linux, only generates 32-bit code.  This
option enables the 32-bit target to be a bi-arch compiler, which is
useful when you want a bi-arch compiler that defaults to 32-bit, and
you are building a bi-arch or multi-arch binutils in a combined tree.
Currently, this option only affects powerpc-linux.

@item --enable-secureplt
This option enables @option{-msecure-plt} by default for powerpc-linux.
@ifnothtml
@xref{RS/6000 and PowerPC Options,, RS/6000 and PowerPC Options, gcc,
Using the GNU Compiler Collection (GCC)},
@end ifnothtml
@ifhtml
See ``RS/6000 and PowerPC Options'' in the main manual
@end ifhtml

@item --enable-win32-registry
@itemx --enable-win32-registry=@var{key}
@itemx --disable-win32-registry

ATMEL AVR-family micro controllers.  These are used in embedded
applications.  There are no standard Unix configurations.
@ifnothtml
@xref{AVR Options,, AVR Options, gcc, Using the GNU Compiler
Collection (GCC)},
@end ifnothtml
@ifhtml


The Blackfin processor, an Analog Devices DSP.
@ifnothtml
@xref{Blackfin Options,, Blackfin Options, gcc, Using the GNU Compiler
Collection (GCC)},
@end ifnothtml
@ifhtml
See ``Blackfin Options'' in the main manual

Processors.  These are used in embedded applications.  There are no
standard Unix configurations.
@ifnothtml
@xref{TMS320C3x/C4x Options,, TMS320C3x/C4x Options, gcc, Using the
GNU Compiler Collection (GCC)},
@end ifnothtml
@ifhtml
See ``TMS320C3x/C4x Options'' in the main manual

series.  These are used in embedded applications.

@ifnothtml
@xref{CRIS Options,, CRIS Options, gcc, Using the GNU Compiler
Collection (GCC)},
@end ifnothtml
@ifhtml




-maix-struct-return  -msvr4-struct-return @gol
-mabi=altivec  -mabi=no-altivec @gol
-mabi=spe  -mabi=no-spe @gol
-msecure-plt -mbss-plt @gol
-misel=yes  -misel=no @gol
-mspe=yes  -mspe=no @gol
-mfloat-gprs=yes  -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol

@opindex mabi=no-spe
Disable Booke SPE ABI extensions for the current ABI@.

@item -msecure-plt
@opindex msecure-plt
Generate code that allows ld and ld.so to build executables and shared
libraries with non-exec .plt and .got sections.  This is a PowerPC
32-bit SYSV ABI option.

@item -mbss-plt
@opindex mbss-plt
Generate code that uses a BSS .plt section that ld.so fills in, and
requires .plt and .got sections that are both writable and executable.
This is a PowerPC 32-bit SYSV ABI option.

@item -misel=@var{yes/no}
@itemx -misel
@opindex misel




/* Default to -msecure-plt.
   Copyright (C) 2005 Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

#define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt"

Lines 55-60 extern enum rs6000_sdata_type rs6000_sda Link Here

(-)gcc/config/rs6000/sysv4.h (-3 / +18 lines)
55	#define MASK_REGNAMES 0x02000000 /* Use alternate register names. */	55	#define MASK_REGNAMES 0x02000000 /* Use alternate register names. */
56	#define MASK_PROTOTYPE 0x01000000 /* Only prototyped fcns pass variable args. */	56	#define MASK_PROTOTYPE 0x01000000 /* Only prototyped fcns pass variable args. */
57	#define MASK_NO_BITFIELD_WORD 0x00800000 /* Bitfields cannot cross word boundaries */	57	#define MASK_NO_BITFIELD_WORD 0x00800000 /* Bitfields cannot cross word boundaries */
		58	#define MASK_SECURE_PLT 0x00400000 /* Use non-exec PLT/GOT. */
58		59
59	#define TARGET_NO_BITFIELD_TYPE (target_flags & MASK_NO_BITFIELD_TYPE)	60	#define TARGET_NO_BITFIELD_TYPE (target_flags & MASK_NO_BITFIELD_TYPE)
60	#define TARGET_STRICT_ALIGN (target_flags & MASK_STRICT_ALIGN)	61	#define TARGET_STRICT_ALIGN (target_flags & MASK_STRICT_ALIGN)
Lines 149-160 extern const char *rs6000_tls_size_strin Link Here
149	N_("Set the PPC_EMB bit in the ELF flags header") }, \	150	N_("Set the PPC_EMB bit in the ELF flags header") }, \
150	{ "windiss", 0, N_("Use the WindISS simulator") }, \	151	{ "windiss", 0, N_("Use the WindISS simulator") }, \
151	{ "shlib", 0, N_("no description yet") }, \	152	{ "shlib", 0, N_("no description yet") }, \
		153	{ "newlib", 0, N_("no description yet") }, \
152	{ "64", MASK_64BIT \| MASK_POWERPC64 \| MASK_POWERPC, \	154	{ "64", MASK_64BIT \| MASK_POWERPC64 \| MASK_POWERPC, \
153	N_("Generate 64-bit code") }, \	155	N_("Generate 64-bit code") }, \
154	{ "32", - (MASK_64BIT \| MASK_POWERPC64), \	156	{ "32", - (MASK_64BIT \| MASK_POWERPC64), \
155	N_("Generate 32-bit code") }, \	157	N_("Generate 32-bit code") }, \
156	EXTRA_SUBTARGET_SWITCHES \	158	{ "secure-plt", MASK_SECURE_PLT, \
157	{ "newlib", 0, N_("no description yet") },	159	N_("Generate code for non-exec PLT and GOT") },\
		160	{ "bss-plt", -MASK_SECURE_PLT, \
		161	N_("Generate code for exec BSS PLT") }, \
		162	EXTRA_SUBTARGET_SWITCHES
158		163
159	/* This is meant to be redefined in the host dependent files. */	164	/* This is meant to be redefined in the host dependent files. */
160	#define EXTRA_SUBTARGET_SWITCHES	165	#define EXTRA_SUBTARGET_SWITCHES
Lines 299-304 do { \ Link Here
299	error ("-mcall-aixdesc must be big endian"); \	304	error ("-mcall-aixdesc must be big endian"); \
300	} \	305	} \
301	\	306	\
		307	if (TARGET_SECURE_PLT != (target_flags & MASK_SECURE_PLT)) \
		308	{ \
		309	error ("-msecure-plt not supported by your assembler"); \
		310	} \
		311	\
302	/* Treat -fPIC the same as -mrelocatable. */ \	312	/* Treat -fPIC the same as -mrelocatable. */ \
303	if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \	313	if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \
304	target_flags \|= MASK_RELOCATABLE \| MASK_MINIMAL_TOC \| MASK_NO_FP_IN_TOC; \	314	target_flags \|= MASK_RELOCATABLE \| MASK_MINIMAL_TOC \| MASK_NO_FP_IN_TOC; \
Lines 844-849 extern int fixuplabelno; Link Here
844		854
845	#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)"	855	#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)"
846		856
		857	#ifndef CC1_SECURE_PLT_DEFAULT_SPEC
		858	#define CC1_SECURE_PLT_DEFAULT_SPEC ""
		859	#endif
		860
847	/* Pass -G xxx to the compiler and set correct endian mode. */	861	/* Pass -G xxx to the compiler and set correct endian mode. */
848	#define CC1_SPEC "%{G*} \	862	#define CC1_SPEC "%{G*} \
849	%{mlittle\|mlittle-endian: %(cc1_endian_little); \	863	%{mlittle\|mlittle-endian: %(cc1_endian_little); \
Lines 856-862 extern int fixuplabelno; Link Here
856	mcall-gnu : -mbig %(cc1_endian_big); \	870	mcall-gnu : -mbig %(cc1_endian_big); \
857	mcall-i960-old : -mlittle %(cc1_endian_little); \	871	mcall-i960-old : -mlittle %(cc1_endian_little); \
858	: %(cc1_endian_default)} \	872	: %(cc1_endian_default)} \
859	%{mno-sdata: -msdata=none } \
860	%{meabi: %{!mcall-*: -mcall-sysv }} \	873	%{meabi: %{!mcall-*: -mcall-sysv }} \
861	%{!meabi: %{!mno-eabi: \	874	%{!meabi: %{!mno-eabi: \
862	%{mrelocatable: -meabi } \	875	%{mrelocatable: -meabi } \
Lines 868-873 extern int fixuplabelno; Link Here
868	%{mcall-openbsd: -mno-eabi }}} \	881	%{mcall-openbsd: -mno-eabi }}} \
869	%{msdata: -msdata=default} \	882	%{msdata: -msdata=default} \
870	%{mno-sdata: -msdata=none} \	883	%{mno-sdata: -msdata=none} \
		884	%{!mbss-plt: %{!msecure-plt: %(cc1_secure_plt_default)}} \
871	%{profile: -p}"	885	%{profile: -p}"
872		886
873	/* Don't put -Y P,<path> for cross compilers. */	887	/* Don't put -Y P,<path> for cross compilers. */
Lines 1308-1313 ncrtn.o%s" Link Here
1308	{ "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \	1322	{ "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \
1309	{ "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \	1323	{ "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \
1310	{ "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \	1324	{ "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \
		1325	{ "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \
1311	{ "cpp_os_ads", CPP_OS_ADS_SPEC }, \	1326	{ "cpp_os_ads", CPP_OS_ADS_SPEC }, \
1312	{ "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \	1327	{ "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \
1313	{ "cpp_os_mvme", CPP_OS_MVME_SPEC }, \	1328	{ "cpp_os_mvme", CPP_OS_MVME_SPEC }, \

Lines 201-208 extern int target_flags; Link Here

(-)gcc/config/rs6000/rs6000.h (-2 / +7 lines)
201	/* Use single field mfcr instruction. */	201	/* Use single field mfcr instruction. */
202	#define MASK_MFCRF 0x00080000	202	#define MASK_MFCRF 0x00080000
203		203
204	/* The only remaining free bits are 0x00600000. linux64.h uses	204	/* The only remaining free bit is 0x00200000. linux64.h uses
205	0x00100000, and sysv4.h uses 0x00800000 -> 0x40000000.	205	0x00100000, and sysv4.h uses 0x00400000 -> 0x40000000.
206	0x80000000 is not available because target_flags is signed. */	206	0x80000000 is not available because target_flags is signed. */
207		207
208	#define TARGET_POWER (target_flags & MASK_POWER)	208	#define TARGET_POWER (target_flags & MASK_POWER)
Lines 234-239 extern int target_flags; Link Here
234	#define TARGET_MFCRF 0	234	#define TARGET_MFCRF 0
235	#endif	235	#endif
236		236
		237	#ifdef HAVE_AS_REL16
		238	#define TARGET_SECURE_PLT (target_flags & MASK_SECURE_PLT)
		239	#else
		240	#define TARGET_SECURE_PLT 0
		241	#endif
237		242
238	#define TARGET_32BIT (! TARGET_64BIT)	243	#define TARGET_32BIT (! TARGET_64BIT)
239	#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)	244	#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)




  rtx dest, insn;
  dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);

  if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
    {
      char buf[30];
      rtx lab, tmp1, tmp2, got, tempLR;

      ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
      lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
      if (flag_pic == 2)
	got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
      else
	got = rs6000_got_sym ();
      tmp1 = tmp2 = dest;
      if (!fromprolog)
	{
	  tmp1 = gen_reg_rtx (Pmode);
	  tmp2 = gen_reg_rtx (Pmode);
	}
      tempLR = (fromprolog
		? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
		: gen_reg_rtx (Pmode));
      insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
      if (fromprolog)
	rs6000_maybe_dead (insn);
      insn = emit_move_insn (tmp1, tempLR);
      if (fromprolog)
	rs6000_maybe_dead (insn);
      insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
      if (fromprolog)
	rs6000_maybe_dead (insn);
      insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
      if (fromprolog)
	rs6000_maybe_dead (insn);
    }
  else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
    {
      rtx tempLR = (fromprolog
		    ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
		    : gen_reg_rtx (Pmode));

      insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
      if (fromprolog)
	rs6000_maybe_dead (insn);
      insn = emit_move_insn (dest, tempLR);
      if (fromprolog)
	rs6000_maybe_dead (insn);
    }


  /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up.  */
  if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
      || (DEFAULT_ABI == ABI_V4
	  && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
	  && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
    {
      /* If emit_load_toc_table will use the link register, we need to save

    }

  if (TARGET_RELOCATABLE
      && !TARGET_SECURE_PLT
      && (get_pool_size () != 0 || current_function_profile)
      && uses_TOC ())
    {





;; Now define ways of moving data around.

;; Elf specific ways of loading addresses for non-PIC code.
;; The output of this could be r0, but we make a very strong
;; preference for a base register because it will usually
;; be needed there.
(define_insn "elf_high"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
	(high:SI (match_operand 1 "" "")))]
  "TARGET_ELF && ! TARGET_64BIT"
  "{liu|lis} %0,%1@ha")

(define_insn "elf_low"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
		   (match_operand 2 "" "")))]
   "TARGET_ELF && ! TARGET_64BIT"
   "@
    {cal|la} %0,%2@l(%1)
    {ai|addic} %0,%1,%K2")


;; Set up a register with a value from the GOT table

(define_expand "movsi_got"

  [(set (match_operand:SI 0 "register_operand" "=l")
	(match_operand:SI 1 "immediate_operand" "s"))
   (use (unspec [(match_dup 1)] UNSPEC_TOC))]
  "TARGET_ELF && DEFAULT_ABI != ABI_AIX
   && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
  "bcl 20,31,%1\\n%1:"
  [(set_attr "type" "branch")
   (set_attr "length" "4")])

  "{l|lwz} %0,%2-%3(%1)"
  [(set_attr "type" "load")])

(define_insn "load_toc_v4_PIC_3b"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		 (high:SI
		   (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
			     (match_operand:SI 3 "symbol_ref_operand" "s")))))]
  "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
  "{cau|addis} %0,%1,%2-%3@ha")

(define_insn "load_toc_v4_PIC_3c"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
		   (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
			     (match_operand:SI 3 "symbol_ref_operand" "s"))))]
  "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
  "{cal|addi} %0,%1,%2-%3@l")


;; If the TOC is shared over a translation unit, as happens with all
;; the kinds of PIC that we support, we need to restore the TOC

    rs6000_emit_load_toc_table (FALSE);
  DONE;
}")

;; Elf specific ways of loading addresses for non-PIC code.
;; The output of this could be r0, but we make a very strong
;; preference for a base register because it will usually
;; be needed there.
(define_insn "elf_high"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
	(high:SI (match_operand 1 "" "")))]
  "TARGET_ELF && ! TARGET_64BIT"
  "{liu|lis} %0,%1@ha")

(define_insn "elf_low"
  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
		   (match_operand 2 "" "")))]
   "TARGET_ELF && ! TARGET_64BIT"
   "@
    {cal|la} %0,%2@l(%1)
    {ai|addic} %0,%1,%K2")


;; A function pointer under AIX is a pointer to a data area whose first word
;; contains the actual address of the function, whose second word contains a


  operands[0] = XEXP (operands[0], 0);

  if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
      && flag_pic
      && GET_CODE (operands[0]) == SYMBOL_REF
      && !SYMBOL_REF_LOCAL_P (operands[0]))
    {
      rtx call;
      rtvec tmp;

      tmp = gen_rtvec (3,
		       gen_rtx_CALL (VOIDmode,
				     gen_rtx_MEM (SImode, operands[0]),
				     operands[1]),
		       gen_rtx_USE (VOIDmode, operands[2]),
		       gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
      call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
      use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
      DONE;
    }

  if (GET_CODE (operands[0]) != SYMBOL_REF
      || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
      || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))


  operands[1] = XEXP (operands[1], 0);

  if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
      && flag_pic
      && GET_CODE (operands[1]) == SYMBOL_REF
      && !SYMBOL_REF_LOCAL_P (operands[1]))
    {
      rtx call;
      rtvec tmp;

      tmp = gen_rtvec (3,
		       gen_rtx_SET (VOIDmode,
				    operands[0],
				    gen_rtx_CALL (VOIDmode,
						  gen_rtx_MEM (SImode,
							       operands[1]),
						  operands[2])),
		       gen_rtx_USE (VOIDmode, operands[3]),
		       gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
      call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
      use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
      DONE;
    }

  if (GET_CODE (operands[1]) != SYMBOL_REF
      || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
      || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))

#if TARGET_MACHO
  return output_call(insn, operands, 0, 2);
#else
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
    {
      if (TARGET_SECURE_PLT && flag_pic == 2)
	/* The magic 32768 offset here and in the other sysv call insns
	   corresponds to the offset of r30 in .got2, as given by LCTOC1.
	   See sysv4.h:toc_section.  */
	return "bl %z0+32768@plt";
      else
	return "bl %z0@plt";
    }
  else
    return "bl %z0";
#endif
}
  [(set_attr "type" "branch,branch")

#if TARGET_MACHO
  return output_call(insn, operands, 1, 3);
#else
  if (DEFAULT_ABI == ABI_V4 && flag_pic)
    {
      if (TARGET_SECURE_PLT && flag_pic == 2)
	return "bl %z1+32768@plt";
      else
	return "bl %z1@plt";
    }
  else
    return "bl %z1";
#endif
}
  [(set_attr "type" "branch,branch")

  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
    output_asm_insn (\"creqv 6,6,6\", operands);

  if (DEFAULT_ABI == ABI_V4 && flag_pic)
    {
      if (TARGET_SECURE_PLT && flag_pic == 2)
	return \"b %z0+32768@plt\";
      else
	return \"b %z0@plt\";
    }
  else
    return \"b %z0\";
}"
  [(set_attr "type" "branch,branch")
   (set_attr "length" "4,8")])

  else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
    output_asm_insn (\"creqv 6,6,6\", operands);

  if (DEFAULT_ABI == ABI_V4 && flag_pic)
    {
      if (TARGET_SECURE_PLT && flag_pic == 2)
	return \"b %z1+32768@plt\";
      else
	return \"b %z1@plt\";
    }
  else
    return \"b %z1\";
}"
  [(set_attr "type" "branch,branch")
   (set_attr "length" "4,8")])

Lines 44-50 Link Here

(-)gcc/config/rs6000/tramp.asm (-2 / +8 lines)
44	.align 2	44	.align 2
45	trampoline_initial:	45	trampoline_initial:
46	mflr r0	46	mflr r0
47	bl 1f	47	bcl 20,31,1f
48	.Lfunc = .-trampoline_initial	48	.Lfunc = .-trampoline_initial
49	.long 0 /* will be replaced with function address */	49	.long 0 /* will be replaced with function address */
50	.Lchain = .-trampoline_initial	50	.Lchain = .-trampoline_initial
Lines 67-73 trampoline_size = .-trampoline_initial Link Here
67		67
68	FUNC_START(__trampoline_setup)	68	FUNC_START(__trampoline_setup)
69	mflr r0 /* save return address */	69	mflr r0 /* save return address */
70	bl .LCF0 /* load up __trampoline_initial into r7 */	70	bcl 20,31,.LCF0 /* load up __trampoline_initial into r7 */
71	.LCF0:	71	.LCF0:
72	mflr r11	72	mflr r11
73	addi r7,r11,trampoline_initial-4-.LCF0 /* trampoline address -4 */	73	addi r7,r11,trampoline_initial-4-.LCF0 /* trampoline address -4 */
Lines 105-110 FUNC_START(__trampoline_setup) Link Here
105	blr	105	blr
106		106
107	.Labort:	107	.Labort:
		108	#if defined SHARED && defined HAVE_AS_REL16
		109	bcl 20,31,1f
		110	1: mflr r30
		111	addis r30,r30,_GLOBAL_OFFSET_TABLE_-1b@ha
		112	addi r30,r30,_GLOBAL_OFFSET_TABLE_-1b@l
		113	#endif
108	bl JUMP_TARGET(abort)	114	bl JUMP_TARGET(abort)
109	FUNC_END(__trampoline_setup)	115	FUNC_END(__trampoline_setup)
110		116

Lines 57-63 ENTRY(ffi_closure_SYSV) Link Here

(-)libffi/src/powerpc/ppc_closure.S (-1 / +1 lines)
57	addi %r7,%r1,152	57	addi %r7,%r1,152
58		58
59	# make the call	59	# make the call
60	bl JUMPTARGET(ffi_closure_helper_SYSV)	60	bl ffi_closure_helper_SYSV@local
61		61
62	# now r3 contains the return type	62	# now r3 contains the return type
63	# so use it to look up in a table	63	# so use it to look up in a table

Lines 60-66 ENTRY(ffi_call_SYSV) Link Here

(-)libffi/src/powerpc/sysv.S (-1 / +1 lines)
60		60
61	/* Call ffi_prep_args_SYSV. */	61	/* Call ffi_prep_args_SYSV. */
62	mr %r4,%r1	62	mr %r4,%r1
63	bl JUMPTARGET(ffi_prep_args_SYSV)	63	bl ffi_prep_args_SYSV@local
64		64
65	/* Now do the call. */	65	/* Now do the call. */
66	/* Set up cr1 with bits 4-7 of the flags. */	66	/* Set up cr1 with bits 4-7 of the flags. */

Return to bug 149649

Lines 1071-1076 do a @samp{make -C gcc gnatlib_and_tools Link Here

(-)gcc/doc/install.texi (-6 / +27 lines)
1071	Specify that the compiler should	1071	Specify that the compiler should
1072	use DWARF 2 debugging information as the default.	1072	use DWARF 2 debugging information as the default.
1073		1073
		1074	@item --enable-targets=all
		1075	@itemx --enable-targets=@var{target_list}
		1076	Some GCC targets, e.g.@: powerpc64-linux, build bi-arch compilers.
		1077	These are compilers that are able to generate either 64-bit or 32-bit
		1078	code. Typicially, the corresponding 32-bit target, e.g.@:
		1079	powerpc-linux for powerpc64-linux, only generates 32-bit code. This
		1080	option enables the 32-bit target to be a bi-arch compiler, which is
		1081	useful when you want a bi-arch compiler that defaults to 32-bit, and
		1082	you are building a bi-arch or multi-arch binutils in a combined tree.
		1083	Currently, this option only affects powerpc-linux.
		1084
		1085	@item --enable-secureplt
		1086	This option enables @option{-msecure-plt} by default for powerpc-linux.
		1087	@ifnothtml
		1088	@xref{RS/6000 and PowerPC Options,, RS/6000 and PowerPC Options, gcc,
		1089	Using the GNU Compiler Collection (GCC)},
		1090	@end ifnothtml
		1091	@ifhtml
		1092	See ``RS/6000 and PowerPC Options'' in the main manual
		1093	@end ifhtml
		1094
1074	@item --enable-win32-registry	1095	@item --enable-win32-registry
1075	@itemx --enable-win32-registry=@var{key}	1096	@itemx --enable-win32-registry=@var{key}
1076	@itemx --disable-win32-registry	1097	@itemx --disable-win32-registry
Lines 2464-2470 ARM-family processors. These targets su Link Here
2464	ATMEL AVR-family micro controllers. These are used in embedded	2485	ATMEL AVR-family micro controllers. These are used in embedded
2465	applications. There are no standard Unix configurations.	2486	applications. There are no standard Unix configurations.
2466	@ifnothtml	2487	@ifnothtml
2467	@xref{AVR Options,, AVR Options, gcc, Using and Porting the GNU Compiler	2488	@xref{AVR Options,, AVR Options, gcc, Using the GNU Compiler
2468	Collection (GCC)},	2489	Collection (GCC)},
2469	@end ifnothtml	2490	@end ifnothtml
2470	@ifhtml	2491	@ifhtml
Lines 2502-2509 indicates that you should upgrade to a n Link Here
2502		2523
2503	The Blackfin processor, an Analog Devices DSP.	2524	The Blackfin processor, an Analog Devices DSP.
2504	@ifnothtml	2525	@ifnothtml
2505	@xref{Blackfin Options,, Blackfin Options, gcc, Using and Porting the GNU	2526	@xref{Blackfin Options,, Blackfin Options, gcc, Using the GNU Compiler
2506	Compiler Collection (GCC)},	2527	Collection (GCC)},
2507	@end ifnothtml	2528	@end ifnothtml
2508	@ifhtml	2529	@ifhtml
2509	See ``Blackfin Options'' in the main manual	2530	See ``Blackfin Options'' in the main manual
Lines 2521-2528 Texas Instruments TMS320C3x and TMS320C4 Link Here
2521	Processors. These are used in embedded applications. There are no	2542	Processors. These are used in embedded applications. There are no
2522	standard Unix configurations.	2543	standard Unix configurations.
2523	@ifnothtml	2544	@ifnothtml
2524	@xref{TMS320C3x/C4x Options,, TMS320C3x/C4x Options, gcc, Using and	2545	@xref{TMS320C3x/C4x Options,, TMS320C3x/C4x Options, gcc, Using the
2525	Porting the GNU Compiler Collection (GCC)},	2546	GNU Compiler Collection (GCC)},
2526	@end ifnothtml	2547	@end ifnothtml
2527	@ifhtml	2548	@ifhtml
2528	See ``TMS320C3x/C4x Options'' in the main manual	2549	See ``TMS320C3x/C4x Options'' in the main manual
Lines 2551-2557 CRIS is the CPU architecture in Axis Com Link Here
2551	series. These are used in embedded applications.	2572	series. These are used in embedded applications.
2552		2573
2553	@ifnothtml	2574	@ifnothtml
2554	@xref{CRIS Options,, CRIS Options, gcc, Using and Porting the GNU Compiler	2575	@xref{CRIS Options,, CRIS Options, gcc, Using the GNU Compiler
2555	Collection (GCC)},	2576	Collection (GCC)},
2556	@end ifnothtml	2577	@end ifnothtml
2557	@ifhtml	2578	@ifhtml

Lines 625-630 See RS/6000 and PowerPC Options. Link Here

(-)gcc/doc/invoke.texi (+13 lines)
625	-maix-struct-return -msvr4-struct-return @gol	625	-maix-struct-return -msvr4-struct-return @gol
626	-mabi=altivec -mabi=no-altivec @gol	626	-mabi=altivec -mabi=no-altivec @gol
627	-mabi=spe -mabi=no-spe @gol	627	-mabi=spe -mabi=no-spe @gol
		628	-msecure-plt -mbss-plt @gol
628	-misel=yes -misel=no @gol	629	-misel=yes -misel=no @gol
629	-mspe=yes -mspe=no @gol	630	-mspe=yes -mspe=no @gol
630	-mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol	631	-mfloat-gprs=yes -mfloat-gprs=no -mfloat-gprs=single -mfloat-gprs=double @gol
Lines 10515-10520 ABI@. Link Here
10515	@opindex mabi=no-spe	10516	@opindex mabi=no-spe
10516	Disable Booke SPE ABI extensions for the current ABI@.	10517	Disable Booke SPE ABI extensions for the current ABI@.
10517		10518
		10519	@item -msecure-plt
		10520	@opindex msecure-plt
		10521	Generate code that allows ld and ld.so to build executables and shared
		10522	libraries with non-exec .plt and .got sections. This is a PowerPC
		10523	32-bit SYSV ABI option.
		10524
		10525	@item -mbss-plt
		10526	@opindex mbss-plt
		10527	Generate code that uses a BSS .plt section that ld.so fills in, and
		10528	requires .plt and .got sections that are both writable and executable.
		10529	This is a PowerPC 32-bit SYSV ABI option.
		10530
10518	@item -misel=@var{yes/no}	10531	@item -misel=@var{yes/no}
10519	@itemx -misel	10532	@itemx -misel
10520	@opindex misel	10533	@opindex misel

Lines 13466-13480 rs6000_emit_load_toc_table (int fromprol Link Here

(-)gcc/config/rs6000/rs6000.c (-7 / +43 lines)
13466	rtx dest, insn;	13520	rtx dest, insn;
13467	dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);	13521	dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13468		13522
13469	if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)	13523	if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13470	{	13524	{
13471	rtx temp = (fromprolog	13525	char buf[30];
13472	? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)	13526	rtx lab, tmp1, tmp2, got, tempLR;
13473	: gen_reg_rtx (Pmode));	13527
13474	insn = emit_insn (gen_load_toc_v4_pic_si (temp));	13528	ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
		13529	lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
		13530	if (flag_pic == 2)
		13531	got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
		13532	else
		13533	got = rs6000_got_sym ();
		13534	tmp1 = tmp2 = dest;
		13535	if (!fromprolog)
		13536	{
		13537	tmp1 = gen_reg_rtx (Pmode);
		13538	tmp2 = gen_reg_rtx (Pmode);
		13539	}
		13540	tempLR = (fromprolog
		13541	? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
		13542	: gen_reg_rtx (Pmode));
		13543	insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
		13544	if (fromprolog)
		13545	rs6000_maybe_dead (insn);
		13546	insn = emit_move_insn (tmp1, tempLR);
		13547	if (fromprolog)
		13548	rs6000_maybe_dead (insn);
		13549	insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
		13550	if (fromprolog)
		13551	rs6000_maybe_dead (insn);
		13552	insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
		13553	if (fromprolog)
		13554	rs6000_maybe_dead (insn);
		13555	}
		13556	else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
		13557	{
		13558	rtx tempLR = (fromprolog
		13559	? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
		13560	: gen_reg_rtx (Pmode));
		13561
		13562	insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13475	if (fromprolog)	13563	if (fromprolog)
13476	rs6000_maybe_dead (insn);	13564	rs6000_maybe_dead (insn);
13477	insn = emit_move_insn (dest, temp);	13565	insn = emit_move_insn (dest, tempLR);
13478	if (fromprolog)	13566	if (fromprolog)
13479	rs6000_maybe_dead (insn);	13567	rs6000_maybe_dead (insn);
13480	}	13568	}
Lines 14565-14571 rs6000_emit_prologue (void) Link Here
14565		14653
14566	/* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */	14654	/* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14567	if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)	14655	if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14568	\|\| (DEFAULT_ABI == ABI_V4 && flag_pic == 1	14656	\|\| (DEFAULT_ABI == ABI_V4
		14657	&& (flag_pic == 1 \|\| (flag_pic && TARGET_SECURE_PLT))
14569	&& regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))	14658	&& regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14570	{	14659	{
14571	/* If emit_load_toc_table will use the link register, we need to save	14660	/* If emit_load_toc_table will use the link register, we need to save
Lines 18082-18087 rs6000_elf_declare_function_name (FILE * Link Here
18082	}	18171	}
18083		18172
18084	if (TARGET_RELOCATABLE	18173	if (TARGET_RELOCATABLE
		18174	&& !TARGET_SECURE_PLT
18085	&& (get_pool_size () != 0 \|\| current_function_profile)	18175	&& (get_pool_size () != 0 \|\| current_function_profile)
18086	&& uses_TOC ())	18176	&& uses_TOC ())
18087	{	18177	{

Line 0 Link Here

(-)gcc/config/rs6000/secureplt.h (+21 lines)
	1	/* Default to -msecure-plt.
	2	Copyright (C) 2005 Free Software Foundation, Inc.
	3
	4	This file is part of GCC.
	5
	6	GCC is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
	8	the Free Software Foundation; either version 2, or (at your option)
	9	any later version.
	10
	11	GCC is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
	17	along with GCC; see the file COPYING. If not, write to
	18	the Free Software Foundation, 59 Temple Place - Suite 330,
	19	Boston, MA 02111-1307, USA. */
	20
	21	#define CC1_SECURE_PLT_DEFAULT_SPEC "-msecure-plt"

Lines 7653-7678 Link Here

(-)gcc/config/rs6000/rs6000.md (-25 / +119 lines)
7653		7653
7654	;; Now define ways of moving data around.	7654	;; Now define ways of moving data around.
7655		7655
7656	;; Elf specific ways of loading addresses for non-PIC code.
7657	;; The output of this could be r0, but we make a very strong
7658	;; preference for a base register because it will usually
7659	;; be needed there.
7660	(define_insn "elf_high"
7661	[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
7662	(high:SI (match_operand 1 "" "")))]
7663	"TARGET_ELF && ! TARGET_64BIT"
7664	"{liu\|lis} %0,%1@ha")
7665
7666	(define_insn "elf_low"
7667	[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
7668	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
7669	(match_operand 2 "" "")))]
7670	"TARGET_ELF && ! TARGET_64BIT"
7671	"@
7672	{cal\|la} %0,%2@l(%1)
7673	{ai\|addic} %0,%1,%K2")
7674
7675
7676	;; Set up a register with a value from the GOT table	7656	;; Set up a register with a value from the GOT table
7677		7657
7678	(define_expand "movsi_got"	7658	(define_expand "movsi_got"
Lines 10133-10139 Link Here
10133	[(set (match_operand:SI 0 "register_operand" "=l")	10111	[(set (match_operand:SI 0 "register_operand" "=l")
10134	(match_operand:SI 1 "immediate_operand" "s"))	10112	(match_operand:SI 1 "immediate_operand" "s"))
10135	(use (unspec [(match_dup 1)] UNSPEC_TOC))]	10113	(use (unspec [(match_dup 1)] UNSPEC_TOC))]
10136	"TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"	10114	"TARGET_ELF && DEFAULT_ABI != ABI_AIX
		10115	&& (flag_pic == 2 \|\| (flag_pic && TARGET_SECURE_PLT))"
10137	"bcl 20,31,%1\\n%1:"	10116	"bcl 20,31,%1\\n%1:"
10138	[(set_attr "type" "branch")	10117	[(set_attr "type" "branch")
10139	(set_attr "length" "4")])	10118	(set_attr "length" "4")])
Lines 10156-10161 Link Here
10156	"{l\|lwz} %0,%2-%3(%1)"	10135	"{l\|lwz} %0,%2-%3(%1)"
10157	[(set_attr "type" "load")])	10136	[(set_attr "type" "load")])
10158		10137
		10138	(define_insn "load_toc_v4_PIC_3b"
		10139	[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
		10140	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
		10141	(high:SI
		10142	(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
		10143	(match_operand:SI 3 "symbol_ref_operand" "s")))))]
		10144	"TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
		10145	"{cau\|addis} %0,%1,%2-%3@ha")
		10146
		10147	(define_insn "load_toc_v4_PIC_3c"
		10148	[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
		10149	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
		10150	(minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
		10151	(match_operand:SI 3 "symbol_ref_operand" "s"))))]
		10152	"TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
		10153	"{cal\|addi} %0,%1,%2-%3@l")
		10154
10159		10155
10160	;; If the TOC is shared over a translation unit, as happens with all	10156	;; If the TOC is shared over a translation unit, as happens with all
10161	;; the kinds of PIC that we support, we need to restore the TOC	10157	;; the kinds of PIC that we support, we need to restore the TOC
Lines 10190-10195 Link Here
10190	rs6000_emit_load_toc_table (FALSE);	10186	rs6000_emit_load_toc_table (FALSE);
10191	DONE;	10187	DONE;
10192	}")	10188	}")
		10189
		10190	;; Elf specific ways of loading addresses for non-PIC code.
		10191	;; The output of this could be r0, but we make a very strong
		10192	;; preference for a base register because it will usually
		10193	;; be needed there.
		10194	(define_insn "elf_high"
		10195	[(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
		10196	(high:SI (match_operand 1 "" "")))]
		10197	"TARGET_ELF && ! TARGET_64BIT"
		10198	"{liu\|lis} %0,%1@ha")
		10199
		10200	(define_insn "elf_low"
		10201	[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
		10202	(lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
		10203	(match_operand 2 "" "")))]
		10204	"TARGET_ELF && ! TARGET_64BIT"
		10205	"@
		10206	{cal\|la} %0,%2@l(%1)
		10207	{ai\|addic} %0,%1,%K2")
		10208
10193		10209
10194	;; A function pointer under AIX is a pointer to a data area whose first word	10210	;; A function pointer under AIX is a pointer to a data area whose first word
10195	;; contains the actual address of the function, whose second word contains a	10211	;; contains the actual address of the function, whose second word contains a
Lines 10306-10311 Link Here
10306		10322
10307	operands[0] = XEXP (operands[0], 0);	10323	operands[0] = XEXP (operands[0], 0);
10308		10324
		10325	if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
		10326	&& flag_pic
		10327	&& GET_CODE (operands[0]) == SYMBOL_REF
		10328	&& !SYMBOL_REF_LOCAL_P (operands[0]))
		10329	{
		10330	rtx call;
		10331	rtvec tmp;
		10332
		10333	tmp = gen_rtvec (3,
		10334	gen_rtx_CALL (VOIDmode,
		10335	gen_rtx_MEM (SImode, operands[0]),
		10336	operands[1]),
		10337	gen_rtx_USE (VOIDmode, operands[2]),
		10338	gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
		10339	call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
		10340	use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
		10341	DONE;
		10342	}
		10343
10309	if (GET_CODE (operands[0]) != SYMBOL_REF	10344	if (GET_CODE (operands[0]) != SYMBOL_REF
10310	\|\| (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))	10345	\|\| (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10311	\|\| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))	10346	\|\| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
Lines 10354-10359 Link Here
10354		10389
10355	operands[1] = XEXP (operands[1], 0);	10390	operands[1] = XEXP (operands[1], 0);
10356		10391
		10392	if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT
		10393	&& flag_pic
		10394	&& GET_CODE (operands[1]) == SYMBOL_REF
		10395	&& !SYMBOL_REF_LOCAL_P (operands[1]))
		10396	{
		10397	rtx call;
		10398	rtvec tmp;
		10399
		10400	tmp = gen_rtvec (3,
		10401	gen_rtx_SET (VOIDmode,
		10402	operands[0],
		10403	gen_rtx_CALL (VOIDmode,
		10404	gen_rtx_MEM (SImode,
		10405	operands[1]),
		10406	operands[2])),
		10407	gen_rtx_USE (VOIDmode, operands[3]),
		10408	gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
		10409	call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp));
		10410	use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx);
		10411	DONE;
		10412	}
		10413
10357	if (GET_CODE (operands[1]) != SYMBOL_REF	10414	if (GET_CODE (operands[1]) != SYMBOL_REF
10358	\|\| (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))	10415	\|\| (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
10359	\|\| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))	10416	\|\| (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
Lines 10624-10630 Link Here
10624	#if TARGET_MACHO	10681	#if TARGET_MACHO
10625	return output_call(insn, operands, 0, 2);	10682	return output_call(insn, operands, 0, 2);
10626	#else	10683	#else
10627	return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";	10684	if (DEFAULT_ABI == ABI_V4 && flag_pic)
		10685	{
		10686	if (TARGET_SECURE_PLT && flag_pic == 2)
		10687	/* The magic 32768 offset here and in the other sysv call insns
		10688	corresponds to the offset of r30 in .got2, as given by LCTOC1.
		10689	See sysv4.h:toc_section. */
		10690	return "bl %z0+32768@plt";
		10691	else
		10692	return "bl %z0@plt";
		10693	}
		10694	else
		10695	return "bl %z0";
10628	#endif	10696	#endif
10629	}	10697	}
10630	[(set_attr "type" "branch,branch")	10698	[(set_attr "type" "branch,branch")
Lines 10669-10675 Link Here
10669	#if TARGET_MACHO	10737	#if TARGET_MACHO
10670	return output_call(insn, operands, 1, 3);	10738	return output_call(insn, operands, 1, 3);
10671	#else	10739	#else
10672	return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";	10740	if (DEFAULT_ABI == ABI_V4 && flag_pic)
		10741	{
		10742	if (TARGET_SECURE_PLT && flag_pic == 2)
		10743	return "bl %z1+32768@plt";
		10744	else
		10745	return "bl %z1@plt";
		10746	}
		10747	else
		10748	return "bl %z1";
10673	#endif	10749	#endif
10674	}	10750	}
10675	[(set_attr "type" "branch,branch")	10751	[(set_attr "type" "branch,branch")
Lines 10884-10890 Link Here
10884	else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)	10960	else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10885	output_asm_insn (\"creqv 6,6,6\", operands);	10961	output_asm_insn (\"creqv 6,6,6\", operands);
10886		10962
10887	return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";	10963	if (DEFAULT_ABI == ABI_V4 && flag_pic)
		10964	{
		10965	if (TARGET_SECURE_PLT && flag_pic == 2)
		10966	return \"b %z0+32768@plt\";
		10967	else
		10968	return \"b %z0@plt\";
		10969	}
		10970	else
		10971	return \"b %z0\";
10888	}"	10972	}"
10889	[(set_attr "type" "branch,branch")	10973	[(set_attr "type" "branch,branch")
10890	(set_attr "length" "4,8")])	10974	(set_attr "length" "4,8")])
Lines 10930-10936 Link Here
10930	else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)	11014	else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10931	output_asm_insn (\"creqv 6,6,6\", operands);	11015	output_asm_insn (\"creqv 6,6,6\", operands);
10932		11016
10933	return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";	11017	if (DEFAULT_ABI == ABI_V4 && flag_pic)
		11018	{
		11019	if (TARGET_SECURE_PLT && flag_pic == 2)
		11020	return \"b %z1+32768@plt\";
		11021	else
		11022	return \"b %z1@plt\";
		11023	}
		11024	else
		11025	return \"b %z1\";
10934	}"	11026	}"
10935	[(set_attr "type" "branch,branch")	11027	[(set_attr "type" "branch,branch")
10936	(set_attr "length" "4,8")])	11028	(set_attr "length" "4,8")])