Lines 24-30
Link Here
|
24 |
/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen |
24 |
/* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen |
25 |
<jpaana@s2.org> */ |
25 |
<jpaana@s2.org> */ |
26 |
|
26 |
|
27 |
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c,v 1.81 2002/01/04 21:22:33 tsi Exp $ */ |
27 |
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c,v 1.87 2002/03/18 21:47:48 mvojkovi Exp $ */ |
28 |
|
28 |
|
29 |
#include "nv_include.h" |
29 |
#include "nv_include.h" |
30 |
|
30 |
|
Lines 87-167
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|
87 |
|
87 |
|
88 |
/* Supported chipsets */ |
88 |
/* Supported chipsets */ |
89 |
static SymTabRec NVChipsets[] = { |
89 |
static SymTabRec NVChipsets[] = { |
90 |
{ NV_CHIP_RIVA128, "RIVA128" }, |
90 |
{NV_CHIP_RIVA_128, "RIVA 128"}, |
91 |
{ NV_CHIP_TNT, "RIVA TNT" }, |
91 |
{NV_CHIP_TNT, "RIVA TNT"}, |
92 |
{ NV_CHIP_TNT2, "RIVA TNT2" }, |
92 |
{NV_CHIP_TNT2, "RIVA TNT2/TNT2 Pro"}, |
93 |
{ NV_CHIP_UTNT2, "RIVA TNT2 Ultra" }, |
93 |
{NV_CHIP_UTNT2, "RIVA TNT2 Ultra"}, |
94 |
{ NV_CHIP_VTNT2, "Vanta" }, |
94 |
{NV_CHIP_VTNT2, "Vanta"}, |
95 |
{ NV_CHIP_UVTNT2, "RIVA TNT2 M64" }, |
95 |
{NV_CHIP_UVTNT2, "Riva TNT2 M64"}, |
96 |
{ NV_CHIP_ITNT2, "Aladdin TNT2" }, |
96 |
{NV_CHIP_ITNT2, "Aladdin TNT2"}, |
97 |
{ NV_CHIP_GEFORCE256, "GeForce 256" }, |
97 |
{NV_CHIP_GEFORCE_256, "GeForce 256"}, |
98 |
{ NV_CHIP_GEFORCEDDR, "GeForce DDR" }, |
98 |
{NV_CHIP_GEFORCE_DDR, "GeForce DDR"}, |
99 |
{ NV_CHIP_QUADRO, "Quadro" }, |
99 |
{NV_CHIP_QUADRO, "Quadro"}, |
100 |
{ NV_CHIP_GEFORCE2GTS, "GeForce2 GTS/Pro"}, |
100 |
{NV_CHIP_GEFORCE2_MX, "GeForce2 MX/MX 400"}, |
101 |
{ NV_CHIP_GEFORCE2GTS_1,"GeForce2 Ti"}, |
101 |
{NV_CHIP_GEFORCE2_MX_100, "GeForce2 MX 100/200"}, |
102 |
{ NV_CHIP_GEFORCE2ULTRA,"GeForce2 Ultra"}, |
102 |
{NV_CHIP_GEFORCE2_GO, "GeForce2 Go"}, |
103 |
{ NV_CHIP_QUADRO2PRO, "Quadro2 Pro"}, |
103 |
{NV_CHIP_QUADRO2_MXR, "Quadro2 MXR"}, |
104 |
{ NV_CHIP_GEFORCE2MX, "GeForce2 MX/MX 400"}, |
104 |
{NV_CHIP_GEFORCE2_GTS, "GeForce2 GTS/Pro"}, |
105 |
{ NV_CHIP_GEFORCE2MXDDR, "GeForce2 MX 100/200"}, |
105 |
{NV_CHIP_GEFORCE2_TI, "GeForce2 Ti"}, |
106 |
{ NV_CHIP_0x0170, "0x0170" }, |
106 |
{NV_CHIP_GEFORCE2_ULTRA, "GeForce2 Ultra"}, |
107 |
{ NV_CHIP_0x0171, "0x0171" }, |
107 |
{NV_CHIP_QUADRO2_PRO, "Quadro2 Pro"}, |
108 |
{ NV_CHIP_0x0172, "0x0172" }, |
108 |
{NV_CHIP_GEFORCE4_MX_460, "GeForce4 MX 460"}, |
109 |
{ NV_CHIP_0x0173, "0x0173" }, |
109 |
{NV_CHIP_GEFORCE4_MX_440, "GeForce4 MX 440"}, |
110 |
{ NV_CHIP_0x0174, "0x0174" }, |
110 |
{NV_CHIP_GEFORCE4_MX_420, "GeForce4 MX 420"}, |
111 |
{ NV_CHIP_0x0175, "0x0175" }, |
111 |
{NV_CHIP_GEFORCE4_440_GO, "GeForce4 440 Go"}, |
112 |
{ NV_CHIP_0x0178, "0x0178" }, |
112 |
{NV_CHIP_GEFORCE4_420_GO, "GeForce4 420 Go"}, |
113 |
{ NV_CHIP_0x017A, "0x017A" }, |
113 |
{NV_CHIP_GEFORCE4_420_GO_M32,"GeForce4 420 Go M32"}, |
114 |
{ NV_CHIP_0x017B, "0x017B" }, |
114 |
{NV_CHIP_QUADRO4_500XGL, "Quadro4 500XGL"}, |
115 |
{ NV_CHIP_0x017C, "0x017C" }, |
115 |
{NV_CHIP_GEFORCE4_440_GO_M64,"GeForce4 440 Go M64"}, |
116 |
{ NV_CHIP_IGEFORCE2, "GeForce2 Integrated"}, |
116 |
{NV_CHIP_QUADRO4_200, "Quadro4 200/400NVS"}, |
117 |
{ NV_CHIP_QUADRO2MXR, "Quadro2 MXR"}, |
117 |
{NV_CHIP_QUADRO4_550XGL, "Quadro4 550XGL"}, |
118 |
{ NV_CHIP_GEFORCE2GO, "GeForce2 Go"}, |
118 |
{NV_CHIP_QUADRO4_500_GOGL, "Quadro4 GoGL"}, |
119 |
{ NV_CHIP_GEFORCE3, "GeForce3"}, |
119 |
{NV_CHIP_IGEFORCE2, "GeForce2 Integrated"}, |
120 |
{ NV_CHIP_GEFORCE3_1, "GeForce3 Ti 200"}, |
120 |
{NV_CHIP_GEFORCE3, "GeForce3"}, |
121 |
{ NV_CHIP_GEFORCE3_2, "GeForce3 Ti 500"}, |
121 |
{NV_CHIP_GEFORCE3_TI_200, "GeForce3 Ti 200"}, |
122 |
{ NV_CHIP_QUADRO_DDC, "Quadro DDC"}, |
122 |
{NV_CHIP_GEFORCE3_TI_500, "GeForce3 Ti 500"}, |
123 |
{ NV_CHIP_0x0250, "0x0250"}, |
123 |
{NV_CHIP_QUADRO_DCC, "Quadro DCC"}, |
124 |
{ NV_CHIP_0x0258, "0x0258"}, |
124 |
{NV_CHIP_GEFORCE4_TI_4600, "GeForce4 Ti 4600"}, |
|
|
125 |
{NV_CHIP_GEFORCE4_TI_4400, "GeForce4 Ti 4400"}, |
126 |
{NV_CHIP_GEFORCE4_TI_4200, "GeForce4 Ti 4200"}, |
127 |
{NV_CHIP_QUADRO4_900XGL, "Quadro4 900 XGL"}, |
128 |
{NV_CHIP_QUADRO4_750XGL, "Quadro4 750 XGL"}, |
129 |
{NV_CHIP_QUADRO4_700XGL, "Quadro4 700 XGL"}, |
125 |
{-1, NULL } |
130 |
{-1, NULL } |
126 |
}; |
131 |
}; |
127 |
|
132 |
|
128 |
static PciChipsets NVPciChipsets[] = { |
133 |
static PciChipsets NVPciChipsets[] = { |
129 |
{ NV_CHIP_RIVA128, NV_CHIP_RIVA128, RES_SHARED_VGA }, |
134 |
{NV_CHIP_RIVA_128, NV_CHIP_RIVA_128, RES_SHARED_VGA}, |
130 |
{ NV_CHIP_TNT, NV_CHIP_TNT, RES_SHARED_VGA }, |
135 |
{NV_CHIP_TNT, NV_CHIP_TNT, RES_SHARED_VGA}, |
131 |
{ NV_CHIP_TNT2, NV_CHIP_TNT2, RES_SHARED_VGA }, |
136 |
{NV_CHIP_TNT2, NV_CHIP_TNT2, RES_SHARED_VGA}, |
132 |
{ NV_CHIP_UTNT2, NV_CHIP_UTNT2, RES_SHARED_VGA }, |
137 |
{NV_CHIP_UTNT2, NV_CHIP_UTNT2, RES_SHARED_VGA}, |
133 |
{ NV_CHIP_VTNT2, NV_CHIP_VTNT2, RES_SHARED_VGA }, |
138 |
{NV_CHIP_VTNT2, NV_CHIP_VTNT2, RES_SHARED_VGA}, |
134 |
{ NV_CHIP_UVTNT2, NV_CHIP_UVTNT2, RES_SHARED_VGA }, |
139 |
{NV_CHIP_UVTNT2, NV_CHIP_UVTNT2, RES_SHARED_VGA}, |
135 |
{ NV_CHIP_ITNT2, NV_CHIP_ITNT2, RES_SHARED_VGA }, |
140 |
{NV_CHIP_ITNT2, NV_CHIP_ITNT2, RES_SHARED_VGA}, |
136 |
{ NV_CHIP_GEFORCE256, NV_CHIP_GEFORCE256, RES_SHARED_VGA }, |
141 |
{NV_CHIP_GEFORCE_256, NV_CHIP_GEFORCE_256, RES_SHARED_VGA}, |
137 |
{ NV_CHIP_GEFORCEDDR, NV_CHIP_GEFORCEDDR, RES_SHARED_VGA }, |
142 |
{NV_CHIP_GEFORCE_DDR, NV_CHIP_GEFORCE_DDR, RES_SHARED_VGA}, |
138 |
{ NV_CHIP_QUADRO, NV_CHIP_QUADRO, RES_SHARED_VGA }, |
143 |
{NV_CHIP_QUADRO, NV_CHIP_QUADRO, RES_SHARED_VGA}, |
139 |
{ NV_CHIP_GEFORCE2GTS, NV_CHIP_GEFORCE2GTS, RES_SHARED_VGA }, |
144 |
{NV_CHIP_GEFORCE2_MX, NV_CHIP_GEFORCE2_MX, RES_SHARED_VGA}, |
140 |
{ NV_CHIP_GEFORCE2GTS_1, NV_CHIP_GEFORCE2GTS_1, RES_SHARED_VGA }, |
145 |
{NV_CHIP_GEFORCE2_MX_100, NV_CHIP_GEFORCE2_MX_100, RES_SHARED_VGA}, |
141 |
{ NV_CHIP_GEFORCE2ULTRA, NV_CHIP_GEFORCE2ULTRA, RES_SHARED_VGA }, |
146 |
{NV_CHIP_GEFORCE2_GO, NV_CHIP_GEFORCE2_GO, RES_SHARED_VGA}, |
142 |
{ NV_CHIP_QUADRO2PRO, NV_CHIP_QUADRO2PRO, RES_SHARED_VGA }, |
147 |
{NV_CHIP_QUADRO2_MXR, NV_CHIP_QUADRO2_MXR, RES_SHARED_VGA}, |
143 |
{ NV_CHIP_GEFORCE2MX, NV_CHIP_GEFORCE2MX, RES_SHARED_VGA }, |
148 |
{NV_CHIP_GEFORCE2_GTS, NV_CHIP_GEFORCE2_GTS, RES_SHARED_VGA}, |
144 |
{ NV_CHIP_GEFORCE2MXDDR, NV_CHIP_GEFORCE2MXDDR, RES_SHARED_VGA }, |
149 |
{NV_CHIP_GEFORCE2_TI, NV_CHIP_GEFORCE2_TI, RES_SHARED_VGA}, |
145 |
{ NV_CHIP_0x0170, NV_CHIP_0x0170, RES_SHARED_VGA }, |
150 |
{NV_CHIP_GEFORCE2_ULTRA, NV_CHIP_GEFORCE2_ULTRA, RES_SHARED_VGA}, |
146 |
{ NV_CHIP_0x0171, NV_CHIP_0x0171, RES_SHARED_VGA }, |
151 |
{NV_CHIP_QUADRO2_PRO, NV_CHIP_QUADRO2_PRO, RES_SHARED_VGA}, |
147 |
{ NV_CHIP_0x0172, NV_CHIP_0x0172, RES_SHARED_VGA }, |
152 |
{NV_CHIP_GEFORCE4_MX_460, NV_CHIP_GEFORCE4_MX_460, RES_SHARED_VGA}, |
148 |
{ NV_CHIP_0x0173, NV_CHIP_0x0173, RES_SHARED_VGA }, |
153 |
{NV_CHIP_GEFORCE4_MX_440, NV_CHIP_GEFORCE4_MX_440, RES_SHARED_VGA}, |
149 |
{ NV_CHIP_0x0174, NV_CHIP_0x0174, RES_SHARED_VGA }, |
154 |
{NV_CHIP_GEFORCE4_MX_420, NV_CHIP_GEFORCE4_MX_420, RES_SHARED_VGA}, |
150 |
{ NV_CHIP_0x0175, NV_CHIP_0x0175, RES_SHARED_VGA }, |
155 |
{NV_CHIP_GEFORCE4_440_GO, NV_CHIP_GEFORCE4_440_GO, RES_SHARED_VGA}, |
151 |
{ NV_CHIP_0x0178, NV_CHIP_0x0178, RES_SHARED_VGA }, |
156 |
{NV_CHIP_GEFORCE4_420_GO, NV_CHIP_GEFORCE4_420_GO, RES_SHARED_VGA}, |
152 |
{ NV_CHIP_0x017A, NV_CHIP_0x017A, RES_SHARED_VGA }, |
157 |
{NV_CHIP_GEFORCE4_420_GO_M32,NV_CHIP_GEFORCE4_420_GO_M32,RES_SHARED_VGA}, |
153 |
{ NV_CHIP_0x017B, NV_CHIP_0x017B, RES_SHARED_VGA }, |
158 |
{NV_CHIP_QUADRO4_500XGL, NV_CHIP_QUADRO4_500XGL, RES_SHARED_VGA}, |
154 |
{ NV_CHIP_0x017C, NV_CHIP_0x017C, RES_SHARED_VGA }, |
159 |
{NV_CHIP_GEFORCE4_440_GO_M64,NV_CHIP_GEFORCE4_440_GO_M64,RES_SHARED_VGA}, |
155 |
{ NV_CHIP_IGEFORCE2, NV_CHIP_IGEFORCE2, RES_SHARED_VGA }, |
160 |
{NV_CHIP_QUADRO4_200, NV_CHIP_QUADRO4_200, RES_SHARED_VGA}, |
156 |
{ NV_CHIP_QUADRO2MXR, NV_CHIP_QUADRO2MXR, RES_SHARED_VGA }, |
161 |
{NV_CHIP_QUADRO4_550XGL, NV_CHIP_QUADRO4_550XGL, RES_SHARED_VGA}, |
157 |
{ NV_CHIP_GEFORCE2GO, NV_CHIP_GEFORCE2GO, RES_SHARED_VGA }, |
162 |
{NV_CHIP_QUADRO4_500_GOGL, NV_CHIP_QUADRO4_500_GOGL, RES_SHARED_VGA}, |
158 |
{ NV_CHIP_GEFORCE3, NV_CHIP_GEFORCE3, RES_SHARED_VGA }, |
163 |
{NV_CHIP_IGEFORCE2, NV_CHIP_IGEFORCE2, RES_SHARED_VGA}, |
159 |
{ NV_CHIP_GEFORCE3_1, NV_CHIP_GEFORCE3_1, RES_SHARED_VGA }, |
164 |
{NV_CHIP_GEFORCE3, NV_CHIP_GEFORCE3, RES_SHARED_VGA}, |
160 |
{ NV_CHIP_GEFORCE3_2, NV_CHIP_GEFORCE3_2, RES_SHARED_VGA }, |
165 |
{NV_CHIP_GEFORCE3_TI_200, NV_CHIP_GEFORCE3_TI_200, RES_SHARED_VGA}, |
161 |
{ NV_CHIP_QUADRO_DDC, NV_CHIP_QUADRO_DDC, RES_SHARED_VGA }, |
166 |
{NV_CHIP_GEFORCE3_TI_500, NV_CHIP_GEFORCE3_TI_500, RES_SHARED_VGA}, |
162 |
{ NV_CHIP_0x0250, NV_CHIP_0x0250, RES_SHARED_VGA }, |
167 |
{NV_CHIP_QUADRO_DCC, NV_CHIP_QUADRO_DCC, RES_SHARED_VGA}, |
163 |
{ NV_CHIP_0x0258, NV_CHIP_0x0258, RES_SHARED_VGA }, |
168 |
{NV_CHIP_GEFORCE4_TI_4600, NV_CHIP_GEFORCE4_TI_4600, RES_SHARED_VGA}, |
164 |
{ -1, -1, RES_UNDEFINED } |
169 |
{NV_CHIP_GEFORCE4_TI_4400, NV_CHIP_GEFORCE4_TI_4400, RES_SHARED_VGA}, |
|
|
170 |
{NV_CHIP_GEFORCE4_TI_4200, NV_CHIP_GEFORCE4_TI_4200, RES_SHARED_VGA}, |
171 |
{NV_CHIP_QUADRO4_900XGL, NV_CHIP_QUADRO4_900XGL, RES_SHARED_VGA}, |
172 |
{NV_CHIP_QUADRO4_750XGL, NV_CHIP_QUADRO4_750XGL, RES_SHARED_VGA}, |
173 |
{NV_CHIP_QUADRO4_700XGL, NV_CHIP_QUADRO4_700XGL, RES_SHARED_VGA}, |
174 |
{ -1, -1, RES_UNDEFINED } |
165 |
}; |
175 |
}; |
166 |
|
176 |
|
167 |
/* |
177 |
/* |
Lines 179-191
Link Here
|
179 |
"vgaHWGetHWRec", |
189 |
"vgaHWGetHWRec", |
180 |
"vgaHWGetIndex", |
190 |
"vgaHWGetIndex", |
181 |
"vgaHWInit", |
191 |
"vgaHWInit", |
182 |
"vgaHWLock", |
|
|
183 |
"vgaHWMapMem", |
192 |
"vgaHWMapMem", |
184 |
"vgaHWProtect", |
193 |
"vgaHWProtect", |
185 |
"vgaHWRestore", |
194 |
"vgaHWRestore", |
186 |
"vgaHWSave", |
195 |
"vgaHWSave", |
187 |
"vgaHWSaveScreen", |
196 |
"vgaHWSaveScreen", |
188 |
"vgaHWUnlock", |
|
|
189 |
"vgaHWddc1SetSpeed", |
197 |
"vgaHWddc1SetSpeed", |
190 |
NULL |
198 |
NULL |
191 |
}; |
199 |
}; |
Lines 305-311
Link Here
|
305 |
OPTION_FBDEV, |
313 |
OPTION_FBDEV, |
306 |
OPTION_ROTATE, |
314 |
OPTION_ROTATE, |
307 |
OPTION_VIDEO_KEY, |
315 |
OPTION_VIDEO_KEY, |
308 |
OPTION_FLAT_PANEL |
316 |
OPTION_FLAT_PANEL, |
|
|
317 |
OPTION_CRTC_NUMBER |
309 |
} NVOpts; |
318 |
} NVOpts; |
310 |
|
319 |
|
311 |
|
320 |
|
Lines 319-324
Link Here
|
319 |
{ OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE }, |
328 |
{ OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE }, |
320 |
{ OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, |
329 |
{ OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, |
321 |
{ OPTION_FLAT_PANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE }, |
330 |
{ OPTION_FLAT_PANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE }, |
|
|
331 |
{ OPTION_CRTC_NUMBER, "CrtcNumber", OPTV_INTEGER, {0}, FALSE }, |
322 |
{ -1, NULL, OPTV_NONE, {0}, FALSE } |
332 |
{ -1, NULL, OPTV_NONE, {0}, FALSE } |
323 |
}; |
333 |
}; |
324 |
|
334 |
|
Lines 333-339
Link Here
|
333 |
*/ |
343 |
*/ |
334 |
static NVRamdacRec DacInit = { |
344 |
static NVRamdacRec DacInit = { |
335 |
FALSE, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, |
345 |
FALSE, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, |
336 |
0, NULL, NULL, NULL, NULL, NULL |
346 |
0, NULL, NULL, NULL, NULL |
337 |
}; |
347 |
}; |
338 |
|
348 |
|
339 |
|
349 |
|
Lines 565-577
Link Here
|
565 |
NVEnterVT(int scrnIndex, int flags) |
575 |
NVEnterVT(int scrnIndex, int flags) |
566 |
{ |
576 |
{ |
567 |
ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; |
577 |
ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; |
568 |
NVPtr pNv = NVPTR(pScrn); |
|
|
569 |
vgaHWPtr hwp = VGAHWPTR(pScrn); |
570 |
|
578 |
|
571 |
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVEnterVT\n")); |
579 |
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVEnterVT\n")); |
572 |
|
580 |
|
573 |
vgaHWUnlock(hwp); |
|
|
574 |
pNv->riva.LockUnlock(&pNv->riva, 0); |
575 |
if (!NVModeInit(pScrn, pScrn->currentMode)) |
581 |
if (!NVModeInit(pScrn, pScrn->currentMode)) |
576 |
return FALSE; |
582 |
return FALSE; |
577 |
NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); |
583 |
NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); |
Lines 600-612
Link Here
|
600 |
{ |
606 |
{ |
601 |
ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; |
607 |
ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; |
602 |
NVPtr pNv = NVPTR(pScrn); |
608 |
NVPtr pNv = NVPTR(pScrn); |
603 |
vgaHWPtr hwp = VGAHWPTR(pScrn); |
|
|
604 |
|
609 |
|
605 |
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVLeaveVT\n")); |
610 |
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVLeaveVT\n")); |
606 |
|
611 |
|
607 |
NVRestore(pScrn); |
612 |
NVRestore(pScrn); |
608 |
pNv->riva.LockUnlock(&pNv->riva, 1); |
613 |
pNv->riva.LockUnlock(&pNv->riva, 1); |
609 |
vgaHWLock(hwp); |
|
|
610 |
} |
614 |
} |
611 |
|
615 |
|
612 |
|
616 |
|
Lines 645-651
Link Here
|
645 |
NVCloseScreen(int scrnIndex, ScreenPtr pScreen) |
649 |
NVCloseScreen(int scrnIndex, ScreenPtr pScreen) |
646 |
{ |
650 |
{ |
647 |
ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; |
651 |
ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; |
648 |
vgaHWPtr hwp = VGAHWPTR(pScrn); |
|
|
649 |
NVPtr pNv = NVPTR(pScrn); |
652 |
NVPtr pNv = NVPTR(pScrn); |
650 |
|
653 |
|
651 |
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVCloseScreen\n")); |
654 |
DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVCloseScreen\n")); |
Lines 653-659
Link Here
|
653 |
if (pScrn->vtSema) { |
656 |
if (pScrn->vtSema) { |
654 |
NVRestore(pScrn); |
657 |
NVRestore(pScrn); |
655 |
pNv->riva.LockUnlock(&pNv->riva, 1); |
658 |
pNv->riva.LockUnlock(&pNv->riva, 1); |
656 |
vgaHWLock(hwp); |
|
|
657 |
} |
659 |
} |
658 |
|
660 |
|
659 |
NVUnmapMem(pScrn); |
661 |
NVUnmapMem(pScrn); |
Lines 779-793
Link Here
|
779 |
|
781 |
|
780 |
|
782 |
|
781 |
/* Internally used */ |
783 |
/* Internally used */ |
782 |
static xf86MonPtr |
784 |
xf86MonPtr |
783 |
NVdoDDC(ScrnInfoPtr pScrn) |
785 |
NVdoDDC(ScrnInfoPtr pScrn) |
784 |
{ |
786 |
{ |
785 |
vgaHWPtr hwp; |
|
|
786 |
NVPtr pNv; |
787 |
NVPtr pNv; |
787 |
NVRamdacPtr NVdac; |
788 |
NVRamdacPtr NVdac; |
788 |
xf86MonPtr MonInfo = NULL; |
789 |
xf86MonPtr MonInfo = NULL; |
789 |
|
790 |
|
790 |
hwp = VGAHWPTR(pScrn); |
|
|
791 |
pNv = NVPTR(pScrn); |
791 |
pNv = NVPTR(pScrn); |
792 |
NVdac = &pNv->Dac; |
792 |
NVdac = &pNv->Dac; |
793 |
|
793 |
|
Lines 800-806
Link Here
|
800 |
/* if ((MonInfo = nvDoDDCVBE(pScrn))) return MonInfo; */ |
800 |
/* if ((MonInfo = nvDoDDCVBE(pScrn))) return MonInfo; */ |
801 |
|
801 |
|
802 |
/* Enable access to extended registers */ |
802 |
/* Enable access to extended registers */ |
803 |
vgaHWUnlock(hwp); |
|
|
804 |
pNv->riva.LockUnlock(&pNv->riva, 0); |
803 |
pNv->riva.LockUnlock(&pNv->riva, 0); |
805 |
/* Save the current state */ |
804 |
/* Save the current state */ |
806 |
NVSave(pScrn); |
805 |
NVSave(pScrn); |
Lines 814-820
Link Here
|
814 |
/* Restore previous state */ |
813 |
/* Restore previous state */ |
815 |
NVRestore(pScrn); |
814 |
NVRestore(pScrn); |
816 |
pNv->riva.LockUnlock(&pNv->riva, 1); |
815 |
pNv->riva.LockUnlock(&pNv->riva, 1); |
817 |
vgaHWLock(hwp); |
|
|
818 |
|
816 |
|
819 |
return MonInfo; |
817 |
return MonInfo; |
820 |
} |
818 |
} |
Lines 972-978
Link Here
|
972 |
/* OK */ |
970 |
/* OK */ |
973 |
break; |
971 |
break; |
974 |
case 16: |
972 |
case 16: |
975 |
if(pNv->Chipset == NV_CHIP_RIVA128) { |
973 |
if(pNv->Chipset == NV_CHIP_RIVA_128) { |
976 |
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, |
974 |
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, |
977 |
"The Riva 128 chipset does not support depth 16. " |
975 |
"The Riva 128 chipset does not support depth 16. " |
978 |
"Using depth 15 instead\n"); |
976 |
"Using depth 15 instead\n"); |
Lines 1141-1150
Link Here
|
1141 |
(((pScrn->mask.blue >> pScrn->offset.blue) - 1) << pScrn->offset.blue); |
1139 |
(((pScrn->mask.blue >> pScrn->offset.blue) - 1) << pScrn->offset.blue); |
1142 |
} |
1140 |
} |
1143 |
|
1141 |
|
1144 |
if (xf86ReturnOptValBool(pNv->Options, OPTION_FLAT_PANEL, FALSE)) { |
1142 |
if (xf86GetOptValBool(pNv->Options, OPTION_FLAT_PANEL, &(pNv->FlatPanel))) { |
1145 |
pNv->FlatPanel = TRUE; |
1143 |
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "forcing %s usage\n", |
1146 |
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "using flat panel\n"); |
1144 |
pNv->FlatPanel ? "DFP" : "CRTC"); |
|
|
1145 |
} else { |
1146 |
pNv->FlatPanel = -1; /* autodetect later */ |
1147 |
} |
1147 |
} |
|
|
1148 |
|
1149 |
if (xf86GetOptValInteger(pNv->Options, OPTION_CRTC_NUMBER, |
1150 |
&pNv->forceCRTC)) |
1151 |
{ |
1152 |
if((pNv->forceCRTC < 0) || (pNv->forceCRTC > 1)) { |
1153 |
pNv->forceCRTC = -1; |
1154 |
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, |
1155 |
"Invalid CRTC number. Must be 0 or 1\n"); |
1156 |
} |
1157 |
} else pNv->forceCRTC = -1; |
1158 |
|
1148 |
|
1159 |
|
1149 |
if (pNv->pEnt->device->MemBase != 0) { |
1160 |
if (pNv->pEnt->device->MemBase != 0) { |
1150 |
/* Require that the config file value matches one of the PCI values. */ |
1161 |
/* Require that the config file value matches one of the PCI values. */ |
Lines 1233-1244
Link Here
|
1233 |
} |
1244 |
} |
1234 |
|
1245 |
|
1235 |
/* |
1246 |
/* |
1236 |
* fill riva structure etc. |
|
|
1237 |
*/ |
1238 |
(*pNv->PreInit)(pScrn); |
1239 |
|
1240 |
|
1241 |
/* |
1242 |
* If the user has specified the amount of memory in the XF86Config |
1247 |
* If the user has specified the amount of memory in the XF86Config |
1243 |
* file, we respect that setting. |
1248 |
* file, we respect that setting. |
1244 |
*/ |
1249 |
*/ |
Lines 1258-1299
Link Here
|
1258 |
|
1263 |
|
1259 |
pNv->FbMapSize = pScrn->videoRam * 1024; |
1264 |
pNv->FbMapSize = pScrn->videoRam * 1024; |
1260 |
|
1265 |
|
1261 |
#if !defined(__powerpc__) |
|
|
1262 |
/* Read and print the Monitor DDC info */ |
1263 |
pScrn->monitor->DDC = NVdoDDC(pScrn); |
1264 |
#endif |
1265 |
|
1266 |
#if 0 |
1267 |
/* |
1268 |
* This code was for testing. It will be removed as soon |
1269 |
* as this is integrated into the common level. |
1270 |
*/ |
1271 |
if ((!pScrn->monitor->nHsync || !pScrn->monitor->nVrefresh) |
1272 |
&& pScrn->monitor->DDC) { |
1273 |
int i; |
1274 |
int h = (!pScrn->monitor->nHsync) ? 0 : -1; |
1275 |
int v = (!pScrn->monitor->nVrefresh) ? 0 : -1; |
1276 |
xf86MonPtr pMon = (xf86MonPtr)pScrn->monitor->DDC; |
1277 |
for (i = 0; i < DET_TIMINGS; i++) { |
1278 |
if (pMon->det_mon[i].type == DS_RANGES) { |
1279 |
if (h != -1) { |
1280 |
pScrn->monitor->hsync[h].lo |
1281 |
= pMon->det_mon[i].section.ranges.min_h; |
1282 |
pScrn->monitor->hsync[h++].hi |
1283 |
= pMon->det_mon[i].section.ranges.max_h; |
1284 |
} |
1285 |
if (v != -1) { |
1286 |
pScrn->monitor->vrefresh[v].lo |
1287 |
= pMon->det_mon[i].section.ranges.min_v; |
1288 |
pScrn->monitor->vrefresh[v++].hi |
1289 |
= pMon->det_mon[i].section.ranges.max_v; |
1290 |
} |
1291 |
} |
1292 |
} |
1293 |
if (h != -1) pScrn->monitor->nHsync = h; |
1294 |
if (v != -1) pScrn->monitor->nVrefresh = v; |
1295 |
} |
1296 |
#endif |
1297 |
/* |
1266 |
/* |
1298 |
* If the driver can do gamma correction, it should call xf86SetGamma() |
1267 |
* If the driver can do gamma correction, it should call xf86SetGamma() |
1299 |
* here. |
1268 |
* here. |
Lines 1318-1323
Link Here
|
1318 |
case NV_ARCH_04: |
1287 |
case NV_ARCH_04: |
1319 |
case NV_ARCH_10: |
1288 |
case NV_ARCH_10: |
1320 |
case NV_ARCH_20: |
1289 |
case NV_ARCH_20: |
|
|
1290 |
default: |
1321 |
pNv->FbUsableSize -= 128 * 1024; |
1291 |
pNv->FbUsableSize -= 128 * 1024; |
1322 |
break; |
1292 |
break; |
1323 |
} |
1293 |
} |
Lines 1344-1349
Link Here
|
1344 |
clockRanges->interlaceAllowed = FALSE; |
1314 |
clockRanges->interlaceAllowed = FALSE; |
1345 |
clockRanges->doubleScanAllowed = TRUE; |
1315 |
clockRanges->doubleScanAllowed = TRUE; |
1346 |
|
1316 |
|
|
|
1317 |
if(pNv->FlatPanel == 1) { |
1318 |
clockRanges->interlaceAllowed = FALSE; |
1319 |
clockRanges->doubleScanAllowed = FALSE; |
1320 |
} |
1321 |
|
1347 |
/* |
1322 |
/* |
1348 |
* xf86ValidateModes will check that the mode HTotal and VTotal values |
1323 |
* xf86ValidateModes will check that the mode HTotal and VTotal values |
1349 |
* don't exceed the chipset's limit if pScrn->maxHValue and |
1324 |
* don't exceed the chipset's limit if pScrn->maxHValue and |
Lines 1538-1546
Link Here
|
1538 |
|
1513 |
|
1539 |
|
1514 |
|
1540 |
/* |
1515 |
/* |
1541 |
* Initialise a new mode. This is currently still using the old |
1516 |
* Initialise a new mode. |
1542 |
* "initialise struct, restore/write struct to HW" model. That could |
|
|
1543 |
* be changed. |
1544 |
*/ |
1517 |
*/ |
1545 |
|
1518 |
|
1546 |
static Bool |
1519 |
static Bool |
Lines 1558-1575
Link Here
|
1558 |
return FALSE; |
1531 |
return FALSE; |
1559 |
pScrn->vtSema = TRUE; |
1532 |
pScrn->vtSema = TRUE; |
1560 |
|
1533 |
|
1561 |
if ( pNv->ModeInit ) { |
1534 |
if(!(*pNv->ModeInit)(pScrn, mode)) |
1562 |
if (!(*pNv->ModeInit)(pScrn, mode)) |
1535 |
return FALSE; |
1563 |
return FALSE; |
|
|
1564 |
} |
1565 |
|
1536 |
|
1566 |
/* Program the registers */ |
1537 |
/* Program the registers */ |
1567 |
vgaHWProtect(pScrn, TRUE); |
1538 |
vgaHWProtect(pScrn, TRUE); |
1568 |
vgaReg = &hwp->ModeReg; |
1539 |
vgaReg = &hwp->ModeReg; |
1569 |
nvReg = &pNv->ModeReg; |
1540 |
nvReg = &pNv->ModeReg; |
1570 |
|
1541 |
|
1571 |
if ( pNv->Restore ) |
1542 |
(*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE); |
1572 |
(*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE); |
|
|
1573 |
|
1543 |
|
1574 |
#if X_BYTE_ORDER == X_BIG_ENDIAN |
1544 |
#if X_BYTE_ORDER == X_BIG_ENDIAN |
1575 |
/* turn on LFB swapping */ |
1545 |
/* turn on LFB swapping */ |
Lines 1606-1615
Link Here
|
1606 |
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVRestore\n")); |
1576 |
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVRestore\n")); |
1607 |
/* Only restore text mode fonts/text for the primary card */ |
1577 |
/* Only restore text mode fonts/text for the primary card */ |
1608 |
vgaHWProtect(pScrn, TRUE); |
1578 |
vgaHWProtect(pScrn, TRUE); |
1609 |
if (pNv->Primary) |
1579 |
(*pNv->Restore)(pScrn, vgaReg, nvReg, pNv->Primary); |
1610 |
(*pNv->Restore)(pScrn, vgaReg, nvReg, TRUE); |
|
|
1611 |
else |
1612 |
vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE); |
1613 |
vgaHWProtect(pScrn, FALSE); |
1580 |
vgaHWProtect(pScrn, FALSE); |
1614 |
} |
1581 |
} |
1615 |
|
1582 |
|
Lines 1666-1672
Link Here
|
1666 |
return FALSE; |
1633 |
return FALSE; |
1667 |
} else { |
1634 |
} else { |
1668 |
/* Save the current state */ |
1635 |
/* Save the current state */ |
1669 |
vgaHWUnlock(hwp); |
|
|
1670 |
pNv->riva.LockUnlock(&pNv->riva, 0); |
1636 |
pNv->riva.LockUnlock(&pNv->riva, 0); |
1671 |
NVSave(pScrn); |
1637 |
NVSave(pScrn); |
1672 |
/* Initialise the first mode */ |
1638 |
/* Initialise the first mode */ |
Lines 1897-1908
Link Here
|
1897 |
vgaRegPtr vgaReg = &pVga->SavedReg; |
1863 |
vgaRegPtr vgaReg = &pVga->SavedReg; |
1898 |
|
1864 |
|
1899 |
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVSave\n")); |
1865 |
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVSave\n")); |
1900 |
#if defined(__powerpc__) |
1866 |
(*pNv->Save)(pScrn, vgaReg, nvReg, pNv->Primary); |
1901 |
/* The console driver will have to save the fonts, we can't */ |
|
|
1902 |
vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE); |
1903 |
#else |
1904 |
vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE | VGA_SR_FONTS); |
1905 |
#endif |
1906 |
pNv->riva.UnloadStateExt(&pNv->riva, nvReg); |
1907 |
} |
1867 |
} |
1908 |
|
1868 |
|