diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man Mon Dec 17 21:52:33 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man Wed Feb 20 00:39:50 2002 @@ -1,4 +1,4 @@ -.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man,v 1.7 2001/12/17 20:52:33 dawes Exp $ +.\" $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv.man,v 1.10 2002/02/19 23:39:50 mvojkovi Exp $ .\" shorthand for double quote that works everywhere. .ds q \N'34' .TH NV __drivermansuffix__ __vendorversion__ @@ -39,12 +39,13 @@ NV10 .TP 22 .B GeForce2, QUADRO2 -NV11 & NV15 (except GeForce2 Go, which is -.B NOT -supported) +NV11 & NV15 .TP 22 .B GeForce3 NV20 +.TP 22 +.B GeForce4, QUADRO4 +NV17 & NV25 .SH CONFIGURATION DETAILS Please refer to XF86Config(__filemansuffix__) for general configuration details. This section only covers configuration details specific to this @@ -68,6 +69,19 @@ on all OSs). See fbdevhw(__drivermansuffix__) for further information. Default: off. .TP +.BI "Option \*qCrtcNumber\*q \*q" integer \*q +NV17 and NV25 can have two video outputs. The driver attempts to autodetect +which one the monitor is connected to. In the case that autodetection picks +the wrong one, this option may be used to force usage of a particular output. +The options are "0" or "1". +Default: autodetected. +.TP +.BI "Option \*qFlatPanel\*q \*q" boolean \*q +This driver has experimental flat panel support for some chips. The driver +cannot autodetect the presence of a flat panel so this option must be set +when used with a flat panel. +Default: off. +.TP .BI "Option \*qRotate\*q \*qCW\*q" .TP .BI "Option \*qRotate\*q \*qCCW\*q" diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c Mon Dec 17 23:17:55 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c Wed Feb 6 02:33:06 2002 @@ -24,7 +24,7 @@ /* Rewritten with reference from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c,v 1.5 2001/12/17 22:17:55 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_cursor.c,v 1.7 2002/02/06 01:33:06 mvojkovi Exp $ */ #include "nv_include.h" @@ -109,7 +109,7 @@ NVPtr pNv = NVPTR(pScrn); pNv->riva.ShowHideCursor(&pNv->riva, 0); - *(pNv->riva.CURSORPOS) = (x & 0xFFFF) | (y << 16); + pNv->riva.PRAMDAC[0x0000300/4] = (x & 0xFFFF) | (y << 16); pNv->riva.ShowHideCursor(&pNv->riva, 1); } @@ -123,8 +123,10 @@ back = ConvertToRGB555(bg); #if X_BYTE_ORDER == X_BIG_ENDIAN - fore = (fore << 8) | (fore >> 8); - back = (back << 8) | (back >> 8); + if((pNv->Chipset & 0x0ff0) == 0x0110) { + fore = (fore << 8) | (fore >> 8); + back = (back << 8) | (back >> 8); + } #endif if (pNv->curFg != fore || pNv->curBg != back) { diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c Tue Dec 11 20:42:01 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c Thu Apr 4 16:05:45 2002 @@ -24,7 +24,7 @@ /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c,v 1.15 2001/12/11 19:42:01 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dac.c,v 1.26 2002/04/04 14:05:45 eich Exp $ */ #include "nv_include.h" @@ -71,6 +71,15 @@ if(mode->Flags & V_INTERLACE) vertTotal |= 1; + if(pNv->FlatPanel == 1) { + vertStart = vertTotal - 3; + vertEnd = vertTotal - 2; + vertBlankStart = vertStart; + horizStart = horizTotal - 3; + horizEnd = horizTotal - 2; + horizBlankEnd = horizTotal + 4; + } + pVga->CRTC[0x0] = Set8Bits(horizTotal); pVga->CRTC[0x1] = Set8Bits(horizDisplay); pVga->CRTC[0x2] = Set8Bits(horizBlankStart); @@ -147,6 +156,8 @@ if(pNv->riva.Architecture >= NV_ARCH_10) pNv->riva.CURSOR = (U032 *)(pNv->FbStart + pNv->riva.CursorStart); + pNv->riva.LockUnlock(&pNv->riva, 0); + pNv->riva.CalcStateExt(&pNv->riva, nvReg, i, @@ -156,21 +167,45 @@ mode->Clock, mode->Flags); + nvReg->scale = pNv->riva.PRAMDAC[0x00000848/4] & 0xfff000ff; + if(pNv->FlatPanel == 1) { + nvReg->pixel |= (1 << 7); + nvReg->scale |= (1 << 8) ; + } + if(pNv->SecondCRTC) { + nvReg->head = pNv->riva.PCRTC0[0x00000860/4] & ~0x00001000; + nvReg->head2 = pNv->riva.PCRTC0[0x00002860/4] | 0x00001000; + nvReg->crtcOwner = 3; + nvReg->pllsel |= 0x20000800; + nvReg->vpll2 = nvReg->vpll; + } else + if(pNv->riva.twoHeads) { + nvReg->head = pNv->riva.PCRTC0[0x00000860/4] | 0x00001000; + nvReg->head2 = pNv->riva.PCRTC0[0x00002860/4] & ~0x00001000; + nvReg->crtcOwner = 0; + nvReg->vpll2 = pNv->riva.PRAMDAC0[0x00000520/4]; + } + return (TRUE); } void NVDACRestore(ScrnInfoPtr pScrn, vgaRegPtr vgaReg, NVRegPtr nvReg, - Bool restoreFonts) + Bool primary) { NVPtr pNv = NVPTR(pScrn); + int restore = VGA_SR_MODE; + DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVDACRestore\n")); + + if(primary) restore |= VGA_SR_CMAP | VGA_SR_FONTS; + else if(pNv->Chipset == NV_CHIP_RIVA_128) + restore |= VGA_SR_CMAP; pNv->riva.LoadStateExt(&pNv->riva, nvReg); #if defined(__powerpc__) - restoreFonts = FALSE; + restore &= ~VGA_SR_FONTS; #endif - vgaHWRestore(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE | - (restoreFonts? VGA_SR_FONTS : 0)); + vgaHWRestore(pScrn, vgaReg, restore); } /* @@ -184,8 +219,17 @@ { NVPtr pNv = NVPTR(pScrn); DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVDACSave\n")); - vgaHWSave(pScrn, vgaReg, VGA_SR_MODE | (saveFonts? VGA_SR_FONTS : 0)); + +#if defined(__powerpc__) + saveFonts = FALSE; +#endif + + vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE | + (saveFonts? VGA_SR_FONTS : 0)); pNv->riva.UnloadStateExt(&pNv->riva, nvReg); + + if((pNv->Chipset & 0x0ff0) == 0x0110) + nvReg->crtcOwner = ((pNv->Chipset & 0x0fff) == 0x0112) ? 3 : 0; } #define DEPTH_SHIFT(val, w) ((val << (8 - w)) | (val >> ((w << 1) - 8))) diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c Mon Jan 22 22:32:36 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c Fri Jan 25 22:56:06 2002 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c,v 1.10 2001/01/22 21:32:36 dawes Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_dga.c,v 1.11 2002/01/25 21:56:06 tsi Exp $ */ #include "nv_local.h" #include "nv_include.h" @@ -234,8 +234,8 @@ NVAdjustFrame(pScrn->pScreen->myNum, x, y, flags); - while(pNv->riva.PCIO[0x3da] & 0x08); - while(!(pNv->riva.PCIO[0x3da] & 0x08)); + while(VGA_RD08(pNv->riva.PCIO, 0x3da) & 0x08); + while(!(VGA_RD08(pNv->riva.PCIO, 0x3da) & 0x08)); pNv->DGAViewportStatus = 0; } diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c Fri Jan 4 22:22:33 2002 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c Mon Mar 18 22:47:48 2002 @@ -24,7 +24,7 @@ /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c,v 1.81 2002/01/04 21:22:33 tsi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_driver.c,v 1.87 2002/03/18 21:47:48 mvojkovi Exp $ */ #include "nv_include.h" @@ -87,81 +87,91 @@ /* Supported chipsets */ static SymTabRec NVChipsets[] = { - { NV_CHIP_RIVA128, "RIVA128" }, - { NV_CHIP_TNT, "RIVA TNT" }, - { NV_CHIP_TNT2, "RIVA TNT2" }, - { NV_CHIP_UTNT2, "RIVA TNT2 Ultra" }, - { NV_CHIP_VTNT2, "Vanta" }, - { NV_CHIP_UVTNT2, "RIVA TNT2 M64" }, - { NV_CHIP_ITNT2, "Aladdin TNT2" }, - { NV_CHIP_GEFORCE256, "GeForce 256" }, - { NV_CHIP_GEFORCEDDR, "GeForce DDR" }, - { NV_CHIP_QUADRO, "Quadro" }, - { NV_CHIP_GEFORCE2GTS, "GeForce2 GTS/Pro"}, - { NV_CHIP_GEFORCE2GTS_1,"GeForce2 Ti"}, - { NV_CHIP_GEFORCE2ULTRA,"GeForce2 Ultra"}, - { NV_CHIP_QUADRO2PRO, "Quadro2 Pro"}, - { NV_CHIP_GEFORCE2MX, "GeForce2 MX/MX 400"}, - { NV_CHIP_GEFORCE2MXDDR, "GeForce2 MX 100/200"}, - { NV_CHIP_0x0170, "0x0170" }, - { NV_CHIP_0x0171, "0x0171" }, - { NV_CHIP_0x0172, "0x0172" }, - { NV_CHIP_0x0173, "0x0173" }, - { NV_CHIP_0x0174, "0x0174" }, - { NV_CHIP_0x0175, "0x0175" }, - { NV_CHIP_0x0178, "0x0178" }, - { NV_CHIP_0x017A, "0x017A" }, - { NV_CHIP_0x017B, "0x017B" }, - { NV_CHIP_0x017C, "0x017C" }, - { NV_CHIP_IGEFORCE2, "GeForce2 Integrated"}, - { NV_CHIP_QUADRO2MXR, "Quadro2 MXR"}, - { NV_CHIP_GEFORCE2GO, "GeForce2 Go"}, - { NV_CHIP_GEFORCE3, "GeForce3"}, - { NV_CHIP_GEFORCE3_1, "GeForce3 Ti 200"}, - { NV_CHIP_GEFORCE3_2, "GeForce3 Ti 500"}, - { NV_CHIP_QUADRO_DDC, "Quadro DDC"}, - { NV_CHIP_0x0250, "0x0250"}, - { NV_CHIP_0x0258, "0x0258"}, + {NV_CHIP_RIVA_128, "RIVA 128"}, + {NV_CHIP_TNT, "RIVA TNT"}, + {NV_CHIP_TNT2, "RIVA TNT2/TNT2 Pro"}, + {NV_CHIP_UTNT2, "RIVA TNT2 Ultra"}, + {NV_CHIP_VTNT2, "Vanta"}, + {NV_CHIP_UVTNT2, "Riva TNT2 M64"}, + {NV_CHIP_ITNT2, "Aladdin TNT2"}, + {NV_CHIP_GEFORCE_256, "GeForce 256"}, + {NV_CHIP_GEFORCE_DDR, "GeForce DDR"}, + {NV_CHIP_QUADRO, "Quadro"}, + {NV_CHIP_GEFORCE2_MX, "GeForce2 MX/MX 400"}, + {NV_CHIP_GEFORCE2_MX_100, "GeForce2 MX 100/200"}, + {NV_CHIP_GEFORCE2_GO, "GeForce2 Go"}, + {NV_CHIP_QUADRO2_MXR, "Quadro2 MXR"}, + {NV_CHIP_GEFORCE2_GTS, "GeForce2 GTS/Pro"}, + {NV_CHIP_GEFORCE2_TI, "GeForce2 Ti"}, + {NV_CHIP_GEFORCE2_ULTRA, "GeForce2 Ultra"}, + {NV_CHIP_QUADRO2_PRO, "Quadro2 Pro"}, + {NV_CHIP_GEFORCE4_MX_460, "GeForce4 MX 460"}, + {NV_CHIP_GEFORCE4_MX_440, "GeForce4 MX 440"}, + {NV_CHIP_GEFORCE4_MX_420, "GeForce4 MX 420"}, + {NV_CHIP_GEFORCE4_440_GO, "GeForce4 440 Go"}, + {NV_CHIP_GEFORCE4_420_GO, "GeForce4 420 Go"}, + {NV_CHIP_GEFORCE4_420_GO_M32,"GeForce4 420 Go M32"}, + {NV_CHIP_QUADRO4_500XGL, "Quadro4 500XGL"}, + {NV_CHIP_GEFORCE4_440_GO_M64,"GeForce4 440 Go M64"}, + {NV_CHIP_QUADRO4_200, "Quadro4 200/400NVS"}, + {NV_CHIP_QUADRO4_550XGL, "Quadro4 550XGL"}, + {NV_CHIP_QUADRO4_500_GOGL, "Quadro4 GoGL"}, + {NV_CHIP_IGEFORCE2, "GeForce2 Integrated"}, + {NV_CHIP_GEFORCE3, "GeForce3"}, + {NV_CHIP_GEFORCE3_TI_200, "GeForce3 Ti 200"}, + {NV_CHIP_GEFORCE3_TI_500, "GeForce3 Ti 500"}, + {NV_CHIP_QUADRO_DCC, "Quadro DCC"}, + {NV_CHIP_GEFORCE4_TI_4600, "GeForce4 Ti 4600"}, + {NV_CHIP_GEFORCE4_TI_4400, "GeForce4 Ti 4400"}, + {NV_CHIP_GEFORCE4_TI_4200, "GeForce4 Ti 4200"}, + {NV_CHIP_QUADRO4_900XGL, "Quadro4 900 XGL"}, + {NV_CHIP_QUADRO4_750XGL, "Quadro4 750 XGL"}, + {NV_CHIP_QUADRO4_700XGL, "Quadro4 700 XGL"}, {-1, NULL } }; static PciChipsets NVPciChipsets[] = { - { NV_CHIP_RIVA128, NV_CHIP_RIVA128, RES_SHARED_VGA }, - { NV_CHIP_TNT, NV_CHIP_TNT, RES_SHARED_VGA }, - { NV_CHIP_TNT2, NV_CHIP_TNT2, RES_SHARED_VGA }, - { NV_CHIP_UTNT2, NV_CHIP_UTNT2, RES_SHARED_VGA }, - { NV_CHIP_VTNT2, NV_CHIP_VTNT2, RES_SHARED_VGA }, - { NV_CHIP_UVTNT2, NV_CHIP_UVTNT2, RES_SHARED_VGA }, - { NV_CHIP_ITNT2, NV_CHIP_ITNT2, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE256, NV_CHIP_GEFORCE256, RES_SHARED_VGA }, - { NV_CHIP_GEFORCEDDR, NV_CHIP_GEFORCEDDR, RES_SHARED_VGA }, - { NV_CHIP_QUADRO, NV_CHIP_QUADRO, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE2GTS, NV_CHIP_GEFORCE2GTS, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE2GTS_1, NV_CHIP_GEFORCE2GTS_1, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE2ULTRA, NV_CHIP_GEFORCE2ULTRA, RES_SHARED_VGA }, - { NV_CHIP_QUADRO2PRO, NV_CHIP_QUADRO2PRO, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE2MX, NV_CHIP_GEFORCE2MX, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE2MXDDR, NV_CHIP_GEFORCE2MXDDR, RES_SHARED_VGA }, - { NV_CHIP_0x0170, NV_CHIP_0x0170, RES_SHARED_VGA }, - { NV_CHIP_0x0171, NV_CHIP_0x0171, RES_SHARED_VGA }, - { NV_CHIP_0x0172, NV_CHIP_0x0172, RES_SHARED_VGA }, - { NV_CHIP_0x0173, NV_CHIP_0x0173, RES_SHARED_VGA }, - { NV_CHIP_0x0174, NV_CHIP_0x0174, RES_SHARED_VGA }, - { NV_CHIP_0x0175, NV_CHIP_0x0175, RES_SHARED_VGA }, - { NV_CHIP_0x0178, NV_CHIP_0x0178, RES_SHARED_VGA }, - { NV_CHIP_0x017A, NV_CHIP_0x017A, RES_SHARED_VGA }, - { NV_CHIP_0x017B, NV_CHIP_0x017B, RES_SHARED_VGA }, - { NV_CHIP_0x017C, NV_CHIP_0x017C, RES_SHARED_VGA }, - { NV_CHIP_IGEFORCE2, NV_CHIP_IGEFORCE2, RES_SHARED_VGA }, - { NV_CHIP_QUADRO2MXR, NV_CHIP_QUADRO2MXR, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE2GO, NV_CHIP_GEFORCE2GO, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE3, NV_CHIP_GEFORCE3, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE3_1, NV_CHIP_GEFORCE3_1, RES_SHARED_VGA }, - { NV_CHIP_GEFORCE3_2, NV_CHIP_GEFORCE3_2, RES_SHARED_VGA }, - { NV_CHIP_QUADRO_DDC, NV_CHIP_QUADRO_DDC, RES_SHARED_VGA }, - { NV_CHIP_0x0250, NV_CHIP_0x0250, RES_SHARED_VGA }, - { NV_CHIP_0x0258, NV_CHIP_0x0258, RES_SHARED_VGA }, - { -1, -1, RES_UNDEFINED } + {NV_CHIP_RIVA_128, NV_CHIP_RIVA_128, RES_SHARED_VGA}, + {NV_CHIP_TNT, NV_CHIP_TNT, RES_SHARED_VGA}, + {NV_CHIP_TNT2, NV_CHIP_TNT2, RES_SHARED_VGA}, + {NV_CHIP_UTNT2, NV_CHIP_UTNT2, RES_SHARED_VGA}, + {NV_CHIP_VTNT2, NV_CHIP_VTNT2, RES_SHARED_VGA}, + {NV_CHIP_UVTNT2, NV_CHIP_UVTNT2, RES_SHARED_VGA}, + {NV_CHIP_ITNT2, NV_CHIP_ITNT2, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE_256, NV_CHIP_GEFORCE_256, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE_DDR, NV_CHIP_GEFORCE_DDR, RES_SHARED_VGA}, + {NV_CHIP_QUADRO, NV_CHIP_QUADRO, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE2_MX, NV_CHIP_GEFORCE2_MX, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE2_MX_100, NV_CHIP_GEFORCE2_MX_100, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE2_GO, NV_CHIP_GEFORCE2_GO, RES_SHARED_VGA}, + {NV_CHIP_QUADRO2_MXR, NV_CHIP_QUADRO2_MXR, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE2_GTS, NV_CHIP_GEFORCE2_GTS, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE2_TI, NV_CHIP_GEFORCE2_TI, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE2_ULTRA, NV_CHIP_GEFORCE2_ULTRA, RES_SHARED_VGA}, + {NV_CHIP_QUADRO2_PRO, NV_CHIP_QUADRO2_PRO, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_MX_460, NV_CHIP_GEFORCE4_MX_460, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_MX_440, NV_CHIP_GEFORCE4_MX_440, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_MX_420, NV_CHIP_GEFORCE4_MX_420, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_440_GO, NV_CHIP_GEFORCE4_440_GO, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_420_GO, NV_CHIP_GEFORCE4_420_GO, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_420_GO_M32,NV_CHIP_GEFORCE4_420_GO_M32,RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_500XGL, NV_CHIP_QUADRO4_500XGL, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_440_GO_M64,NV_CHIP_GEFORCE4_440_GO_M64,RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_200, NV_CHIP_QUADRO4_200, RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_550XGL, NV_CHIP_QUADRO4_550XGL, RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_500_GOGL, NV_CHIP_QUADRO4_500_GOGL, RES_SHARED_VGA}, + {NV_CHIP_IGEFORCE2, NV_CHIP_IGEFORCE2, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE3, NV_CHIP_GEFORCE3, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE3_TI_200, NV_CHIP_GEFORCE3_TI_200, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE3_TI_500, NV_CHIP_GEFORCE3_TI_500, RES_SHARED_VGA}, + {NV_CHIP_QUADRO_DCC, NV_CHIP_QUADRO_DCC, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_TI_4600, NV_CHIP_GEFORCE4_TI_4600, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_TI_4400, NV_CHIP_GEFORCE4_TI_4400, RES_SHARED_VGA}, + {NV_CHIP_GEFORCE4_TI_4200, NV_CHIP_GEFORCE4_TI_4200, RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_900XGL, NV_CHIP_QUADRO4_900XGL, RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_750XGL, NV_CHIP_QUADRO4_750XGL, RES_SHARED_VGA}, + {NV_CHIP_QUADRO4_700XGL, NV_CHIP_QUADRO4_700XGL, RES_SHARED_VGA}, + { -1, -1, RES_UNDEFINED } }; /* @@ -179,13 +189,11 @@ "vgaHWGetHWRec", "vgaHWGetIndex", "vgaHWInit", - "vgaHWLock", "vgaHWMapMem", "vgaHWProtect", "vgaHWRestore", "vgaHWSave", "vgaHWSaveScreen", - "vgaHWUnlock", "vgaHWddc1SetSpeed", NULL }; @@ -305,7 +313,8 @@ OPTION_FBDEV, OPTION_ROTATE, OPTION_VIDEO_KEY, - OPTION_FLAT_PANEL + OPTION_FLAT_PANEL, + OPTION_CRTC_NUMBER } NVOpts; @@ -319,6 +328,7 @@ { OPTION_ROTATE, "Rotate", OPTV_ANYSTR, {0}, FALSE }, { OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE }, { OPTION_FLAT_PANEL, "FlatPanel", OPTV_BOOLEAN, {0}, FALSE }, + { OPTION_CRTC_NUMBER, "CrtcNumber", OPTV_INTEGER, {0}, FALSE }, { -1, NULL, OPTV_NONE, {0}, FALSE } }; @@ -333,7 +343,7 @@ */ static NVRamdacRec DacInit = { FALSE, 0, 0, 0, 0, NULL, NULL, NULL, NULL, NULL, NULL, - 0, NULL, NULL, NULL, NULL, NULL + 0, NULL, NULL, NULL, NULL }; @@ -565,13 +575,9 @@ NVEnterVT(int scrnIndex, int flags) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; - NVPtr pNv = NVPTR(pScrn); - vgaHWPtr hwp = VGAHWPTR(pScrn); DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVEnterVT\n")); - vgaHWUnlock(hwp); - pNv->riva.LockUnlock(&pNv->riva, 0); if (!NVModeInit(pScrn, pScrn->currentMode)) return FALSE; NVAdjustFrame(scrnIndex, pScrn->frameX0, pScrn->frameY0, 0); @@ -600,13 +606,11 @@ { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; NVPtr pNv = NVPTR(pScrn); - vgaHWPtr hwp = VGAHWPTR(pScrn); DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVLeaveVT\n")); NVRestore(pScrn); pNv->riva.LockUnlock(&pNv->riva, 1); - vgaHWLock(hwp); } @@ -645,7 +649,6 @@ NVCloseScreen(int scrnIndex, ScreenPtr pScreen) { ScrnInfoPtr pScrn = xf86Screens[scrnIndex]; - vgaHWPtr hwp = VGAHWPTR(pScrn); NVPtr pNv = NVPTR(pScrn); DEBUG(xf86DrvMsg(scrnIndex, X_INFO, "NVCloseScreen\n")); @@ -653,7 +656,6 @@ if (pScrn->vtSema) { NVRestore(pScrn); pNv->riva.LockUnlock(&pNv->riva, 1); - vgaHWLock(hwp); } NVUnmapMem(pScrn); @@ -779,15 +781,13 @@ /* Internally used */ -static xf86MonPtr +xf86MonPtr NVdoDDC(ScrnInfoPtr pScrn) { - vgaHWPtr hwp; NVPtr pNv; NVRamdacPtr NVdac; xf86MonPtr MonInfo = NULL; - hwp = VGAHWPTR(pScrn); pNv = NVPTR(pScrn); NVdac = &pNv->Dac; @@ -800,7 +800,6 @@ /* if ((MonInfo = nvDoDDCVBE(pScrn))) return MonInfo; */ /* Enable access to extended registers */ - vgaHWUnlock(hwp); pNv->riva.LockUnlock(&pNv->riva, 0); /* Save the current state */ NVSave(pScrn); @@ -814,7 +813,6 @@ /* Restore previous state */ NVRestore(pScrn); pNv->riva.LockUnlock(&pNv->riva, 1); - vgaHWLock(hwp); return MonInfo; } @@ -972,7 +970,7 @@ /* OK */ break; case 16: - if(pNv->Chipset == NV_CHIP_RIVA128) { + if(pNv->Chipset == NV_CHIP_RIVA_128) { xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "The Riva 128 chipset does not support depth 16. " "Using depth 15 instead\n"); @@ -1141,10 +1139,23 @@ (((pScrn->mask.blue >> pScrn->offset.blue) - 1) << pScrn->offset.blue); } - if (xf86ReturnOptValBool(pNv->Options, OPTION_FLAT_PANEL, FALSE)) { - pNv->FlatPanel = TRUE; - xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "using flat panel\n"); + if (xf86GetOptValBool(pNv->Options, OPTION_FLAT_PANEL, &(pNv->FlatPanel))) { + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "forcing %s usage\n", + pNv->FlatPanel ? "DFP" : "CRTC"); + } else { + pNv->FlatPanel = -1; /* autodetect later */ } + + if (xf86GetOptValInteger(pNv->Options, OPTION_CRTC_NUMBER, + &pNv->forceCRTC)) + { + if((pNv->forceCRTC < 0) || (pNv->forceCRTC > 1)) { + pNv->forceCRTC = -1; + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "Invalid CRTC number. Must be 0 or 1\n"); + } + } else pNv->forceCRTC = -1; + if (pNv->pEnt->device->MemBase != 0) { /* Require that the config file value matches one of the PCI values. */ @@ -1233,12 +1244,6 @@ } /* - * fill riva structure etc. - */ - (*pNv->PreInit)(pScrn); - - - /* * If the user has specified the amount of memory in the XF86Config * file, we respect that setting. */ @@ -1258,42 +1263,6 @@ pNv->FbMapSize = pScrn->videoRam * 1024; -#if !defined(__powerpc__) - /* Read and print the Monitor DDC info */ - pScrn->monitor->DDC = NVdoDDC(pScrn); -#endif - -#if 0 - /* - * This code was for testing. It will be removed as soon - * as this is integrated into the common level. - */ - if ((!pScrn->monitor->nHsync || !pScrn->monitor->nVrefresh) - && pScrn->monitor->DDC) { - int i; - int h = (!pScrn->monitor->nHsync) ? 0 : -1; - int v = (!pScrn->monitor->nVrefresh) ? 0 : -1; - xf86MonPtr pMon = (xf86MonPtr)pScrn->monitor->DDC; - for (i = 0; i < DET_TIMINGS; i++) { - if (pMon->det_mon[i].type == DS_RANGES) { - if (h != -1) { - pScrn->monitor->hsync[h].lo - = pMon->det_mon[i].section.ranges.min_h; - pScrn->monitor->hsync[h++].hi - = pMon->det_mon[i].section.ranges.max_h; - } - if (v != -1) { - pScrn->monitor->vrefresh[v].lo - = pMon->det_mon[i].section.ranges.min_v; - pScrn->monitor->vrefresh[v++].hi - = pMon->det_mon[i].section.ranges.max_v; - } - } - } - if (h != -1) pScrn->monitor->nHsync = h; - if (v != -1) pScrn->monitor->nVrefresh = v; - } -#endif /* * If the driver can do gamma correction, it should call xf86SetGamma() * here. @@ -1318,6 +1287,7 @@ case NV_ARCH_04: case NV_ARCH_10: case NV_ARCH_20: + default: pNv->FbUsableSize -= 128 * 1024; break; } @@ -1344,6 +1314,11 @@ clockRanges->interlaceAllowed = FALSE; clockRanges->doubleScanAllowed = TRUE; + if(pNv->FlatPanel == 1) { + clockRanges->interlaceAllowed = FALSE; + clockRanges->doubleScanAllowed = FALSE; + } + /* * xf86ValidateModes will check that the mode HTotal and VTotal values * don't exceed the chipset's limit if pScrn->maxHValue and @@ -1538,9 +1513,7 @@ /* - * Initialise a new mode. This is currently still using the old - * "initialise struct, restore/write struct to HW" model. That could - * be changed. + * Initialise a new mode. */ static Bool @@ -1558,18 +1531,15 @@ return FALSE; pScrn->vtSema = TRUE; - if ( pNv->ModeInit ) { - if (!(*pNv->ModeInit)(pScrn, mode)) - return FALSE; - } + if(!(*pNv->ModeInit)(pScrn, mode)) + return FALSE; /* Program the registers */ vgaHWProtect(pScrn, TRUE); vgaReg = &hwp->ModeReg; nvReg = &pNv->ModeReg; - if ( pNv->Restore ) - (*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE); + (*pNv->Restore)(pScrn, vgaReg, nvReg, FALSE); #if X_BYTE_ORDER == X_BIG_ENDIAN /* turn on LFB swapping */ @@ -1606,10 +1576,7 @@ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVRestore\n")); /* Only restore text mode fonts/text for the primary card */ vgaHWProtect(pScrn, TRUE); - if (pNv->Primary) - (*pNv->Restore)(pScrn, vgaReg, nvReg, TRUE); - else - vgaHWRestore(pScrn, vgaReg, VGA_SR_MODE); + (*pNv->Restore)(pScrn, vgaReg, nvReg, pNv->Primary); vgaHWProtect(pScrn, FALSE); } @@ -1666,7 +1633,6 @@ return FALSE; } else { /* Save the current state */ - vgaHWUnlock(hwp); pNv->riva.LockUnlock(&pNv->riva, 0); NVSave(pScrn); /* Initialise the first mode */ @@ -1897,12 +1863,6 @@ vgaRegPtr vgaReg = &pVga->SavedReg; DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NVSave\n")); -#if defined(__powerpc__) - /* The console driver will have to save the fonts, we can't */ - vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE); -#else - vgaHWSave(pScrn, vgaReg, VGA_SR_CMAP | VGA_SR_MODE | VGA_SR_FONTS); -#endif - pNv->riva.UnloadStateExt(&pNv->riva, nvReg); + (*pNv->Save)(pScrn, vgaReg, nvReg, pNv->Primary); } diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h Fri Nov 3 19:46:12 2000 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h Fri Jan 25 22:56:06 2002 @@ -36,40 +36,39 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.6 2000/11/03 18:46:12 eich Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_local.h,v 1.7 2002/01/25 21:56:06 tsi Exp $ */ #ifndef __NV_LOCAL_H__ #define __NV_LOCAL_H__ + /* - * This file includes any environment or machine specific values to access the HW. - * Put all affected includes, typdefs, etc. here so the riva_hw.* files can stay - * generic in nature. + * This file includes any environment or machine specific values to access the + * HW. Put all affected includes, typdefs, etc. here so the riva_hw.* files + * can stay generic in nature. */ #include "xf86_ansic.h" #include "compiler.h" +#include "xf86_OSproc.h" + /* * Typedefs to force certain sized values. */ typedef unsigned char U008; typedef unsigned short U016; typedef unsigned int U032; + /* - * HW access macros. + * HW access macros. These assume memory-mapped I/O, and not normal I/O space. */ -#include "xf86_OSproc.h" -/* these assume memory-mapped I/O, and not normal I/O space */ #define NV_WR08(p,i,d) MMIO_OUT8((volatile pointer)(p), (i), (d)) #define NV_RD08(p,i) MMIO_IN8((volatile pointer)(p), (i)) #define NV_WR16(p,i,d) MMIO_OUT16((volatile pointer)(p), (i), (d)) #define NV_RD16(p,i) MMIO_IN16((volatile pointer)(p), (i)) #define NV_WR32(p,i,d) MMIO_OUT32((volatile pointer)(p), (i), (d)) #define NV_RD32(p,i) MMIO_IN32((volatile pointer)(p), (i)) -#if 1 + +/* VGA I/O is now always done through MMIO */ #define VGA_WR08(p,i,d) NV_WR08(p,i,d) #define VGA_RD08(p,i) NV_RD08(p,i) -#else -#define VGA_WR08(p,i,d) outb(i,d) -#define VGA_RD08(p,i) inb(i) -#endif -#endif /* __NV_LOCAL_H__ */ +#endif /* __NV_LOCAL_H__ */ diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h Wed Mar 28 03:17:43 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h Fri Mar 15 06:16:40 2002 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h,v 1.6 2001/03/28 01:17:43 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_proto.h,v 1.7 2002/03/15 05:16:40 mvojkovi Exp $ */ #ifndef __NV_PROTO_H__ #define __NV_PROTO_H__ @@ -6,6 +6,8 @@ /* in nv_driver.c */ Bool NVSwitchMode(int scrnIndex, DisplayModePtr mode, int flags); void NVAdjustFrame(int scrnIndex, int x, int y, int flags); +xf86MonPtr NVdoDDC(ScrnInfoPtr pScrn); + /* in nv_dac.c */ void NVRamdacInit(ScrnInfoPtr pScrn); diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c Tue Oct 30 20:38:29 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c Fri Mar 15 06:16:40 2002 @@ -24,7 +24,7 @@ /* Hacked together from mga driver and 3.3.4 NVIDIA driver by Jarno Paananen */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.11 2001/10/30 19:38:29 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_setup.c,v 1.17 2002/03/15 05:16:40 mvojkovi Exp $ */ #include "nv_include.h" @@ -155,6 +155,92 @@ return (VGA_RD08(pNv->riva.PDIO, VGA_DAC_DATA)); } +static Bool +NVIsConnected (ScrnInfoPtr pScrn, Bool second) +{ + NVPtr pNv = NVPTR(pScrn); + volatile U032 *PRAMDAC = pNv->riva.PRAMDAC0; + CARD32 reg52C, reg608; + Bool present; + + if(second) PRAMDAC += 0x800; + + reg52C = PRAMDAC[0x052C/4]; + reg608 = PRAMDAC[0x0608/4]; + + PRAMDAC[0x0608/4] = reg608 & ~0x00010000; + + PRAMDAC[0x052C/4] = reg52C & 0x0000FEEE; + usleep(1000); + PRAMDAC[0x052C/4] |= 1; + + pNv->riva.PRAMDAC0[0x0610/4] = 0x94050140; + pNv->riva.PRAMDAC0[0x0608/4] |= 0x00001000; + + usleep(1000); + + present = (PRAMDAC[0x0608/4] & (1 << 28)) ? TRUE : FALSE; + + pNv->riva.PRAMDAC0[0x0608/4] &= 0x0000EFFF; + + PRAMDAC[0x052C/4] = reg52C; + PRAMDAC[0x0608/4] = reg608; + + return present; +} + +static void +NVOverrideCRTC(ScrnInfoPtr pScrn) +{ + NVPtr pNv = NVPTR(pScrn); + + xf86DrvMsg(pScrn->scrnIndex, X_INFO, + "Detected CRTC controller %i being used\n", + pNv->SecondCRTC ? 1 : 0); + + if(pNv->forceCRTC != -1) { + xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, + "Forcing usage of CRTC %i\n", pNv->forceCRTC); + pNv->SecondCRTC = pNv->forceCRTC; + } +} + +static void +NVIsSecond (ScrnInfoPtr pScrn) +{ + NVPtr pNv = NVPTR(pScrn); + + if(pNv->FlatPanel == 1) { + switch(pNv->Chipset) { + case NV_CHIP_GEFORCE4_440_GO: + case NV_CHIP_GEFORCE4_440_GO_M64: + case NV_CHIP_GEFORCE4_420_GO: + case NV_CHIP_GEFORCE4_420_GO_M32: + case NV_CHIP_QUADRO4_500_GOGL: + pNv->SecondCRTC = TRUE; + break; + default: + pNv->SecondCRTC = FALSE; + break; + } + } else { + if(NVIsConnected(pScrn, 0)) { + if(pNv->riva.PRAMDAC0[0x0000052C/4] & 0x100) + pNv->SecondCRTC = TRUE; + else + pNv->SecondCRTC = FALSE; + } else + if (NVIsConnected(pScrn, 1)) { + if(pNv->riva.PRAMDAC0[0x0000252C/4] & 0x100) + pNv->SecondCRTC = TRUE; + else + pNv->SecondCRTC = FALSE; + } else /* default */ + pNv->SecondCRTC = FALSE; + } + + NVOverrideCRTC(pScrn); +} static void NVCommonSetup(ScrnInfoPtr pScrn) @@ -168,7 +254,6 @@ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- Regbase %x\n", regBase)); DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- riva %x\n", &pNv->riva)); - pNv->PreInit = NVRamdacInit; pNv->Save = NVDACSave; pNv->Restore = NVDACRestore; pNv->ModeInit = NVDACInit; @@ -216,9 +301,9 @@ mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT; - pNv->riva.PRAMDAC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + pNv->riva.PRAMDAC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00680000, 0x00003000); - DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PRAMDAC %x\n", pNv->riva.PRAMDAC)); + DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PRAMDAC %x\n", pNv->riva.PRAMDAC0)); pNv->riva.PFB = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00100000, 0x00001000); DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "- PFB %x\n", pNv->riva.PFB)); @@ -245,22 +330,88 @@ * These registers are read/write as 8 bit values. Probably have to map * sparse on alpha. */ - pNv->riva.PCIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, + pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00601000, - 0x00001000); - pNv->riva.PDIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, + 0x00003000); + pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00681000, - 0x00001000); + 0x00003000); pNv->riva.PVIO = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x000C0000, 0x00001000); - + + if(pNv->FlatPanel == -1) { + switch(pNv->Chipset) { + case NV_CHIP_GEFORCE4_440_GO: + case NV_CHIP_GEFORCE4_440_GO_M64: + case NV_CHIP_GEFORCE4_420_GO: + case NV_CHIP_GEFORCE4_420_GO_M32: + case NV_CHIP_QUADRO4_500_GOGL: + case NV_CHIP_GEFORCE2_GO: + xf86DrvMsg(pScrn->scrnIndex, X_PROBED, + "On a laptop. Assuming Digital Flat Panel\n"); + pNv->FlatPanel = 1; + break; + default: + break; + } + } + + switch(pNv->Chipset & 0x0ff0) { + case 0x0110: + if(pNv->Chipset == NV_CHIP_GEFORCE2_GO) + pNv->SecondCRTC = TRUE; +#if defined(__powerpc__) + else if(pNv->FlatPanel == 1) + pNv->SecondCRTC = TRUE; +#endif + NVOverrideCRTC(pScrn); + break; + case 0x0170: + case 0x0250: + NVIsSecond(pScrn); + break; + default: + break; + } + + if(pNv->SecondCRTC) { + pNv->riva.PCIO = pNv->riva.PCIO0 + 0x2000; + pNv->riva.PCRTC = pNv->riva.PCRTC0 + 0x800; + pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0 + 0x800; + pNv->riva.PDIO = pNv->riva.PDIO0 + 0x2000; + } else { + pNv->riva.PCIO = pNv->riva.PCIO0; + pNv->riva.PCRTC = pNv->riva.PCRTC0; + pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0; + pNv->riva.PDIO = pNv->riva.PDIO0; + } + RivaGetConfig(pNv); pNv->Dac.maxPixelClock = pNv->riva.MaxVClockFreqKHz; - vgaHWUnlock(VGAHWPTR(pScrn)); pNv->riva.LockUnlock(&pNv->riva, 0); + + NVRamdacInit(pScrn); + +#if !defined(__powerpc__) + /* Read and print the Monitor DDC info */ + pScrn->monitor->DDC = NVdoDDC(pScrn); +#endif + if(pNv->FlatPanel == -1) { + pNv->FlatPanel = 0; + if(pScrn->monitor->DDC) { + xf86MonPtr ddc = (xf86MonPtr)pScrn->monitor->DDC; + + if(ddc->features.input_type) { + pNv->FlatPanel = 1; + xf86DrvMsg(pScrn->scrnIndex, X_PROBED, + "autodetected Digital Flat Panel\n"); + } + } + } + pNv->riva.flatPanel = (pNv->FlatPanel > 0) ? TRUE : FALSE; } void @@ -289,6 +440,7 @@ frameBase+0x00C00000, 0x00008000); NVCommonSetup(pScrn); + pNv->riva.PCRTC = pNv->riva.PCRTC0 = pNv->riva.PGRAPH; } void @@ -307,11 +459,12 @@ mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT; pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00710000, 0x00010000); - pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00600000, 0x00001000); NVCommonSetup(pScrn); } + void NV10Setup(ScrnInfoPtr pScrn) { @@ -322,14 +475,11 @@ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV10Setup\n")); pNv->riva.Architecture = 0x10; - /* - * Map chip-specific memory-mapped registers. This MUST be done in the OS specific driver code. - */ mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT; pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00710000, 0x00010000); - pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, - regBase+0x00600000, 0x00001000); + pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00600000, 0x00003000); NVCommonSetup(pScrn); } @@ -341,18 +491,14 @@ CARD32 regBase = pNv->IOAddress; int mmioFlags; - DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV10Setup\n")); + DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO, "NV20Setup\n")); pNv->riva.Architecture = 0x20; - /* - * Map chip-specific memory-mapped registers. This MUST be done in the OS sp -ecific driver code. - */ mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT; pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00710000, 0x00010000); - pNv->riva.PCRTC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, - regBase+0x00600000, 0x00001000); + pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00600000, 0x00003000); NVCommonSetup(pScrn); } diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h Fri Dec 7 01:09:56 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h Mon Mar 18 22:47:48 2002 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.29 2001/12/07 00:09:56 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_type.h,v 1.34 2002/03/18 21:47:48 mvojkovi Exp $ */ #ifndef __NV_STRUCT_H__ #define __NV_STRUCT_H__ @@ -32,7 +32,6 @@ void (*SetCursorColors)(ScrnInfoPtr, int, int); long maxPixelClock; void (*LoadPalette)(ScrnInfoPtr, int, int*, LOCO*, VisualPtr); - void (*PreInit)(ScrnInfoPtr); void (*Save)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool); void (*Restore)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool); Bool (*ModeInit)(ScrnInfoPtr, DisplayModePtr); @@ -80,7 +79,6 @@ int numDGAModes; Bool DGAactive; int DGAViewportStatus; - void (*PreInit)(ScrnInfoPtr pScrn); void (*Save)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool); void (*Restore)(ScrnInfoPtr, vgaRegPtr, NVRegPtr, Bool); Bool (*ModeInit)(ScrnInfoPtr, DisplayModePtr); @@ -113,7 +111,9 @@ void (*VideoTimerCallback)(ScrnInfoPtr, Time); XF86VideoAdaptorPtr overlayAdaptor; int videoKey; - Bool FlatPanel; + int FlatPanel; + Bool SecondCRTC; + int forceCRTC; OptionInfoPtr Options; } NVRec, *NVPtr; @@ -127,40 +127,46 @@ int RivaGetConfig(NVPtr); -#define NV_CHIP_RIVA128 ((PCI_VENDOR_NVIDIA_SGS << 16)| PCI_CHIP_RIVA128) -#define NV_CHIP_TNT ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT) -#define NV_CHIP_TNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT2) -#define NV_CHIP_UTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UTNT2) -#define NV_CHIP_VTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_VTNT2) -#define NV_CHIP_UVTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UVTNT2) -#define NV_CHIP_ITNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_ITNT2) -#define NV_CHIP_GEFORCE256 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCE256) -#define NV_CHIP_GEFORCEDDR ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCEDDR) -#define NV_CHIP_QUADRO ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_QUADRO) -#define NV_CHIP_GEFORCE2MX ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2MX) -#define NV_CHIP_GEFORCE2MXDDR ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2MXDDR) -#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_IGEFORCE2) -#define NV_CHIP_0x0170 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0170) -#define NV_CHIP_0x0171 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0171) -#define NV_CHIP_0x0172 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0172) -#define NV_CHIP_0x0173 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0173) -#define NV_CHIP_0x0174 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0174) -#define NV_CHIP_0x0175 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0175) -#define NV_CHIP_0x0178 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0178) -#define NV_CHIP_0x017A ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x017A) -#define NV_CHIP_0x017B ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x017B) -#define NV_CHIP_0x017C ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x017C) -#define NV_CHIP_QUADRO2MXR ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2MXR) -#define NV_CHIP_GEFORCE2GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2GO) -#define NV_CHIP_GEFORCE2GTS ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2GTS) -#define NV_CHIP_GEFORCE2GTS_1 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2GTS_1) -#define NV_CHIP_GEFORCE2ULTRA ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2ULTRA) -#define NV_CHIP_QUADRO2PRO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2PRO) -#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3) -#define NV_CHIP_GEFORCE3_1 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_1) -#define NV_CHIP_GEFORCE3_2 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_2) -#define NV_CHIP_QUADRO_DDC ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO_DDC) -#define NV_CHIP_0x0250 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0250) -#define NV_CHIP_0x0258 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_0x0258) +#define NV_CHIP_RIVA_128 ((PCI_VENDOR_NVIDIA_SGS << 16)| PCI_CHIP_RIVA128) +#define NV_CHIP_TNT ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT) +#define NV_CHIP_TNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_TNT2) +#define NV_CHIP_UTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UTNT2) +#define NV_CHIP_VTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_VTNT2) +#define NV_CHIP_UVTNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_UVTNT2) +#define NV_CHIP_ITNT2 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_ITNT2) +#define NV_CHIP_GEFORCE_256 ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCE_256) +#define NV_CHIP_GEFORCE_DDR ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_GEFORCE_DDR) +#define NV_CHIP_QUADRO ((PCI_VENDOR_NVIDIA << 16)| PCI_CHIP_QUADRO) +#define NV_CHIP_GEFORCE2_MX ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_MX) +#define NV_CHIP_GEFORCE2_MX_100 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_MX_100) +#define NV_CHIP_QUADRO2_MXR ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2_MXR) +#define NV_CHIP_GEFORCE2_GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_GO) +#define NV_CHIP_GEFORCE2_GTS ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_GTS) +#define NV_CHIP_GEFORCE2_TI ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_TI) +#define NV_CHIP_GEFORCE2_ULTRA ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE2_ULTRA) +#define NV_CHIP_QUADRO2_PRO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO2_PRO) +#define NV_CHIP_GEFORCE4_MX_460 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_MX_460) +#define NV_CHIP_GEFORCE4_MX_440 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_MX_440) +#define NV_CHIP_GEFORCE4_MX_420 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_MX_420) +#define NV_CHIP_GEFORCE4_440_GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_440_GO) +#define NV_CHIP_GEFORCE4_420_GO ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_420_GO) +#define NV_CHIP_GEFORCE4_420_GO_M32 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_420_GO_M32) +#define NV_CHIP_QUADRO4_500XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_500XGL) +#define NV_CHIP_GEFORCE4_440_GO_M64 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_440_GO_M64) +#define NV_CHIP_QUADRO4_200 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_200) +#define NV_CHIP_QUADRO4_550XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_550XGL) +#define NV_CHIP_QUADRO4_500_GOGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_500_GOGL) +#define NV_CHIP_IGEFORCE2 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_IGEFORCE2) +#define NV_CHIP_GEFORCE3 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3) +#define NV_CHIP_GEFORCE3_TI_200 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_TI_200) +#define NV_CHIP_GEFORCE3_TI_500 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE3_TI_500) +#define NV_CHIP_QUADRO_DCC ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO_DCC) +#define NV_CHIP_GEFORCE4_TI_4600 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_TI_4600) +#define NV_CHIP_GEFORCE4_TI_4400 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_TI_4400) +#define NV_CHIP_GEFORCE4_TI_4200 ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_GEFORCE4_TI_4200) +#define NV_CHIP_QUADRO4_900XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_900XGL) +#define NV_CHIP_QUADRO4_750XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_750XGL) +#define NV_CHIP_QUADRO4_700XGL ((PCI_VENDOR_NVIDIA << 16) | PCI_CHIP_QUADRO4_700XGL) + #endif /* __NV_STRUCT_H__ */ diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nv_video.c xc/programs/Xserver/hw/xfree86/drivers/nv/nv_video.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/nv_video.c Fri Dec 14 02:20:44 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nv_video.c Fri Apr 26 21:57:14 2002 @@ -1,4 +1,4 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_video.c,v 1.6 2001/12/14 01:20:44 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nv_video.c,v 1.8 2002/04/26 19:57:14 mvojkovi Exp $ */ #include "xf86.h" #include "xf86_OSproc.h" @@ -103,7 +103,7 @@ { 0, "XV_IMAGE", - 2046, 2047, + 2046, 2046, {1, 1} }; @@ -863,8 +863,8 @@ if(*w > 2046) *w = 2046; - if(*h > 2047) - *h = 2047; + if(*h > 2046) + *h = 2046; *w = (*w + 1) & ~1; if (offsets) @@ -960,7 +960,7 @@ if(pPriv->grabbedByV4L) return BadAlloc; - if((w > 2046) || (h > 2047)) return BadValue; + if((w > 2046) || (h > 2046)) return BadValue; w = (w + 1) & ~1; pPriv->pitch = ((w << 1) + 63) & ~63; @@ -980,6 +980,7 @@ surface->pitches = &pPriv->pitch; surface->offsets = &pPriv->offset; surface->devPrivate.ptr = (pointer)pPriv; + surface->id = id; /* grab the video */ NVStopOverlay(pScrnInfo); @@ -1109,7 +1110,7 @@ NVStopSurface, NVGetSurfaceAttribute, NVSetSurfaceAttribute, - 2046, 2047, + 2046, 2046, NUM_ATTRIBUTES - 1, &NVAttributes[1] }, @@ -1122,7 +1123,7 @@ NVStopSurface, NVGetSurfaceAttribute, NVSetSurfaceAttribute, - 2046, 2047, + 2046, 2046, NUM_ATTRIBUTES - 1, &NVAttributes[1] }, diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h --- xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h Fri Nov 12 03:12:41 1999 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h Fri Jan 25 22:56:06 2002 @@ -21,7 +21,7 @@ * SOFTWARE. */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.5 1999/11/12 02:12:41 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/nvreg.h,v 1.6 2002/01/25 21:56:06 tsi Exp $ */ #ifndef __NVREG_H_ #define __NVREG_H_ @@ -164,19 +164,10 @@ (PDAC_Write(INDEX_HI,((NV_PDAC_EXT_##reg) >> 8) & 0xff)),\ (PDAC_Write(INDEX_DATA,(value)))) -#define CRTC_Write(index,value) outb(0x3d4,(index));outb(0x3d5,value) -#define CRTC_Read(index) (outb(0x3d4,index),inb(0x3d5)) - -#define PCRTC_Write(index,value) CRTC_Write(NV_PCRTC_##index,value) -#define PCRTC_Read(index) CRTC_Read(NV_PCRTC_##index) - #define PCRTC_Def(mask,value) DEVICE_DEF(PCRTC,mask,value) #define PCRTC_Val(mask,value) DEVICE_VALUE(PCRTC,mask,value) #define PCRTC_Mask(mask) DEVICE_MASK(PCRTC,mask) -#define SR_Write(index,value) outb(0x3c4,(index));outb(0x3c5,value) -#define SR_Read(index) (outb(0x3c4,index),inb(0x3c5)) - /* These are the variables which actually point at the register blocks */ extern volatile unsigned *nvPDACPort; /* Points to the DAC */ diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c --- xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c Mon Dec 17 23:17:55 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c Tue Apr 30 22:04:44 2002 @@ -36,7 +36,7 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.21 2001/12/17 22:17:55 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.c,v 1.32 2002/04/30 20:04:44 mvojkovi Exp $ */ #include "nv_local.h" #include "compiler.h" @@ -70,34 +70,40 @@ { return ((chip->Rop->FifoFree < chip->FifoEmptyCount) || (chip->PGRAPH[0x00000700/4] & 0x01)); } -static void nv3LockUnlock +static void vgaLockUnlock ( RIVA_HW_INST *chip, - int LockUnlock + Bool Lock ) { - VGA_WR08(chip->PVIO, 0x3C4, 0x06); - VGA_WR08(chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); + CARD8 cr11; + VGA_WR08(chip->PCIO, 0x3D4, 0x11); + cr11 = VGA_RD08(chip->PCIO, 0x3D5); + if(Lock) cr11 |= 0x80; + else cr11 &= ~0x80; + VGA_WR08(chip->PCIO, 0x3D5, cr11); } -static void nv4LockUnlock + +static void nv3LockUnlock ( RIVA_HW_INST *chip, - int LockUnlock + Bool Lock ) { - VGA_WR08(chip->PCIO, 0x3D4, 0x1F); - VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); + VGA_WR08(chip->PVIO, 0x3C4, 0x06); + VGA_WR08(chip->PVIO, 0x3C5, Lock ? 0x99 : 0x57); + vgaLockUnlock(chip, Lock); } -static void nv10LockUnlock +static void nv4LockUnlock ( RIVA_HW_INST *chip, - int LockUnlock + Bool Lock ) { VGA_WR08(chip->PCIO, 0x3D4, 0x1F); - VGA_WR08(chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); + VGA_WR08(chip->PCIO, 0x3D5, Lock ? 0x99 : 0x57); + vgaLockUnlock(chip, Lock); } - static int ShowHideCursor ( RIVA_HW_INST *chip, @@ -601,7 +607,7 @@ nv3_sim_state sim_data; unsigned int M, N, P, pll, MClk; - pll = chip->PRAMDAC[0x00000504/4]; + pll = chip->PRAMDAC0[0x00000504/4]; M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; MClk = (N * chip->CrystalFreqKHz / M) >> P; sim_data.pix_bpp = (char)pixelDepth; @@ -788,10 +794,10 @@ nv4_sim_state sim_data; unsigned int M, N, P, pll, MClk, NVClk, cfg1; - pll = chip->PRAMDAC[0x00000504/4]; + pll = chip->PRAMDAC0[0x00000504/4]; M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = chip->PRAMDAC[0x00000500/4]; + pll = chip->PRAMDAC0[0x00000500/4]; M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; NVClk = (N * chip->CrystalFreqKHz / M) >> P; cfg1 = chip->PFB[0x00000204/4]; @@ -1049,10 +1055,10 @@ nv10_sim_state sim_data; unsigned int M, N, P, pll, MClk, NVClk, cfg1; - pll = chip->PRAMDAC[0x00000504/4]; + pll = chip->PRAMDAC0[0x00000504/4]; M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; MClk = (N * chip->CrystalFreqKHz / M) >> P; - pll = chip->PRAMDAC[0x00000500/4]; + pll = chip->PRAMDAC0[0x00000500/4]; M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; NVClk = (N * chip->CrystalFreqKHz / M) >> P; cfg1 = chip->PFB[0x00000204/4]; @@ -1078,6 +1084,66 @@ } } +static void nForceUpdateArbitrationSettings +( + unsigned VClk, + unsigned pixelDepth, + unsigned *burst, + unsigned *lwm, + RIVA_HW_INST *chip +) +{ + nv10_fifo_info fifo_data; + nv10_sim_state sim_data; + unsigned int M, N, P, pll, MClk, NVClk; + unsigned int uMClkPostDiv, memctrl; + + uMClkPostDiv = (pciReadLong(pciTag(0, 0, 3), 0x6C) >> 8) & 0xf; + if(!uMClkPostDiv) uMClkPostDiv = 4; + MClk = 400000 / uMClkPostDiv; + + pll = chip->PRAMDAC0[0x00000500/4]; + M = (pll >> 0) & 0xFF; N = (pll >> 8) & 0xFF; P = (pll >> 16) & 0x0F; + NVClk = (N * chip->CrystalFreqKHz / M) >> P; + sim_data.pix_bpp = (char)pixelDepth; + sim_data.enable_video = 0; + sim_data.enable_mp = 0; + sim_data.memory_type = (pciReadLong(pciTag(0, 0, 1), 0x7C) >> 12) & 1; + sim_data.memory_width = 64; + + memctrl = pciReadLong(pciTag(0, 0, 3), 0x00) >> 16; + + if((memctrl == 0x1A9) || (memctrl == 0x1AB)) { + int dimm[3]; + + dimm[0] = (pciReadLong(pciTag(0, 0, 2), 0x40) >> 8) & 0x4F; + dimm[1] = (pciReadLong(pciTag(0, 0, 2), 0x44) >> 8) & 0x4F; + dimm[2] = (pciReadLong(pciTag(0, 0, 2), 0x48) >> 8) & 0x4F; + + if((dimm[0] + dimm[1]) != dimm[2]) { + ErrorF("WARNING: " + "your nForce DIMMs are not arranged in optimal banks!\n"); + } + } + + sim_data.mem_latency = 3; + sim_data.mem_aligned = 1; + sim_data.mem_page_miss = 10; + sim_data.gr_during_vid = 0; + sim_data.pclk_khz = VClk; + sim_data.mclk_khz = MClk; + sim_data.nvclk_khz = NVClk; + nv10CalcArbitration(&fifo_data, &sim_data); + if (fifo_data.valid) + { + int b = fifo_data.graphics_burst_size >> 4; + *burst = 0; + while (b >>= 1) (*burst)++; + *lwm = fifo_data.graphics_lwm >> 3; + } +} + + /****************************************************************************\ * * * RIVA Mode State Routines * @@ -1106,16 +1172,16 @@ VClk = (unsigned)clockIn; - if (chip->CrystalFreqKHz == 14318) - { - lowM = 8; - highM = 14 - (chip->Architecture == NV_ARCH_03); - } - else + if (chip->CrystalFreqKHz == 13500) { lowM = 7; highM = 13 - (chip->Architecture == NV_ARCH_03); } + else + { + lowM = 8; + highM = 14 - (chip->Architecture == NV_ARCH_03); + } highP = 4 - (chip->Architecture == NV_ARCH_03); for (P = 0; P <= highP; P ++) @@ -1125,19 +1191,21 @@ { for (M = lowM; M <= highM; M++) { - N = (VClk * M / chip->CrystalFreqKHz) << P; - Freq = (chip->CrystalFreqKHz * N / M) >> P; - if (Freq > VClk) - DeltaNew = Freq - VClk; - else - DeltaNew = VClk - Freq; - if (DeltaNew < DeltaOld) - { - *mOut = M; - *nOut = N; - *pOut = P; - *clockOut = Freq; - DeltaOld = DeltaNew; + N = (VClk << P) * M / chip->CrystalFreqKHz; + if(N <= 255) { + Freq = (chip->CrystalFreqKHz * N / M) >> P; + if (Freq > VClk) + DeltaNew = Freq - VClk; + else + DeltaNew = VClk - Freq; + if (DeltaNew < DeltaOld) + { + *mOut = M; + *nOut = N; + *pOut = P; + *clockOut = Freq; + DeltaOld = DeltaNew; + } } } } @@ -1211,11 +1279,19 @@ break; case NV_ARCH_10: case NV_ARCH_20: - nv10UpdateArbitrationSettings(VClk, + if(chip->Chipset == NV_CHIP_IGEFORCE2) { + nForceUpdateArbitrationSettings(VClk, + pixelDepth * 8, + &(state->arbitration0), + &(state->arbitration1), + chip); + } else { + nv10UpdateArbitrationSettings(VClk, pixelDepth * 8, &(state->arbitration0), &(state->arbitration1), chip); + } state->cursor0 = 0x80 | (chip->CursorStart >> 17); state->cursor1 = (chip->CursorStart >> 11) << 2; state->cursor2 = chip->CursorStart >> 24; @@ -1272,18 +1348,10 @@ { case NV_ARCH_04: LOAD_FIXED_STATE(nv4,FIFO); - chip->Tri03 = 0L; - chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]); break; case NV_ARCH_10: case NV_ARCH_20: - /* - * Initialize state for the RivaTriangle3D05 routines. - */ - LOAD_FIXED_STATE(nv10tri05,PGRAPH); LOAD_FIXED_STATE(nv10,FIFO); - chip->Tri03 = 0L; - chip->Tri05 = (RivaTexturedTriangle05 *)&(chip->FIFO[0x0000E000/4]); break; } } @@ -1316,19 +1384,16 @@ case 16: LOAD_FIXED_STATE_15BPP(nv3,PRAMIN); LOAD_FIXED_STATE_15BPP(nv3,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); break; case 24: case 32: LOAD_FIXED_STATE_32BPP(nv3,PRAMIN); LOAD_FIXED_STATE_32BPP(nv3,PGRAPH); - chip->Tri03 = 0L; break; case 8: default: LOAD_FIXED_STATE_8BPP(nv3,PRAMIN); LOAD_FIXED_STATE_8BPP(nv3,PGRAPH); - chip->Tri03 = 0L; break; } for (i = 0x00000; i < 0x00800; i++) @@ -1355,24 +1420,20 @@ case 15: LOAD_FIXED_STATE_15BPP(nv4,PRAMIN); LOAD_FIXED_STATE_15BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); break; case 16: LOAD_FIXED_STATE_16BPP(nv4,PRAMIN); LOAD_FIXED_STATE_16BPP(nv4,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); break; case 24: case 32: LOAD_FIXED_STATE_32BPP(nv4,PRAMIN); LOAD_FIXED_STATE_32BPP(nv4,PGRAPH); - chip->Tri03 = 0L; break; case 8: default: LOAD_FIXED_STATE_8BPP(nv4,PRAMIN); LOAD_FIXED_STATE_8BPP(nv4,PGRAPH); - chip->Tri03 = 0L; break; } chip->PGRAPH[0x00000640/4] = state->offset0; @@ -1386,6 +1447,12 @@ break; case NV_ARCH_10: case NV_ARCH_20: + if(chip->twoHeads) { + VGA_WR08(chip->PCIO, 0x03D4, 0x44); + VGA_WR08(chip->PCIO, 0x03D5, state->crtcOwner); + chip->LockUnlock(chip, 0); + } + LOAD_FIXED_STATE(nv10,PFIFO); LOAD_FIXED_STATE(nv10,PRAMIN); LOAD_FIXED_STATE(nv10,PGRAPH); @@ -1394,24 +1461,20 @@ case 15: LOAD_FIXED_STATE_15BPP(nv10,PRAMIN); LOAD_FIXED_STATE_15BPP(nv10,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); break; case 16: LOAD_FIXED_STATE_16BPP(nv10,PRAMIN); LOAD_FIXED_STATE_16BPP(nv10,PGRAPH); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); break; case 24: case 32: LOAD_FIXED_STATE_32BPP(nv10,PRAMIN); LOAD_FIXED_STATE_32BPP(nv10,PGRAPH); - chip->Tri03 = 0L; break; case 8: default: LOAD_FIXED_STATE_8BPP(nv10,PRAMIN); LOAD_FIXED_STATE_8BPP(nv10,PGRAPH); - chip->Tri03 = 0L; break; } @@ -1438,11 +1501,12 @@ chip->PGRAPH[0x00000864/4] = state->pitch3; chip->PGRAPH[0x000009A4/4] = chip->PFB[0x00000200/4]; chip->PGRAPH[0x000009A8/4] = chip->PFB[0x00000204/4]; - chip->PRAMDAC[0x0000052C/4] = 0x00000101; - chip->PRAMDAC[0x0000252C/4] = 0x00000001; } + if(chip->twoHeads) { + chip->PCRTC0[0x00000860/4] = state->head; + chip->PCRTC0[0x00002860/4] = state->head2; + } chip->PRAMDAC[0x00000404/4] |= (1 << 25); - chip->PRAMDAC[0x00002404/4] |= (1 << 25); chip->PMC[0x00008704/4] = 1; chip->PMC[0x00008140/4] = 0; @@ -1450,6 +1514,7 @@ chip->PMC[0x00008924/4] = 0; chip->PMC[0x00008908/4] = 0x01ffffff; chip->PMC[0x0000890C/4] = 0x01ffffff; + chip->PMC[0x00001588/4] = 0; chip->PFB[0x00000240/4] = 0; chip->PFB[0x00000244/4] = 0; @@ -1533,14 +1598,27 @@ chip->PGRAPH[0x00000F50/4] = 0x00000040; for (i = 0; i < 4; i++) chip->PGRAPH[0x00000F54/4] = 0x00000000; + + if(chip->flatPanel) { + VGA_WR08(chip->PCIO, 0x03D4, 0x53); + VGA_WR08(chip->PCIO, 0x03D5, 0); + VGA_WR08(chip->PCIO, 0x03D4, 0x54); + VGA_WR08(chip->PCIO, 0x03D5, 0); + VGA_WR08(chip->PCIO, 0x03D4, 0x21); + VGA_WR08(chip->PCIO, 0x03D5, 0xfa); + } break; + + VGA_WR08(chip->PCIO, 0x03D4, 0x41); + VGA_WR08(chip->PCIO, 0x03D5, state->extra); } + LOAD_FIXED_STATE(Riva,FIFO); UpdateFifoState(chip); + /* * Load HW mode state. */ - VGA_WR08(chip->PCIO, 0x03D4, 0x19); VGA_WR08(chip->PCIO, 0x03D5, state->repaint0); VGA_WR08(chip->PCIO, 0x03D4, 0x1A); @@ -1563,16 +1641,22 @@ VGA_WR08(chip->PCIO, 0x03D5, state->cursor2); VGA_WR08(chip->PCIO, 0x03D4, 0x39); VGA_WR08(chip->PCIO, 0x03D5, state->interlace); - VGA_WR08(chip->PCIO, 0x03D4, 0x41); - VGA_WR08(chip->PCIO, 0x03D5, state->extra); - chip->PRAMDAC[0x00000508/4] = state->vpll; - chip->PRAMDAC[0x0000050C/4] = state->pllsel; + + if(!chip->flatPanel) { + chip->PRAMDAC0[0x00000508/4] = state->vpll; + chip->PRAMDAC0[0x0000050C/4] = state->pllsel; + if(chip->twoHeads) + chip->PRAMDAC0[0x00000520/4] = state->vpll2; + } else { + chip->PRAMDAC[0x00000848/4] = state->scale; + } chip->PRAMDAC[0x00000600/4] = state->general; + /* * Turn off VBlank enable and reset. */ - *(chip->VBLANKENABLE) = 0; - *(chip->VBLANK) = chip->VBlankBit; + chip->PCRTC[0x00000140/4] = 0; + chip->PCRTC[0x00000100/4] = chip->VBlankBit; /* * Set interrupt enable. */ @@ -1588,6 +1672,7 @@ /* Free count from first subchannel */ chip->FifoEmptyCount = chip->Rop->FifoFree; } + static void UnloadStateExt ( RIVA_HW_INST *chip, @@ -1619,12 +1704,13 @@ state->cursor2 = VGA_RD08(chip->PCIO, 0x03D5); VGA_WR08(chip->PCIO, 0x03D4, 0x39); state->interlace = VGA_RD08(chip->PCIO, 0x03D5); - VGA_WR08(chip->PCIO, 0x03D4, 0x41); - state->extra = VGA_RD08(chip->PCIO, 0x03D5); - state->vpll = chip->PRAMDAC[0x00000508/4]; - state->pllsel = chip->PRAMDAC[0x0000050C/4]; + state->vpll = chip->PRAMDAC0[0x00000508/4]; + state->vpll2 = chip->PRAMDAC0[0x00000520/4]; + state->pllsel = chip->PRAMDAC0[0x0000050C/4]; state->general = chip->PRAMDAC[0x00000600/4]; + state->scale = chip->PRAMDAC[0x00000848/4]; state->config = chip->PFB[0x00000200/4]; + switch (chip->Architecture) { case NV_ARCH_03: @@ -1657,6 +1743,14 @@ state->pitch1 = chip->PGRAPH[0x00000674/4]; state->pitch2 = chip->PGRAPH[0x00000678/4]; state->pitch3 = chip->PGRAPH[0x0000067C/4]; + if(chip->twoHeads) { + state->head = chip->PCRTC0[0x00000860/4]; + state->head2 = chip->PCRTC0[0x00002860/4]; + VGA_WR08(chip->PCIO, 0x03D4, 0x44); + state->crtcOwner = VGA_RD08(chip->PCIO, 0x03D5); + } + VGA_WR08(chip->PCIO, 0x03D4, 0x41); + state->extra = VGA_RD08(chip->PCIO, 0x03D5); break; } } @@ -1666,6 +1760,15 @@ unsigned start ) { + chip->PCRTC[0x800/4] = start; +} + +static void SetStartAddress3 +( + RIVA_HW_INST *chip, + unsigned start +) +{ int offset = start >> 2; int pan = (start & 3) << 1; unsigned char tmp; @@ -1692,99 +1795,6 @@ VGA_WR08(chip->PCIO, 0x3C0, 0x13); VGA_WR08(chip->PCIO, 0x3C0, pan); } -static void nv3SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,5); - chip->FIFO[0x00003800] = 0x80000003; - Surface->Offset = surf0; - chip->FIFO[0x00003800] = 0x80000004; - Surface->Offset = surf1; - chip->FIFO[0x00003800] = 0x80000013; -} -static void nv4SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); - - chip->FIFO[0x00003800] = 0x80000003; - Surface->Offset = surf0; - chip->FIFO[0x00003800] = 0x80000004; - Surface->Offset = surf1; - chip->FIFO[0x00003800] = 0x80000014; -} -static void nv10SetSurfaces2D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); - - chip->FIFO[0x00003800] = 0x80000003; - Surface->Offset = surf0; - chip->FIFO[0x00003800] = 0x80000004; - Surface->Offset = surf1; - chip->FIFO[0x00003800] = 0x80000014; -} -static void nv3SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,5); - chip->FIFO[0x00003800] = 0x80000005; - Surface->Offset = surf0; - chip->FIFO[0x00003800] = 0x80000006; - Surface->Offset = surf1; - chip->FIFO[0x00003800] = 0x80000013; -} -static void nv4SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface *Surface = (RivaSurface *)&(chip->FIFO[0x0000E000/4]); - - chip->FIFO[0x00003800] = 0x80000005; - Surface->Offset = surf0; - chip->FIFO[0x00003800] = 0x80000006; - Surface->Offset = surf1; - chip->FIFO[0x00003800] = 0x80000014; -} -static void nv10SetSurfaces3D -( - RIVA_HW_INST *chip, - unsigned surf0, - unsigned surf1 -) -{ - RivaSurface3D *Surfaces3D = (RivaSurface3D *)&(chip->FIFO[0x0000E000/4]); - - RIVA_FIFO_FREE(*chip,Tri03,4); - chip->FIFO[0x00003800] = 0x80000007; - Surfaces3D->RenderBufferOffset = surf0; - Surfaces3D->ZBufferOffset = surf1; - chip->FIFO[0x00003800] = 0x80000014; -} - /****************************************************************************\ * * * Probe RIVA Chip Configuration * @@ -1848,9 +1858,6 @@ } chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500; chip->CURSOR = &(chip->PRAMIN[0x00008000/4 - 0x0800/4]); - chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); - chip->VBLANKENABLE = &(chip->PGRAPH[0x0140/4]); - chip->VBLANK = &(chip->PGRAPH[0x0100/4]); chip->VBlankBit = 0x00000100; chip->MaxVClockFreqKHz = 256000; /* @@ -1861,9 +1868,7 @@ chip->CalcStateExt = CalcStateExt; chip->LoadStateExt = LoadStateExt; chip->UnloadStateExt = UnloadStateExt; - chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv3SetSurfaces2D; - chip->SetSurfaces3D = nv3SetSurfaces3D; + chip->SetStartAddress = SetStartAddress3; chip->LockUnlock = nv3LockUnlock; } static void nv4GetConfig @@ -1909,9 +1914,6 @@ } chip->CrystalFreqKHz = (chip->PEXTDEV[0x00000000/4] & 0x00000040) ? 14318 : 13500; chip->CURSOR = &(chip->PRAMIN[0x00010000/4 - 0x0800/4]); - chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); - chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); - chip->VBLANK = &(chip->PCRTC[0x0100/4]); chip->VBlankBit = 0x00000001; chip->MaxVClockFreqKHz = 350000; /* @@ -1923,8 +1925,6 @@ chip->LoadStateExt = LoadStateExt; chip->UnloadStateExt = UnloadStateExt; chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv4SetSurfaces2D; - chip->SetSurfaces3D = nv4SetSurfaces3D; chip->LockUnlock = nv4LockUnlock; } static void nv10GetConfig @@ -1984,14 +1984,21 @@ chip->RamBandwidthKBytesPerSec = 1000000; break; } - chip->CrystalFreqKHz = (chip->PEXTDEV[0x0000/4] & (1 << 6)) ? 14318 : - (chip->PEXTDEV[0x0000/4] & (1 << 22)) ? 27000 : - 13500; + + chip->CrystalFreqKHz = (chip->PEXTDEV[0x0000/4] & (1 << 6)) ? 14318 : + 13500; + switch(pNv->Chipset & 0x0ff0) { + case 0x0170: + case 0x0250: + if(chip->PEXTDEV[0x0000/4] & (1 << 22)) + chip->CrystalFreqKHz = 27000; + break; + default: + break; + } + chip->CursorStart = (chip->RamAmountKBytes - 128) * 1024; chip->CURSOR = NULL; /* can't set this here */ - chip->CURSORPOS = &(chip->PRAMDAC[0x0300/4]); - chip->VBLANKENABLE = &(chip->PCRTC[0x0140/4]); - chip->VBLANK = &(chip->PCRTC[0x0100/4]); chip->VBlankBit = 0x00000001; chip->MaxVClockFreqKHz = 350000; /* @@ -2003,9 +2010,18 @@ chip->LoadStateExt = LoadStateExt; chip->UnloadStateExt = UnloadStateExt; chip->SetStartAddress = SetStartAddress; - chip->SetSurfaces2D = nv10SetSurfaces2D; - chip->SetSurfaces3D = nv10SetSurfaces3D; - chip->LockUnlock = nv10LockUnlock; + chip->LockUnlock = nv4LockUnlock; + + switch(pNv->Chipset & 0x0ff0) { + case 0x0110: + case 0x0170: + case 0x0250: + chip->twoHeads = TRUE; + break; + default: + chip->twoHeads = FALSE; + break; + } } int RivaGetConfig ( @@ -2035,6 +2051,7 @@ default: return (-1); } + chip->Chipset = pNv->Chipset; /* * Fill in FIFO pointers. */ @@ -2045,7 +2062,6 @@ chip->Blt = (RivaScreenBlt *)&(chip->FIFO[0x00008000/4]); chip->Bitmap = (RivaBitmap *)&(chip->FIFO[0x0000A000/4]); chip->Line = (RivaLine *)&(chip->FIFO[0x0000C000/4]); - chip->Tri03 = (RivaTexturedTriangle03 *)&(chip->FIFO[0x0000E000/4]); return (0); } diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h --- xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h Tue Oct 9 00:28:53 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h Thu Mar 14 21:35:53 2002 @@ -36,7 +36,7 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.15 2001/10/08 22:28:53 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.19 2002/03/14 20:35:53 mvojkovi Exp $ */ #ifndef __RIVA_HW_H__ #define __RIVA_HW_H__ #define RIVA_SW_VERSION 0x00010003 @@ -225,74 +225,6 @@ U032 MonochromeData01E; } RivaBitmap; /* - * 3D textured, Z buffered triangle. - */ -typedef volatile struct -{ - U032 reserved00[4]; -#if X_BYTE_ORDER == X_BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BC]; - U032 TextureOffset; - U032 TextureFormat; - U032 TextureFilter; - U032 FogColor; -/* This is a problem on LynxOS */ -#ifdef Control -#undef Control -#endif - U032 Control; - U032 AlphaTest; - U032 reserved02[0x339]; - U032 FogAndIndex; - U032 Color; - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - float TextureS; - float TextureT; -} RivaTexturedTriangle03; -typedef volatile struct -{ - U032 reserved00[4]; -#if X_BYTE_ORDER == X_BIG_ENDIAN - U032 FifoFree; -#else - U016 FifoFree; - U016 Nop; -#endif - U032 reserved01[0x0BB]; - U032 ColorKey; - U032 TextureOffset; - U032 TextureFormat; - U032 TextureFilter; - U032 Blend; -/* This is a problem on LynxOS */ -#ifdef Control -#undef Control -#endif - U032 Control; - U032 FogColor; - U032 reserved02[0x39]; - struct - { - float ScreenX; - float ScreenY; - float ScreenZ; - float EyeM; - U032 Color; - U032 Specular; - float TextureS; - float TextureT; - } Vertex[16]; - U032 DrawTriangle3D; -} RivaTexturedTriangle05; -/* * 2D line. */ typedef volatile struct @@ -375,6 +307,7 @@ */ U032 Architecture; U032 Version; + U032 Chipset; U032 CrystalFreqKHz; U032 RamAmountKBytes; U032 MaxVClockFreqKHz; @@ -385,11 +318,14 @@ U032 FifoFreeCount; U032 FifoEmptyCount; U032 CursorStart; + Bool flatPanel; + Bool twoHeads; /* * Non-FIFO registers. */ + volatile U032 *PCRTC0; volatile U032 *PCRTC; - volatile U032 *PRAMDAC; + volatile U032 *PRAMDAC0; volatile U032 *PFB; volatile U032 *PFIFO; volatile U032 *PGRAPH; @@ -399,12 +335,12 @@ volatile U032 *PRAMIN; volatile U032 *FIFO; volatile U032 *CURSOR; - volatile U032 *CURSORPOS; - volatile U032 *VBLANKENABLE; - volatile U032 *VBLANK; + volatile U008 *PCIO0; volatile U008 *PCIO; volatile U008 *PVIO; + volatile U008 *PDIO0; volatile U008 *PDIO; + volatile U032 *PRAMDAC; /* * Common chip functions. */ @@ -413,8 +349,6 @@ void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *); void (*SetStartAddress)(struct _riva_hw_inst *,U032); - void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032); - void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032); int (*ShowHideCursor)(struct _riva_hw_inst *,int); void (*LockUnlock)(struct _riva_hw_inst *, int); /* @@ -431,8 +365,6 @@ RivaScreenBlt *Blt; RivaBitmap *Bitmap; RivaLine *Line; - RivaTexturedTriangle03 *Tri03; - RivaTexturedTriangle05 *Tri05; } RIVA_HW_INST; /* * Extended mode state information. @@ -446,14 +378,19 @@ U032 repaint0; U032 repaint1; U032 screen; + U032 scale; U032 extra; U032 pixel; U032 horiz; U032 arbitration0; U032 arbitration1; U032 vpll; + U032 vpll2; U032 pllsel; U032 general; + U032 crtcOwner; + U032 head; + U032 head2; U032 config; U032 cursor0; U032 cursor1; diff -r -u xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h --- xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h Thu Sep 20 01:40:06 2001 +++ xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h Wed Jan 30 02:35:03 2002 @@ -36,7 +36,7 @@ |* those rights set forth herein. *| |* *| \***************************************************************************/ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.8 2001/09/19 23:40:06 mvojkovi Exp $ */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_tbl.h,v 1.9 2002/01/30 01:35:03 mvojkovi Exp $ */ /* @@ -634,180 +634,6 @@ {0x00000186, 0x000070E5}, {0x0000020C, 0x0E0D0D0D} }; -static unsigned nv10tri05TablePGRAPH[][2] = -{ - {(0x00000E00/4), 0x00000000}, - {(0x00000E04/4), 0x00000000}, - {(0x00000E08/4), 0x00000000}, - {(0x00000E0C/4), 0x00000000}, - {(0x00000E10/4), 0x00001000}, - {(0x00000E14/4), 0x00001000}, - {(0x00000E18/4), 0x4003ff80}, - {(0x00000E1C/4), 0x00000000}, - {(0x00000E20/4), 0x00000000}, - {(0x00000E24/4), 0x00000000}, - {(0x00000E28/4), 0x00000000}, - {(0x00000E2C/4), 0x00000000}, - {(0x00000E30/4), 0x00080008}, - {(0x00000E34/4), 0x00080008}, - {(0x00000E38/4), 0x00000000}, - {(0x00000E3C/4), 0x00000000}, - {(0x00000E40/4), 0x00000000}, - {(0x00000E44/4), 0x00000000}, - {(0x00000E48/4), 0x00000000}, - {(0x00000E4C/4), 0x00000000}, - {(0x00000E50/4), 0x00000000}, - {(0x00000E54/4), 0x00000000}, - {(0x00000E58/4), 0x00000000}, - {(0x00000E5C/4), 0x00000000}, - {(0x00000E60/4), 0x00000000}, - {(0x00000E64/4), 0x10000000}, - {(0x00000E68/4), 0x00000000}, - {(0x00000E6C/4), 0x00000000}, - {(0x00000E70/4), 0x00000000}, - {(0x00000E74/4), 0x00000000}, - {(0x00000E78/4), 0x00000000}, - {(0x00000E7C/4), 0x00000000}, - {(0x00000E80/4), 0x00000000}, - {(0x00000E84/4), 0x00000000}, - {(0x00000E88/4), 0x08000000}, - {(0x00000E8C/4), 0x00000000}, - {(0x00000E90/4), 0x00000000}, - {(0x00000E94/4), 0x00000000}, - {(0x00000E98/4), 0x00000000}, - {(0x00000E9C/4), 0x4B7FFFFF}, - {(0x00000EA0/4), 0x00000000}, - {(0x00000EA4/4), 0x00000000}, - {(0x00000EA8/4), 0x00000000}, - {(0x00000F00/4), 0x07FF0800}, - {(0x00000F04/4), 0x07FF0800}, - {(0x00000F08/4), 0x07FF0800}, - {(0x00000F0C/4), 0x07FF0800}, - {(0x00000F10/4), 0x07FF0800}, - {(0x00000F14/4), 0x07FF0800}, - {(0x00000F18/4), 0x07FF0800}, - {(0x00000F1C/4), 0x07FF0800}, - {(0x00000F20/4), 0x07FF0800}, - {(0x00000F24/4), 0x07FF0800}, - {(0x00000F28/4), 0x07FF0800}, - {(0x00000F2C/4), 0x07FF0800}, - {(0x00000F30/4), 0x07FF0800}, - {(0x00000F34/4), 0x07FF0800}, - {(0x00000F38/4), 0x07FF0800}, - {(0x00000F3C/4), 0x07FF0800}, - {(0x00000F40/4), 0x10000000}, - {(0x00000F44/4), 0x00000000}, - {(0x00000F50/4), 0x00006740}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006750}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F54/4), 0x40000000}, - {(0x00000F50/4), 0x00006760}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006770}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006780}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000067A0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AB0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AC0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006C10}, - {(0x00000F54/4), 0xBF800000}, - {(0x00000F50/4), 0x00007030}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007040}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007050}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007060}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007070}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007080}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00007090}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x000070A0}, - {(0x00000F54/4), 0x7149F2CA}, - {(0x00000F50/4), 0x00006A80}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x00006AA0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00000040}, - {(0x00000F54/4), 0x00000005}, - {(0x00000F50/4), 0x00006400}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x4B7FFFFF}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006410}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006420}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x00006430}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064C0}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F54/4), 0x477FFFFF}, - {(0x00000F54/4), 0x3F800000}, - {(0x00000F50/4), 0x000064D0}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0xC5000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064E0}, - {(0x00000F54/4), 0xC4FFF000}, - {(0x00000F54/4), 0xC4FFF000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F50/4), 0x000064F0}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F54/4), 0x00000000}, - {(0x00000F40/4), 0x30000000}, - {(0x00000F44/4), 0x00000004}, - {(0x00000F48/4), 0x10000000}, - {(0x00000F4C/4), 0x00000000} -}; static unsigned nv10TablePRAMIN[][2] = { {0x00000000, 0x80000010}, diff -r -u xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h --- xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h Wed Jan 16 03:00:43 2002 +++ xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h Wed Jan 16 03:00:43 2002 @@ -506,42 +506,47 @@ #define PCI_CHIP_BT849 0x0351 /* NVIDIA */ -#define PCI_CHIP_NV1 0x0008 -#define PCI_CHIP_DAC64 0x0009 -#define PCI_CHIP_TNT 0x0020 -#define PCI_CHIP_TNT2 0x0028 -#define PCI_CHIP_UTNT2 0x0029 -#define PCI_CHIP_VTNT2 0x002C -#define PCI_CHIP_UVTNT2 0x002D -#define PCI_CHIP_ITNT2 0x00A0 -#define PCI_CHIP_GEFORCE256 0x0100 -#define PCI_CHIP_GEFORCEDDR 0x0101 -#define PCI_CHIP_QUADRO 0x0103 -#define PCI_CHIP_GEFORCE2MX 0x0110 -#define PCI_CHIP_GEFORCE2MXDDR 0x0111 -#define PCI_CHIP_GEFORCE2GO 0x0112 -#define PCI_CHIP_QUADRO2MXR 0x0113 -#define PCI_CHIP_GEFORCE2GTS 0x0150 -#define PCI_CHIP_GEFORCE2GTS_1 0x0151 -#define PCI_CHIP_GEFORCE2ULTRA 0x0152 -#define PCI_CHIP_QUADRO2PRO 0x0153 -#define PCI_CHIP_0x0170 0x0170 -#define PCI_CHIP_0x0171 0x0171 -#define PCI_CHIP_0x0172 0x0172 -#define PCI_CHIP_0x0173 0x0173 -#define PCI_CHIP_0x0174 0x0174 -#define PCI_CHIP_0x0175 0x0175 -#define PCI_CHIP_0x0178 0x0178 -#define PCI_CHIP_0x017A 0x017A -#define PCI_CHIP_0x017B 0x017B -#define PCI_CHIP_0x017C 0x017C -#define PCI_CHIP_IGEFORCE2 0x01A0 -#define PCI_CHIP_GEFORCE3 0x0200 -#define PCI_CHIP_GEFORCE3_1 0x0201 -#define PCI_CHIP_GEFORCE3_2 0x0202 -#define PCI_CHIP_QUADRO_DDC 0x0203 -#define PCI_CHIP_0x0250 0x0250 -#define PCI_CHIP_0x0258 0x0258 +#define PCI_CHIP_NV1 0x0008 +#define PCI_CHIP_DAC64 0x0009 +#define PCI_CHIP_TNT 0x0020 +#define PCI_CHIP_TNT2 0x0028 +#define PCI_CHIP_UTNT2 0x0029 +#define PCI_CHIP_VTNT2 0x002C +#define PCI_CHIP_UVTNT2 0x002D +#define PCI_CHIP_ITNT2 0x00A0 +#define PCI_CHIP_GEFORCE_256 0x0100 +#define PCI_CHIP_GEFORCE_DDR 0x0101 +#define PCI_CHIP_QUADRO 0x0103 +#define PCI_CHIP_GEFORCE2_MX 0x0110 +#define PCI_CHIP_GEFORCE2_MX_100 0x0111 +#define PCI_CHIP_GEFORCE2_GO 0x0112 +#define PCI_CHIP_QUADRO2_MXR 0x0113 +#define PCI_CHIP_GEFORCE2_GTS 0x0150 +#define PCI_CHIP_GEFORCE2_TI 0x0151 +#define PCI_CHIP_GEFORCE2_ULTRA 0x0152 +#define PCI_CHIP_QUADRO2_PRO 0x0153 +#define PCI_CHIP_GEFORCE4_MX_460 0x0170 +#define PCI_CHIP_GEFORCE4_MX_440 0x0171 +#define PCI_CHIP_GEFORCE4_MX_420 0x0172 +#define PCI_CHIP_GEFORCE4_440_GO 0x0174 +#define PCI_CHIP_GEFORCE4_420_GO 0x0175 +#define PCI_CHIP_GEFORCE4_420_GO_M32 0x0176 +#define PCI_CHIP_QUADRO4_500XGL 0x0178 +#define PCI_CHIP_GEFORCE4_440_GO_M64 0x0179 +#define PCI_CHIP_QUADRO4_200 0x017A +#define PCI_CHIP_QUADRO4_550XGL 0x017B +#define PCI_CHIP_QUADRO4_500_GOGL 0x017C +#define PCI_CHIP_IGEFORCE2 0x01A0 +#define PCI_CHIP_GEFORCE3 0x0200 +#define PCI_CHIP_GEFORCE3_TI_200 0x0201 +#define PCI_CHIP_GEFORCE3_TI_500 0x0202 +#define PCI_CHIP_QUADRO_DCC 0x0203 +#define PCI_CHIP_GEFORCE4_TI_4600 0x0250 +#define PCI_CHIP_GEFORCE4_TI_4400 0x0251 +#define PCI_CHIP_GEFORCE4_TI_4200 0x0253 +#define PCI_CHIP_QUADRO4_900XGL 0x0258 +#define PCI_CHIP_QUADRO4_750XGL 0x0259 +#define PCI_CHIP_QUADRO4_700XGL 0x025B /* NVIDIA & SGS */ #define PCI_CHIP_RIVA128 0x0018 @@ -1308,42 +1313,47 @@ {0x0000, NULL,0}}}, #endif {PCI_VENDOR_NVIDIA, { - {PCI_CHIP_NV1, "NV1",0}, - {PCI_CHIP_DAC64, "DAC64",0}, - {PCI_CHIP_TNT, "RIVA TNT",0}, - {PCI_CHIP_TNT2, "RIVA TNT2/TNT2 Pro",0}, - {PCI_CHIP_UTNT2, "RIVA TNT2 Ultra",0}, - {PCI_CHIP_VTNT2, "Vanta",0}, - {PCI_CHIP_UVTNT2, "Riva TNT2 M64",0}, - {PCI_CHIP_ITNT2, "Aladdin TNT2",0}, - {PCI_CHIP_GEFORCE256, "GeForce 256",0}, - {PCI_CHIP_GEFORCEDDR, "GeForce DDR",0}, - {PCI_CHIP_QUADRO, "Quadro",0}, - {PCI_CHIP_GEFORCE2MX, "GeForce2 MX/MX 400",0}, - {PCI_CHIP_GEFORCE2MXDDR,"GeForce2 MX 100/200",0}, - {PCI_CHIP_GEFORCE2GO, "GeForce2 Go", 0}, - {PCI_CHIP_QUADRO2MXR, "Quadro2 MXR",0}, - {PCI_CHIP_GEFORCE2GTS, "GeForce2 GTS/Pro",0}, - {PCI_CHIP_GEFORCE2GTS_1,"GeForce2 Ti",0}, - {PCI_CHIP_GEFORCE2ULTRA,"GeForce2 Ultra",0}, - {PCI_CHIP_QUADRO2PRO, "Quadro2 Pro",0}, - {PCI_CHIP_0x0170, "0x0170",0}, - {PCI_CHIP_0x0171, "0x0171",0}, - {PCI_CHIP_0x0172, "0x0172",0}, - {PCI_CHIP_0x0173, "0x0173",0}, - {PCI_CHIP_0x0174, "0x0174",0}, - {PCI_CHIP_0x0175, "0x0175",0}, - {PCI_CHIP_0x0178, "0x0178",0}, - {PCI_CHIP_0x017A, "0x017A",0}, - {PCI_CHIP_0x017B, "0x017B",0}, - {PCI_CHIP_0x017C, "0x017C",0}, - {PCI_CHIP_IGEFORCE2, "GeForce2 Integrated",0}, - {PCI_CHIP_GEFORCE3, "GeForce3",0}, - {PCI_CHIP_GEFORCE3_1, "GeForce3 Ti 200",0}, - {PCI_CHIP_GEFORCE3_2, "GeForce3 Ti 500",0}, - {PCI_CHIP_QUADRO_DDC, "Quadro DDC",0}, - {PCI_CHIP_0x0250, "0x0250",0}, - {PCI_CHIP_0x0258, "0x0258",0}, + {PCI_CHIP_NV1, "NV1",0}, + {PCI_CHIP_DAC64, "DAC64",0}, + {PCI_CHIP_TNT, "RIVA TNT",0}, + {PCI_CHIP_TNT2, "RIVA TNT2/TNT2 Pro",0}, + {PCI_CHIP_UTNT2, "RIVA TNT2 Ultra",0}, + {PCI_CHIP_VTNT2, "Vanta",0}, + {PCI_CHIP_UVTNT2, "Riva TNT2 M64",0}, + {PCI_CHIP_ITNT2, "Aladdin TNT2",0}, + {PCI_CHIP_GEFORCE_256, "GeForce 256",0}, + {PCI_CHIP_GEFORCE_DDR, "GeForce DDR",0}, + {PCI_CHIP_QUADRO, "Quadro",0}, + {PCI_CHIP_GEFORCE2_MX, "GeForce2 MX/MX 400",0}, + {PCI_CHIP_GEFORCE2_MX_100, "GeForce2 MX 100/200",0}, + {PCI_CHIP_GEFORCE2_GO, "GeForce2 Go", 0}, + {PCI_CHIP_QUADRO2_MXR, "Quadro2 MXR",0}, + {PCI_CHIP_GEFORCE2_GTS, "GeForce2 GTS/Pro",0}, + {PCI_CHIP_GEFORCE2_TI, "GeForce2 Ti",0}, + {PCI_CHIP_GEFORCE2_ULTRA, "GeForce2 Ultra",0}, + {PCI_CHIP_QUADRO2_PRO, "Quadro2 Pro",0}, + {PCI_CHIP_GEFORCE4_MX_460, "GeForce4 MX 460",0}, + {PCI_CHIP_GEFORCE4_MX_440, "GeForce4 MX 440",0}, + {PCI_CHIP_GEFORCE4_MX_420, "GeForce4 MX 420",0}, + {PCI_CHIP_GEFORCE4_440_GO, "GeForce4 440 Go",0}, + {PCI_CHIP_GEFORCE4_420_GO, "GeForce4 420 Go",0}, + {PCI_CHIP_GEFORCE4_420_GO_M32,"GeForce4 420 Go M32",0}, + {PCI_CHIP_QUADRO4_500XGL, "Quadro4 500XGL",0}, + {PCI_CHIP_GEFORCE4_440_GO_M64,"GeForce4 440 Go M64",0}, + {PCI_CHIP_QUADRO4_200, "Quadro4 200/400NVS",0}, + {PCI_CHIP_QUADRO4_550XGL, "Quadro4 550XGL",0}, + {PCI_CHIP_QUADRO4_500_GOGL, "Quadro4 GoGL",0}, + {PCI_CHIP_IGEFORCE2, "GeForce2 Integrated",0}, + {PCI_CHIP_GEFORCE3, "GeForce3",0}, + {PCI_CHIP_GEFORCE3_TI_200, "GeForce3 Ti 200",0}, + {PCI_CHIP_GEFORCE3_TI_500, "GeForce3 Ti 500",0}, + {PCI_CHIP_QUADRO_DCC, "Quadro DCC",0}, + {PCI_CHIP_GEFORCE4_TI_4600, "GeForce4 Ti 4600",0}, + {PCI_CHIP_GEFORCE4_TI_4400, "GeForce4 Ti 4400",0}, + {PCI_CHIP_GEFORCE4_TI_4200, "GeForce4 Ti 4200",0}, + {PCI_CHIP_QUADRO4_900XGL, "Quadro4 900 XGL",0}, + {PCI_CHIP_QUADRO4_750XGL, "Quadro4 750 XGL",0}, + {PCI_CHIP_QUADRO4_700XGL, "Quadro4 700 XGL",0}, {0x0000, NULL,0}}}, {PCI_VENDOR_IMS, { {PCI_CHIP_IMSTT128, "TwinTurbo 128", 0},