Go to:
Gentoo Home
Documentation
Forums
Lists
Bugs
Planet
Store
Wiki
Get Gentoo!
Gentoo's Bugzilla – Attachment 897754 Details for
Bug 935047
sci-libs/rocBLAS-6.1.1 fails to compile
Home
|
New
–
[Ex]
|
Browse
|
Search
|
Privacy Policy
|
[?]
|
Reports
|
Requests
|
Help
|
New Account
|
Log In
[x]
|
Forgot Password
Login:
[x]
Additional failure build.log
rocBLAS-6.1.1.build.log (text/x-log), 60.05 KB, created by
MrSnivvel
on 2024-07-16 03:16:44 UTC
(
hide
)
Description:
Additional failure build.log
Filename:
MIME Type:
Creator:
MrSnivvel
Created:
2024-07-16 03:16:44 UTC
Size:
60.05 KB
patch
obsolete
>[32m * [39;49;00mPackage: sci-libs/rocBLAS-6.1.1:0/6.1 >[32m * [39;49;00mRepository: gentoo >[32m * [39;49;00mMaintainer: sci@gentoo.org gentoo@holzke.net,xgreenlandforwyy@gmail.com,lockalsash@gmail.com >[32m * [39;49;00mUSE: abi_x86_64 amd64 amdgpu_targets_gfx1012 elibc_glibc kernel_linux video_cards_amdgpu >[32m * [39;49;00mFEATURES: network-sandbox preserve-libs sandbox userpriv usersandbox > [32m*[0m Source directory (CMAKE_USE_DIR): "/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1" > [32m*[0m Build directory (BUILD_DIR): "/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build" > [32m*[0m Applying rocBLAS-5.4.2-cpp_lib_filesystem.patch ... >patching file clients/common/utility.cpp >Hunk #1 succeeded at 40 with fuzz 2 (offset 2 lines). >patching file clients/include/singletons.hpp >[A[260C [34;01m[ [32;01mok[34;01m ][0m > [32m*[0m Applying rocBLAS-5.4.2-add-missing-header.patch ... >[A[260C [34;01m[ [32;01mok[34;01m ][0m > [32m*[0m Applying rocBLAS-5.4.2-link-cblas.patch ... >patching file clients/CMakeLists.txt >Hunk #1 succeeded at 134 with fuzz 2 (offset 15 lines). >[A[260C [34;01m[ [32;01mok[34;01m ][0m > [32m*[0m Applying rocBLAS-6.0.2-expand-isa-compatibility.patch ... >[A[260C [34;01m[ [32;01mok[34;01m ][0m > [32m*[0m Hardcoded definition(s) removed in CMakeLists.txt: > [32m*[0m set( CMAKE_BUILD_TYPE Release CACHE STRING "Choose the type of build, optio > [32m*[0m SET( CMAKE_INSTALL_PREFIX "C:/hipSDK" CACHE PATH "Install path" FORCE ) > [32m*[0m Hardcoded definition(s) removed in clients/CMakeLists.txt: > [32m*[0m set( CMAKE_BUILD_TYPE Release CACHE STRING "Choose the type of build, optio > [32m*[0m Hardcoded definition(s) removed in deps/CMakeLists.txt: > [32m*[0m set( CMAKE_BUILD_TYPE Release CACHE STRING "Choose the type of build, optio >yes > [32m*[0m Source directory (CMAKE_USE_DIR): "/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1" > [32m*[0m Build directory (BUILD_DIR): "/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build" >cmake -C /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/gentoo_common_config.cmake -G Ninja -DCMAKE_INSTALL_PREFIX=/usr -DCMAKE_SKIP_RPATH=ON -DBUILD_FILE_REORG_BACKWARD_COMPATIBILITY=OFF -DROCM_SYMLINK_LIBS=OFF -DAMDGPU_TARGETS=gfx1012; -DBUILD_WITH_TENSILE=yes -DCMAKE_INSTALL_INCLUDEDIR=include/rocblas -DBUILD_CLIENTS_SAMPLES=OFF -DBUILD_CLIENTS_TESTS=no -DBUILD_CLIENTS_BENCHMARKS=no -DBUILD_WITH_PIP=OFF -DTensile_LOGIC=asm_full -DTensile_COMPILER=hipcc -DTensile_LIBRARY_FORMAT=msgpack -DTensile_CODE_OBJECT_VERSION=default -DTensile_ROOT=/usr/share/Tensile -DTensile_CPU_THREADS=48 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_TOOLCHAIN_FILE=/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/gentoo_toolchain.cmake /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1 >loading initial cache file /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/gentoo_common_config.cmake >-- The CXX compiler identification is Clang 18.1.8 >-- Detecting CXX compiler ABI info >-- Detecting CXX compiler ABI info - done >-- Check for working CXX compiler: /usr/bin/hipcc - skipped >-- Detecting CXX compile features >-- Detecting CXX compile features - done >-- Use hip-clang to build for amdgpu backend >-- Performing Test CMAKE_HAVE_LIBC_PTHREAD >-- Performing Test CMAKE_HAVE_LIBC_PTHREAD - Success >-- Found Threads: TRUE >-- Found Python3: /usr/bin/python3 (found version "3.12.4") found components: Interpreter >-- OS detected is gentoo >-- ROCM Platform Version: is not set, using default supported list >-- Performing Test COMPILER_HAS_TARGET_ID_gfx1012 >-- Performing Test COMPILER_HAS_TARGET_ID_gfx1012 - Success >-- The C compiler identification is GNU 14.1.1 >-- Detecting C compiler ABI info >-- Detecting C compiler ABI info - done >-- Check for working C compiler: /usr/bin/x86_64-pc-linux-gnu-gcc - skipped >-- Detecting C compile features >-- Detecting C compile features - done >-- Performing Test HIP_CLANG_SUPPORTS_PARALLEL_JOBS >-- Performing Test HIP_CLANG_SUPPORTS_PARALLEL_JOBS - Failed >[33mCMake Warning (dev) at /usr/share/cmake/Modules/CMakeFindDependencyMacro.cmake:76 (find_package): > Policy CMP0167 is not set: The FindBoost module is removed. Run "cmake > --help-policy CMP0167" for policy details. Use the cmake_policy command to > set the policy and suppress this warning. > >Call Stack (most recent call first): > /usr/lib64/cmake/msgpack-cxx/msgpack-cxx-config.cmake:40 (find_dependency) > /usr/share/Tensile/Source/lib/CMakeLists.txt:101 (find_package) >This warning is for project developers. Use -Wno-dev to suppress it. >[0m >-- Found Boost: /usr/lib64/cmake/Boost-1.85.0/BoostConfig.cmake (found version "1.85.0") >-- Using AMDGPU_TARGETS: gfx1012 >-- Tensile script: TensileCreateLibrary >-- Tensile_CREATE_COMMAND: TensileCreateLibrary;--merge-files;--separate-architectures;--lazy-library-loading;--no-short-file-names;--no-library-print-debug;--code-object-version=default;--cxx-compiler=hipcc;--jobs=48;--library-format=msgpack;--architecture=gfx1012;/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full;/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile;HIP >-- Tensile_MANIFEST_FILE_PATH: /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile/library/TensileManifest.txt >'TensileCreateLibrary' '--merge-files' '--separate-architectures' '--lazy-library-loading' '--no-short-file-names' '--no-library-print-debug' '--code-object-version=default' '--cxx-compiler=hipcc' '--jobs=48' '--library-format=msgpack' '--architecture=gfx1012' '/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full' '/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile' 'HIP' '--generate-manifest-and-exit' > >################################################################################ ># Tensile Create Library ># Detected local GPU with ISA: gfx1012 ># Found hipcc version 6.1.40092- > cap gfx000 gfx803 gfx900 gfx906 gfx908 gfx90a gfx940 gfx941 gfx942 gfx1010 gfx1011 gfx1012 gfx1030 gfx1031 gfx1100 gfx1101 gfx1102 > HasMFMA_bf16_1k 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > HasMFMA_i8_908 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 > HasMFMA_i8_940 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > HasAddLshl 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasAtomicAdd 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 > HasDirectToLdsDest 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > HasDirectToLdsNoDest 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 > HasExplicitCO 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasExplicitNC 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > HasGLCModifier 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 > HasLshlOr 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasMFMA 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 > HasSMulHi 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasWMMA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 > KernargPreloading 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > MaxLgkmcnt 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > MaxVmcnt 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > SupportedISA 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > SupportedSource 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasMFMA_b8 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > HasMFMA_constSrc 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > v_dot2_f32_f16 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 > v_dot2c_f32_f16 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 > v_fma_f16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_fmac_f16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > v_mac_f16 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 > v_pk_fma_f16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_pk_fmac_f16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > v_fma_f32 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_fma_mix_f32 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_fmac_f32 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_mac_f32 0 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 > v_mad_mix_f32 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > HasMFMA_f64 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > v_fma_f64 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasMFMA_f8 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > VOP3v_dot4_i32_i8 0 0 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 > v_dot4_i32_i8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > v_dot4c_i32_i8 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 >HasMFMA_bf16_original 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 > HasMFMA_vgpr 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > HasMFMA_xf32 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > ArchAccUnifiedRegs 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > CMPXWritesSGPR 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 > CrosslaneWait 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > ForceStoreSC1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 > HasAccCD 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > HasEccHalf 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 > HasWave32 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > InstRename 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 > SeparateVscnt 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > VgprBank 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > Waitcnt0Disabled 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 >Tensile::WARNING: Global parameter WriteMasterSolutionIndex = False unrecognized. ># CodeObjectVersion from TensileCreateLibrary: default ># CxxCompiler from TensileCreateLibrary: hipcc ># Architecture from TensileCreateLibrary: gfx1012 ># LibraryFormat from TensileCreateLibrary: msgpack ># LibraryLogicFiles: ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_ZB_GB.yaml >Reading logic files: Launching 32 threads for 108 tasks... >Reading logic files: Done. > Processing logic data: 0%| | 0/108 [00:00<?, ?it/s] Processing logic data: 18%|ââ | 19/108 [00:00<00:00, 186.42it/s] Processing logic data: 38%|ââââ | 41/108 [00:00<00:00, 206.00it/s] Processing logic data: 74%|ââââââââ | 80/108 [00:00<00:00, 289.59it/s] Processing logic data: 100%|ââââââââââ| 108/108 [00:00<00:00, 258.96it/s] >-- *** NOTE: blas2/rocblas_ger_kernels.cpp is compiled with the verbose flag -v for QC purposes. >-- ***** rocblas_library_settings: rocblas >-- Performing Test COMPILER_HAS_HIDDEN_VISIBILITY >-- Performing Test COMPILER_HAS_HIDDEN_VISIBILITY - Success >-- Performing Test COMPILER_HAS_HIDDEN_INLINE_VISIBILITY >-- Performing Test COMPILER_HAS_HIDDEN_INLINE_VISIBILITY - Success >-- Performing Test COMPILER_HAS_DEPRECATED_ATTR >-- Performing Test COMPILER_HAS_DEPRECATED_ATTR - Success >-- Found Doxygen: /usr/bin/doxygen (found version "1.10.0") found components: doxygen missing components: dot >-- <<< Gentoo configuration >>> >Build type RelWithDebInfo >Install path /usr >Compiler flags: >C -march=native -O2 -pipe >C++ -march=native -O2 -pipe -D__HIP_HCC_COMPAT_MODE__=1 >Linker flags: >Executable -Wl,-O1 -Wl,--as-needed -Wl,-z,pack-relative-relocs >Module -Wl,-O1 -Wl,--as-needed -Wl,-z,pack-relative-relocs >Shared -Wl,-O1 -Wl,--as-needed -Wl,-z,pack-relative-relocs > >-- Configuring done (59.7s) >-- Generating done (0.1s) >-- Build files have been written to: /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build > [32m*[0m Source directory (CMAKE_USE_DIR): "/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1" > [32m*[0m Build directory (BUILD_DIR): "/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build" >ninja -v -j48 -l0 >[0/2] /usr/bin/cmake -P /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/CMakeFiles/VerifyGlobs.cmake >[0/335] cd /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/library/src && TensileCreateLibrary --merge-files --separate-architectures --lazy-library-loading --no-short-file-names --no-library-print-debug --code-object-version=default --cxx-compiler=hipcc --jobs=48 --library-format=msgpack --architecture=gfx1012 /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile HIP > >################################################################################ ># Tensile Create Library ># Detected local GPU with ISA: gfx1012 ># Found hipcc version 6.1.40092- > cap gfx000 gfx803 gfx900 gfx906 gfx908 gfx90a gfx940 gfx941 gfx942 gfx1010 gfx1011 gfx1012 gfx1030 gfx1031 gfx1100 gfx1101 gfx1102 > HasMFMA_bf16_1k 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > HasMFMA_i8_908 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 > HasMFMA_i8_940 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > HasAddLshl 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasAtomicAdd 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 > HasDirectToLdsDest 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > HasDirectToLdsNoDest 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 > HasExplicitCO 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasExplicitNC 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > HasGLCModifier 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 > HasLshlOr 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasMFMA 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 > HasSMulHi 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasWMMA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 > KernargPreloading 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > MaxLgkmcnt 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > MaxVmcnt 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > SupportedISA 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > SupportedSource 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasMFMA_b8 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > HasMFMA_constSrc 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > v_dot2_f32_f16 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 > v_dot2c_f32_f16 0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 > v_fma_f16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_fmac_f16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > v_mac_f16 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 > v_pk_fma_f16 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_pk_fmac_f16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > v_fma_f32 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_fma_mix_f32 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_fmac_f32 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > v_mac_f32 0 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 > v_mad_mix_f32 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > HasMFMA_f64 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > v_fma_f64 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 > HasMFMA_f8 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > VOP3v_dot4_i32_i8 0 0 0 1 1 1 1 1 1 0 1 1 1 1 0 0 0 > v_dot4_i32_i8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 > v_dot4c_i32_i8 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 0 0 >HasMFMA_bf16_original 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 > HasMFMA_vgpr 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > HasMFMA_xf32 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > ArchAccUnifiedRegs 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > CMPXWritesSGPR 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 > CrosslaneWait 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 > ForceStoreSC1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 > HasAccCD 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 > HasEccHalf 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 > HasWave32 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > InstRename 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 > SeparateVscnt 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > VgprBank 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 > Waitcnt0Disabled 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 >Tensile::WARNING: Global parameter WriteMasterSolutionIndex = False unrecognized. ># CodeObjectVersion from TensileCreateLibrary: default ># CxxCompiler from TensileCreateLibrary: hipcc ># Architecture from TensileCreateLibrary: gfx1012 ># LibraryFormat from TensileCreateLibrary: msgpack ># LibraryLogicFiles: ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_BjlkC_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bjlk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Ailk_Bljk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_BjlkC_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bjlk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_AlikC_Bljk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_BjlkC_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bjlk_ZB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_4xi8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_4xi8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BBS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BBS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_BSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_CB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_CB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_DB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_DB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HHS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HHS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HSS_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_HSS_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_I8II_BH.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_I8II_BH_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_SB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_SB_GB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_ZB.yaml ># /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full/hip/hip_Cijk_Alik_Bljk_ZB_GB.yaml >Reading logic files: Launching 32 threads for 108 tasks... >Reading logic files: Done. > Processing logic data: 0% 0/108 [00:00<?, ?it/s] Processing logic data: 18% 19/108 [00:00<00:00, 182.71it/s] Processing logic data: 38% 41/108 [00:00<00:00, 199.42it/s] Processing logic data: 74% 80/108 [00:00<00:00, 281.01it/s] Processing logic data: 100% 108/108 [00:00<00:00, 252.13it/s] ># Writing Custom CMake ># Writing Kernels... >Generating kernels: Launching 32 threads... >Generating kernels: Done. > 0it [00:00, ?it/s] 0it [00:00, ?it/s] >Compiling source kernels: Launching 32 threads... >hipcc: /usr/bin/hipcc --genco -D__HIP_HCC_COMPAT_MODE__=1 -I /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile -Xoffload-linker --build-id --offload-arch=gfx1012 /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile/Kernels.cpp -c -o /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/library/src/build_tmp/TENSILE/code_object_tmp/Kernels.o >/usr/lib/llvm/18/bin/clang-offload-bundler -type=o -targets=hipv4-amdgcn-amd-amdhsa--gfx1012 -input=/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/library/src/build_tmp/TENSILE/code_object_tmp/Kernels.o -output=/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/library/src/build_tmp/TENSILE/code_object_tmp/Kernels.so-000-gfx1012.hsaco -unbundle >Compiling source kernels: Done. ># Kernel Building elapsed time = 0.9 secs >codeObjectFiles: ['/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile/library/Kernels.so-000-gfx1012.hsaco'] >sourceLibPaths + asmLibPaths: ['/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile/library/Kernels.so-000-gfx1012.hsaco'] >Traceback (most recent call last): > File "/usr/lib/python-exec/python3.12/TensileCreateLibrary", line 8, in <module> > sys.exit(TensileCreateLibrary()) > ^^^^^^^^^^^^^^^^^^^^^^ > File "/usr/lib/python3.12/site-packages/Tensile/TensileCreateLibrary.py", line 1301, in TensileCreateLibrary > theMasterLibrary = list(masterLibraries.values())[0] > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^^^ >IndexError: list index out of range >[2/335] cd /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src && /usr/bin/python3 template-proto.py /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/ /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/ /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas2/ /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas1/ > /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/include/rocblas/internal/rocblas-exported-proto.hpp >[31mFAILED: [0mTensile/library/Kernels.so-000-gfx1012.hsaco /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile/library/Kernels.so-000-gfx1012.hsaco >cd /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/library/src && TensileCreateLibrary --merge-files --separate-architectures --lazy-library-loading --no-short-file-names --no-library-print-debug --code-object-version=default --cxx-compiler=hipcc --jobs=48 --library-format=msgpack --architecture=gfx1012 /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1/library/src/blas3/Tensile/Logic/asm_full /var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build/Tensile HIP >ninja: build stopped: subcommand failed. > [31;01m*[0m ERROR: sci-libs/rocBLAS-6.1.1::gentoo failed (compile phase): > [31;01m*[0m ninja -v -j48 -l0 failed > [31;01m*[0m > [31;01m*[0m Call stack: > [31;01m*[0m ebuild.sh, line 136: Called src_compile > [31;01m*[0m environment, line 2333: Called cmake_src_compile > [31;01m*[0m environment, line 916: Called cmake_build > [31;01m*[0m environment, line 883: Called eninja > [31;01m*[0m environment, line 1428: Called die > [31;01m*[0m The specific snippet of code: > [31;01m*[0m "$@" || die -n "${*} failed" > [31;01m*[0m > [31;01m*[0m If you need support, post the output of `emerge --info '=sci-libs/rocBLAS-6.1.1::gentoo'`, > [31;01m*[0m the complete build log and the output of `emerge -pqv '=sci-libs/rocBLAS-6.1.1::gentoo'`. > [31;01m*[0m The complete build log is located at '/var/tmp/portage/sci-libs/rocBLAS-6.1.1/temp/build.log'. > [31;01m*[0m The ebuild environment file is located at '/var/tmp/portage/sci-libs/rocBLAS-6.1.1/temp/environment'. > [31;01m*[0m Working directory: '/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1_build' > [31;01m*[0m S: '/var/tmp/portage/sci-libs/rocBLAS-6.1.1/work/rocBLAS-rocm-6.1.1'
<b>You cannot view the attachment while viewing its details because your browser does not support IFRAMEs. <a href="attachment.cgi?id=897754">View the attachment on a separate page</a>.</b>
View Attachment As Raw
Actions:
View
Attachments on
bug 935047
:
896559
|
896560
| 897754 |
897755
