[patch] Patch for chromium-58.0.3029.19

chromium-58.0.3029.19_mm256_setr_m128.patch (text/plain), 3.44 KB, created by Vitaliy Batichko on 2017-03-19 16:15:55 UTC

--- chromium-58.0.3029.19/third_party/skia/src/opts/SkNx_sse.h	2017-03-19 15:26:45.487712508 +0200
+++ chromium-58.0.3029.19/third_party/skia/src/opts/SkNx_sse.h	2017-03-19 15:27:16.639687726 +0200
@@ -486,7 +486,7 @@
     __m128i fVec;
 };
 
-#if SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#if SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__))
 
     template <>
     class SkNx<8, uint8_t> {
--- chromium-58.0.3029.19/third_party/skia/src/opts/SkRasterPipeline_opts.h	2017-03-19 15:27:36.776671630 +0200
+++ chromium-58.0.3029.19/third_party/skia/src/opts/SkRasterPipeline_opts.h	2017-03-19 15:28:11.398643825 +0200
@@ -23,7 +23,7 @@
 
 namespace {
 
-#if SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#if SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__))
     static constexpr int N = 8;
 #else
     static constexpr int N = 4;
@@ -201,7 +201,7 @@
     v.store(dst);
 }
 
-#if !defined(SKNX_NO_SIMD) && SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#if !defined(SKNX_NO_SIMD) && (SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__)))
     SI __m256i mask(size_t tail) {
         static const int masks[][8] = {
             {~0,~0,~0,~0, ~0,~0,~0,~0 },  // remember, tail == 0 ~~> load all N
--- chromium-58.0.3029.19/third_party/skia/src/core/SkCpu.h	2017-03-19 15:30:39.465552769 +0200
+++ chromium-58.0.3029.19/third_party/skia/src/core/SkCpu.h	2017-03-19 15:30:14.002561410 +0200
@@ -80,7 +80,7 @@
     features |= AVX;
     #endif
     // F16C goes here if we add SK_CPU_SSE_LEVEL_F16C
-    #if SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+    #if SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__))
     features |= AVX2;
     #endif
     // FMA doesn't fit neatly into this total ordering.
--- chromium-58.0.3029.19/third_party/skia/src/core/SkHalf.h	2017-03-19 15:31:21.859537181 +0200
+++ chromium-58.0.3029.19/third_party/skia/src/core/SkHalf.h	2017-03-19 15:30:49.585549182 +0200
@@ -11,7 +11,7 @@
 #include "SkNx.h"
 #include "SkTypes.h"
 
-#if !defined(_MSC_VER) && SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#if !defined(_MSC_VER) && (SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__)))
     #include <x86intrin.h>
 #endif
 
@@ -90,7 +90,7 @@
 }
 
 static inline Sk8f SkHalfToFloat_finite_ftz(const Sk8h& hs) {
-#if !defined(SKNX_NO_SIMD) && SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#if !defined(SKNX_NO_SIMD) && (SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__)))
     return _mm256_cvtph_ps(hs.fVec);
 
 #else
@@ -103,7 +103,7 @@
 }
 
 static inline Sk8h SkFloatToHalf_finite_ftz(const Sk8f& fs) {
-#if !defined(SKNX_NO_SIMD) && SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#if !defined(SKNX_NO_SIMD) && (SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__)))
     return _mm256_cvtps_ph(fs.fVec, _MM_FROUND_CUR_DIRECTION);
 
 #else
--- chromium-58.0.3029.19/third_party/skia/src/core/SkOpts.cpp	2017-03-19 15:31:55.621523762 +0200
+++ chromium-58.0.3029.19/third_party/skia/src/core/SkOpts.cpp	2017-03-19 15:31:42.527529067 +0200
@@ -16,7 +16,7 @@
     #else
         #define SK_OPTS_NS neon
     #endif
-#elif SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2
+#elif SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX2 && (!defined(__GNUC__) || defined(__clang__))
     #define SK_OPTS_NS avx2
 #elif SK_CPU_SSE_LEVEL >= SK_CPU_SSE_LEVEL_AVX
     #define SK_OPTS_NS avx