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Gentoo's Bugzilla – Attachment 286241 Details for
Bug 382725
crossdev fails to build powerpc64-unknown-linux-newlib during GCC stage 1
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gcc 4.6.1 diff
gcc-4.6.1.diff (text/plain), 7.06 KB, created by
Andrew Udvare
on 2011-09-12 17:33:48 UTC
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Description:
gcc 4.6.1 diff
Filename:
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Creator:
Andrew Udvare
Created:
2011-09-12 17:33:48 UTC
Size:
7.06 KB
patch
obsolete
>diff -NurpP --minimal gcc-4.6.1//config.sub gcc-4.6.1-xenon//config.sub >--- gcc-4.6.1//config.sub 2010-05-25 09:22:07.000000000 -0400 >+++ gcc-4.6.1-xenon//config.sub 2011-08-21 13:37:29.016458785 -0400 >@@ -962,6 +962,10 @@ case $basic_machine in > ppc64le-* | powerpc64little-*) > basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` > ;; >+ xenon) >+ basic_machine=powerpc64-unknown >+ os=-linux-gnu >+ ;; > ps2) > basic_machine=i386-ibm > ;; >diff -NurpP --minimal gcc-4.6.1//gcc/config/rs6000/altivec.md gcc-4.6.1-xenon//gcc/config/rs6000/altivec.md >--- gcc-4.6.1//gcc/config/rs6000/altivec.md 2011-04-28 18:39:59.000000000 -0400 >+++ gcc-4.6.1-xenon//gcc/config/rs6000/altivec.md 2011-08-21 13:55:47.672551230 -0400 >@@ -642,7 +642,7 @@ > (match_operand:VIshort 2 "register_operand" "v") > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMU))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumu<VI_char>m %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -652,7 +652,7 @@ > (match_operand:VIshort 2 "register_operand" "v") > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMM))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumm<VI_char>m %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -662,7 +662,7 @@ > (match_operand:V8HI 2 "register_operand" "v") > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMSHM))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumshm %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -673,7 +673,7 @@ > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMUHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumuhs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -684,7 +684,7 @@ > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMSHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumshs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -745,7 +745,7 @@ > (match_operand:V8HI 3 "register_operand" "v")] > UNSPEC_VMHADDSHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmhaddshs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -756,7 +756,7 @@ > (match_operand:V8HI 3 "register_operand" "v")] > UNSPEC_VMHRADDSHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmhraddshs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -766,7 +766,7 @@ > (match_operand:V8HI 2 "register_operand" "v") > (match_operand:V8HI 3 "register_operand" "v")] > UNSPEC_VMLADDUHM))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmladduhm %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -977,7 +977,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULEUB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmuleub %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -986,7 +986,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULESB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulesb %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -995,7 +995,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULEUH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmuleuh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1004,7 +1004,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULESH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulesh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1013,7 +1013,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULOUB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmuloub %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1022,7 +1022,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULOSB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulosb %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1031,7 +1031,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULOUH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulouh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1040,7 +1040,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULOSH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulosh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1256,7 +1256,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUM4UBS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsum4ubs %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1266,7 +1266,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUM4S)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsum4s<VI_char>s %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1276,7 +1276,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUM2SWS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsum2sws %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1286,7 +1286,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUMSWS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsumsws %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >diff -NurpP --minimal gcc-4.6.1//libstdc++-v3/configure gcc-4.6.1-xenon//libstdc++-v3/configure >--- gcc-4.6.1//libstdc++-v3/configure 2011-05-25 20:15:58.000000000 -0400 >+++ gcc-4.6.1-xenon//libstdc++-v3/configure 2011-08-21 13:45:28.112976307 -0400 >@@ -10790,6 +10790,7 @@ linux* | k*bsd*-gnu | kopensolaris*-gnu) > finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' > shlibpath_var=LD_LIBRARY_PATH > shlibpath_overrides_runpath=no >+ lt_cv_shlibpath_overrides_runpath=no > > # Some binutils ld are patched to set DT_RUNPATH > if test "${lt_cv_shlibpath_overrides_runpath+set}" = set; then :
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bug 382725
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