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Gentoo's Bugzilla – Attachment 286239 Details for
Bug 382725
crossdev fails to build powerpc64-unknown-linux-newlib during GCC stage 1
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gcc diff
gcc-4.6.0.diff (text/plain), 7.31 KB, created by
Andrew Udvare
on 2011-09-12 17:33:35 UTC
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Description:
gcc diff
Filename:
MIME Type:
Creator:
Andrew Udvare
Created:
2011-09-12 17:33:35 UTC
Size:
7.31 KB
patch
obsolete
>--- gcc-4.6.0/config.sub 2010-05-25 15:22:07.000000000 +0200 >+++ gcc-4.6.0/config.sub 2011-05-08 20:01:59.131496120 +0200 >@@ -962,6 +962,10 @@ > ppc64le-* | powerpc64little-*) > basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` > ;; >+ xenon) >+ basic_machine=powerpc64-unknown >+ os=-linux-gnu >+ ;; > ps2) > basic_machine=i386-ibm > ;; >--- gcc-4.6.0/libstdc++-v3/configure 2011-03-08 01:04:05.000000000 +0100 >+++ gcc-4.6.0/libstdc++-v3/configure 2011-05-08 20:03:15.371557434 +0200 >@@ -10790,6 +10790,7 @@ > finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' > shlibpath_var=LD_LIBRARY_PATH > shlibpath_overrides_runpath=no >+ lt_cv_shlibpath_overrides_runpath=no > > # Some binutils ld are patched to set DT_RUNPATH > if test "${lt_cv_shlibpath_overrides_runpath+set}" = set; then : >--- gcc-4.6.0/gcc/config/rs6000/altivec.md 2011-02-03 06:42:19.000000000 +0100 >+++ gcc-4.6.0/gcc/config/rs6000/altivec.md 2011-06-28 20:46:28.580429716 +0200 >@@ -584,7 +584,7 @@ > > two = gen_reg_rtx (V8HImode); > convert_move (two, operands[2], 0); >- >+ > small_swap = gen_reg_rtx (V8HImode); > convert_move (small_swap, swap, 0); > >@@ -642,7 +642,7 @@ > (match_operand:VIshort 2 "register_operand" "v") > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMU))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumu<VI_char>m %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -652,7 +652,7 @@ > (match_operand:VIshort 2 "register_operand" "v") > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMM))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumm<VI_char>m %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -662,7 +662,7 @@ > (match_operand:V8HI 2 "register_operand" "v") > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMSHM))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumshm %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -673,7 +673,7 @@ > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMUHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumuhs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -684,7 +684,7 @@ > (match_operand:V4SI 3 "register_operand" "v")] > UNSPEC_VMSUMSHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmsumshs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -745,7 +745,7 @@ > (match_operand:V8HI 3 "register_operand" "v")] > UNSPEC_VMHADDSHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmhaddshs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -756,7 +756,7 @@ > (match_operand:V8HI 3 "register_operand" "v")] > UNSPEC_VMHRADDSHS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmhraddshs %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -766,7 +766,7 @@ > (match_operand:V8HI 2 "register_operand" "v") > (match_operand:V8HI 3 "register_operand" "v")] > UNSPEC_VMLADDUHM))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmladduhm %0,%1,%2,%3" > [(set_attr "type" "veccomplex")]) > >@@ -977,7 +977,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULEUB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmuleub %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -986,7 +986,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULESB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulesb %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -995,7 +995,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULEUH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmuleuh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1004,7 +1004,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULESH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulesh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1013,7 +1013,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULOUB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmuloub %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1022,7 +1022,7 @@ > (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") > (match_operand:V16QI 2 "register_operand" "v")] > UNSPEC_VMULOSB))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulosb %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1031,7 +1031,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULOUH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulouh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1040,7 +1040,7 @@ > (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") > (match_operand:V8HI 2 "register_operand" "v")] > UNSPEC_VMULOSH))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vmulosh %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1256,7 +1256,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUM4UBS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsum4ubs %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1266,7 +1266,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUM4S)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsum4s<VI_char>s %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1276,7 +1276,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUM2SWS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsum2sws %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1286,7 +1286,7 @@ > (match_operand:V4SI 2 "register_operand" "v")] > UNSPEC_VSUMSWS)) > (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))] >- "TARGET_ALTIVEC" >+ "(TARGET_ALTIVEC && 0)" > "vsumsws %0,%1,%2" > [(set_attr "type" "veccomplex")]) > >@@ -1898,7 +1898,7 @@ > vzero = gen_reg_rtx (GET_MODE (operands[0])); > emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx)); > emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1])); >- >+ > DONE; > }") > >@@ -2044,7 +2044,7 @@ > UNSPEC_VUPKHUB))] > "TARGET_ALTIVEC" > " >-{ >+{ > rtx vzero = gen_reg_rtx (V8HImode); > rtx mask = gen_reg_rtx (V16QImode); > rtvec v = rtvec_alloc (16);
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